CN117276410B - Passivation contact solar cell and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Life Sciences & Earth Sciences (AREA)
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Abstract
The embodiment of the application relates to the technical field of solar cells, and provides a passivation contact solar cell and a preparation method thereof, wherein the method comprises the following steps: forming a tunneling layer and an initial silicon layer which are sequentially stacked on the surface of a substrate, wherein the material of the initial silicon layer comprises a polycrystalline structure and an amorphous structure; placing the substrate with the tunneling layer and the initial silicon layer into a diffusion chamber; performing a first temperature raising process to raise the temperature of the diffusion chamber to a first preset temperature; annealing treatment is carried out in the diffusion chamber at a first preset temperature so as to convert the initial silicon layer into a polycrystalline silicon layer; and doping the polysilicon layer, and introducing source gas into the diffusion chamber in the doping process to convert the polysilicon layer into a doped polysilicon layer. The passivation contact solar cell and the preparation method thereof are at least beneficial to improving the performance of the solar cell.
Description
Technical Field
The embodiment of the application relates to the technical field of solar cells, in particular to a passivation contact solar cell and a preparation method thereof.
Background
The fossil energy has the advantages of air pollution and limited reserves, and solar energy has the advantages of cleanness, no pollution, abundant resources and the like, so the solar energy is gradually becoming a core clean energy for replacing the fossil energy, and the solar cell becomes the development center of gravity for the utilization of the clean energy due to the good photoelectric conversion efficiency of the solar cell.
In order to improve the efficiency of the solar cell, a passivation contact structure can be formed on the front side and/or the back side of the solar cell, and the field passivation and/or chemical passivation capability of the passivation contact structure is utilized to improve the carrier tunneling capability of the solar cell and reduce the recombination of carriers on the surface of the substrate. For example, tunnel oxide passivation has applications in Contact solar cells (Tunnel Oxide Passivated Contact solar cell, TOPCon), tall Wen Yizhi junction cells (Heterojunction with Intrinsic Thin-layer, HJT), and Back Contact solar cells (BC). However, defects are easily formed when manufacturing the passivation contact structure, resulting in degradation of the performance of the solar cell.
Disclosure of Invention
The embodiment of the application provides a passivation contact solar cell and a preparation method thereof, which are at least beneficial to improving the performance of the solar cell.
According to some embodiments of the present application, an aspect of an embodiment of the present application provides a method for preparing a passivation contact solar cell, including: forming a tunneling layer and an initial silicon layer which are sequentially stacked on the surface of a substrate, wherein the material of the initial silicon layer comprises a polycrystalline structure and an amorphous structure; placing the substrate with the tunneling layer and the initial silicon layer into a diffusion chamber; performing a first temperature raising process to raise the temperature of the diffusion chamber to a first preset temperature; annealing treatment is carried out in the diffusion chamber at a first preset temperature so as to convert the initial silicon layer into a polycrystalline silicon layer; and doping the polysilicon layer, and introducing source gas into the diffusion chamber in the doping process to convert the polysilicon layer into a doped polysilicon layer.
In some embodiments, the annealing process comprises: and maintaining the temperature of the diffusion chamber to be a first preset temperature within a first preset time, wherein the range of the first preset time is 10-60 min.
In some embodiments, the first predetermined temperature ranges from 800 ℃ to 1000 ℃.
In some embodiments, the first temperature ramp up process has a ramp up rate of 3 ℃/min to 10 ℃/min.
In some embodiments, the initial silicon layer is formed using a low pressure chemical vapor deposition process.
In some embodiments, the doping process includes: performing cooling treatment to reduce the temperature of the diffusion chamber from a first preset temperature to a second preset temperature; performing deposition treatment to introduce source gas into the diffusion chamber at a second preset temperature, and keeping the temperature of the diffusion chamber at the second preset temperature within a second preset time; and performing junction pushing treatment to increase the temperature of the diffusion chamber from the second preset temperature to a third preset temperature, and keeping the temperature of the diffusion chamber at the third preset temperature within the third preset time.
In some embodiments, the third preset temperature is higher than the first preset temperature.
In some embodiments, after performing the push junction process, further comprising: and performing post junction pushing treatment to increase the temperature of the diffusion chamber from the third preset temperature to the fourth preset temperature, and keeping the temperature of the diffusion chamber at the fourth preset temperature within the fourth preset time.
In some embodiments, the second preset temperature ranges from 750 ℃ to 950 ℃; the second preset time is 10-60 min.
In some embodiments, after the first temperature increasing process, before the annealing process, further comprising: and carrying out leak detection treatment to detect whether the leak rate of the diffusion chamber is less than or equal to 5mbar/min.
According to some embodiments of the present application, another embodiment of the present application provides a passivation contact solar cell, which is formed by using the preparation method of the passivation contact solar cell in any one of the above embodiments, and includes: a substrate; the tunneling layer is positioned on the surface of the substrate; the doped polysilicon layer is positioned on the surface of the tunneling layer, which is far away from the substrate.
In some embodiments, the dopant atom concentration in the doped polysilicon layer is greater than or equal to 3E+20 atoms/cm 3 。
The technical scheme provided by the embodiment of the application has at least the following advantages:
according to the preparation method of the passivation contact solar cell, after the tunneling layer and the initial silicon layer are formed on the substrate, the substrate with the tunneling layer and the initial silicon layer is placed into the diffusion chamber for first temperature rising treatment, and annealing treatment is carried out at a first preset temperature, so that the initial silicon layer is converted into the polycrystalline silicon layer. Therefore, the diffusion chamber required by the existing diffusion process can be utilized to anneal the initial silicon layer, new equipment is not required to be added, and the process cost is not increased. After annealing treatment, doping treatment is directly carried out without changing a chamber, so that the problem that the crystallinity of the polysilicon layer is changed in the process of cooling, changing the chamber and then heating up is avoided, and meanwhile, the process efficiency is improved. The annealing step is performed firstly, so that the mixed crystal phase structure formed by the polycrystalline structure and the amorphous structure of the initial crystalline silicon layer is converted into a uniform polycrystalline structure, and compared with the initial silicon layer, the converted polycrystalline silicon layer has higher crystallinity, so that doping atoms are not easy to gather in the polycrystalline silicon layer when doping treatment is performed by further introducing source gas, more holes in the formed doped polycrystalline silicon are avoided, and the stability and efficiency of the passivation contact solar cell are improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings that are required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a passivation contact structure according to an embodiment of the present application;
FIG. 2 is a laser microscope image of an initial silicon layer and a doped polysilicon layer according to one embodiment of the present application;
fig. 3 is a flowchart of a method for manufacturing a passivation contact solar cell according to an embodiment of the present disclosure;
fig. 4 is a laser microscope image of doped polysilicon in two passivation contact solar cells according to an embodiment of the present application.
Detailed Description
Fig. 1 is a schematic diagram of a passivation contact structure according to an embodiment of the present application.
Referring to fig. 1, the passivation contact structure is composed of a tunneling layer 101 and a doped polysilicon layer 102 on the surface of a substrate 100, and the tunneling layer 101 contacts with the substrate 100 to neutralize dangling bonds on the surface of the substrate 100 for excellent chemical passivation; the doped polysilicon layer 102 has a fermi level difference with the substrate 100, and causes band bending on the surface of the substrate 100, so that the passage of minority carriers (also called minority carriers) can be more effectively blocked, the transmission of the majority carriers (also called majority carriers) can not be affected, and the selective collection of the carriers can be realized.
The passivation contact structure is generally formed by depositing a tunneling layer 101 and an initial silicon layer on the surface of a substrate 100, doping the initial silicon layer, and activating the initial silicon layer through an annealing process, wherein the crystallinity of the initial silicon layer changes during the annealing process, and the initial silicon layer is converted into a uniform polycrystalline structure from a mixed crystal phase structure composed of a polycrystalline structure and an amorphous structure, so that the initial silicon layer is converted into a doped polysilicon layer 102.
Fig. 2 is a laser microscope image of an initial silicon layer and a doped polysilicon layer according to an embodiment of the present application. Here, (a) in fig. 2 shows an initial silicon layer which is not subjected to doping treatment and annealing treatment, and (B) in fig. 2 shows doped polysilicon which has been subjected to doping treatment and annealing treatment.
Comparing fig. 2 (a) with fig. 2 (B), it is found that the initial silicon layer which is not subjected to the doping treatment and the annealing treatment is relatively free of holes, after the initial silicon layer is converted into the doped polysilicon layer 102, more holes are formed on the surface of the doped polysilicon layer 102, so that in the subsequent cleaning or etching process, the cleaning solution or etching solution can contact the tunneling layer 101 through the holes, which results in the tunneling layer 101 being damaged to affect the passivation contact structure effect, and further results in the performance of the solar cell being damaged. This is because the initial silicon layer includes a polycrystalline structure and an amorphous structure, and the inter-lattice space between the polycrystalline structures in the initial silicon layer is large, so that the doping atoms are easy to gather in the space during the doping process, and thus the doped polysilicon 103 formed after annealing has many holes.
An embodiment of the application provides a preparation method of a passivation contact solar cell, which is at least beneficial to improving the performance of the solar cell.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 3 is a flowchart of a method for manufacturing a passivation contact solar cell according to an embodiment of the present application.
Referring to fig. 3, a method of manufacturing a passivation contact solar cell includes:
step 11: and forming a tunneling layer and an initial silicon layer which are sequentially stacked on the surface of the substrate, wherein the material of the initial silicon layer comprises a polycrystalline structure and an amorphous structure.
In some embodiments, the substrate may be an elemental semiconductor material. The elemental semiconductor material may be composed of a single element, and may be silicon or germanium, for example. Alternatively, the elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystal state and an amorphous state, referred to as a microcrystalline state), and for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.
In some embodiments, the material of the substrate may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenium, and the like.
The substrate may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In some embodiments, the substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any of v group elements such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, and arsenic (As) element. The P-type semiconductor substrate is doped with a P-type element, and the P-type doped element may be any one of group iii elements such as boron (B) element, aluminum (Al) element, gallium (Ga) element, and indium (In) element.
In some embodiments, the substrate may have opposite front and back sides. If the passivation contact solar cell is a single-sided cell, the front side of the substrate may be used as a light receiving surface for receiving incident light, and the back side may be used as a back side. If the passivation contact solar cell is a double-sided cell, both the front and back sides of the substrate can be used as light receiving surfaces, which can be used to receive incident light.
In some embodiments, a texturing process may be performed on at least one of the front or back surfaces of the substrate to form a textured surface on at least one of the front or back surfaces of the substrate, so that absorption and utilization of incident light by the front and back surfaces of the substrate may be enhanced. For example, the pile surface may be a pyramid-structured pile surface.
If the passivation contact solar cell is a single-sided cell, a suede surface can be formed on the light receiving surface of the substrate, and the back light surface of the substrate can be a polished surface, i.e. the back light surface of the substrate is flatter than the light receiving surface. In the case of a single-sided battery, a textured surface may be formed on both the light-receiving surface and the back surface of the substrate.
If the solar cell is a double sided cell, a textured surface may be formed on both the front and back sides of the substrate.
In some embodiments, the material of the tunneling layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.
The tunneling layer is positioned on the surface of the substrate, can play a role in chemical passivation, can saturate dangling bonds on the surface of the substrate due to the existence of interface state defects on the surface of the substrate, reduces the defect state density on the surface of the substrate, reduces the recombination center on the surface of the substrate to reduce the carrier recombination rate, ensures that the interface state density on the surface of the substrate is larger, increases the interface state density to promote the recombination of photo-generated carriers, and increases the filling factor, the short-circuit current and the open-circuit voltage of the solar cell so as to improve the photoelectric conversion efficiency of the solar cell.
In some embodiments, the process of forming the tunneling layer may employ a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.
In some embodiments, the initial silicon layer may be at least one of amorphous silicon or polysilicon.
In some embodiments, the process of forming the initial silicon layer may employ a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition process (Physical Vapor Deposition, PVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), or the like.
In some embodiments, the initial silicon layer may be formed using a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, LPCVD).
In some embodiments, the deposition process employed in forming the initial silicon layer may employ a deposition temperature of 500-700 ℃, e.g., the deposition temperature may be 500 ℃, 530 ℃, 560 ℃, 590 ℃, 610 ℃, 640 ℃, 670 ℃, or 700 ℃. The product temperature is in the range of 500-700 ℃, which is favorable for the initial silicon layer to have higher conductivity and carrier mobility.
Step 12: the substrate with the tunneling layer and the initial silicon layer formed is placed in a diffusion chamber.
In some embodiments, after placing the substrate with the tunneling layer and the initial silicon layer into the diffusion chamber, the pressure within the diffusion chamber is reduced to a negative pressure of 50mbar to 200mbar, e.g., 50mbar, 55mbar, 70mbar, 100mbar, 130mbar, 160mbar, 180mbar, or 200mbar.
In some embodiments, after the pressure in the diffusion chamber is reduced to a negative pressure of 50 mbar-200 mbar, a leak detection process may be performed to detect whether the leak rate of the diffusion chamber is less than or equal to 3mbar/min, e.g., the leak rate may be 3mbar/min, 2mbar/min, 1mbar/min, or 0.5mbar/min. That is, before the diffusion chamber is heated, the diffusion chamber is subjected to leak detection treatment, and the leak rate needs to be in a proper range to perform subsequent process steps so as to ensure that the gas environment in the diffusion chamber is in a controllable range, thereby being beneficial to the subsequent process.
If the leak rate of the diffusion chamber is less than or equal to 3mbar/min, the subsequent process steps can be performed; if the leak rate of the diffusion chamber is greater than 3mbar/min, the substrate with the tunneling layer and the initial silicon layer formed needs to be removed to inspect the diffusion chamber.
Step 13: a first temperature raising process is performed to raise the temperature of the diffusion chamber to a first preset temperature.
In some embodiments, the pressure in the diffusion chamber may be reduced to a negative pressure of 50 to 200mbar, e.g. 50, 55, 70, 100, 130, 160, 180 or 200mbar, during the first warming process.
In some embodiments, a leak detection process may be performed after the first elevated temperature process and before the annealing process to detect whether the leak rate of the diffusion chamber is less than or equal to 5mbar/min, e.g., the leak rate may be 5mbar/min, 4.3mbar/min, 3.5mbar/min, 2.4mbar/min, 1.6mbar/min, or 0.8mbar/min. After the diffusion chamber is subjected to the first heating treatment, the diffusion chamber is subjected to the leak detection treatment, and the environment in the diffusion chamber is closer to the actual condition of the follow-up process, so that the leak rate accuracy is higher, and the corresponding judgment and operation can be made in time.
If the leak rate of the diffusion chamber is less than or equal to 5mbar/min, the subsequent process steps can be performed; if the leak rate of the diffusion chamber is greater than 5mbar/min, the substrate with the tunneling layer and the initial silicon layer is required to be taken out to overhaul the diffusion chamber, so that the defect that the subsequent process cannot be performed or the obtained product yield is low due to poor working environment of the diffusion chamber is avoided.
In some embodiments, the heating rate of the first heating process may be 3 ℃/min to 10 ℃/min, for example, the heating rate of the first heating process may be 3 ℃/min, 4 ℃/min, 5 ℃/min, 6 ℃/min, 7 ℃/min, 8 ℃/min, 9 ℃/min, or 10 ℃/min. The temperature rising rate of the first temperature rising treatment is too high, so that the size distribution of the grain structure in the converted polycrystalline silicon layer is easy to be uneven; the temperature increase rate of the first temperature increase treatment is too slow, which tends to cause low process efficiency, and therefore the temperature increase rate of the first temperature increase treatment needs to be adjusted within an appropriate range.
Step 14: and performing annealing treatment in the diffusion chamber at a first preset temperature to convert the initial silicon layer into a polycrystalline silicon layer. And at a first preset temperature, the amorphous structure and the polycrystalline structure in the initial silicon layer are recombined to be converted into a polycrystalline silicon layer formed by the polycrystalline structure with higher density.
If the initial silicon layer is a polysilicon material, the temperature required to deposit the initial silicon layer is relatively high. In the polycrystalline silicon material, the polycrystalline structure is more than the amorphous structure, the size of the polycrystalline structure is larger, the size difference of different grain structures is larger, the interfaces among the grain structures are more, and the conductivity of the initial silicon layer is lower easily. Through carrying out annealing treatment at a first preset temperature, the polycrystalline structures in the polycrystalline silicon material can be recombined to form polycrystalline structures with smaller grain structure size difference and uniform grain structure size distribution, and the amorphous structure is converted into the polycrystalline structure to form a polycrystalline silicon layer with higher density.
If the initial silicon layer is an amorphous silicon material, the temperature required to deposit the initial silicon layer is lower. In the amorphous silicon material, the amorphous structure is more than the polycrystalline structure, the gaps among the polycrystalline structures are larger, the aggregation of doping atoms is easy to cause, and the doped polycrystalline silicon with holes is easy to form in the subsequent doping treatment. Therefore, at the first preset temperature, the initial silicon layer is annealed, so that the amorphous structure in the amorphous silicon material is converted into a polycrystalline structure, and a polycrystalline silicon layer with higher density is formed.
In some embodiments, the annealing process comprises: maintaining the temperature of the diffusion chamber at a first preset temperature within a first preset time, wherein the first preset time ranges from 10min to 60min, for example, the first preset time may be 10min, 15min, 20min, 25min, 30min, 35min, 40min, 45min, 50min, 55min or 60min. The initial silicon layer cannot be sufficiently converted into a polysilicon layer when the first preset time is too short; the first preset time is too long, so that the grain size in the multi-layer silicon layer is larger, the interfaces among the corresponding grains are more, and the conductivity of the polycrystalline silicon layer is lower.
In some embodiments, the first preset temperature ranges from 800 ℃ to 1000 ℃, for example, the first preset temperature may be 800 ℃, 830 ℃, 850 ℃, 880 ℃, 900 ℃, 920 ℃, 960 ℃, 990 ℃, or 1000 ℃. Too low a temperature may result in a slow or even impossible transformation of the amorphous structure in the initial silicon layer into the polycrystalline structure, and too high a temperature may easily result in the silicon structure in the initial silicon layer being destroyed, affecting the electronic properties of the initial silicon layer, and therefore the first preset temperature needs to be within a proper range.
In some embodiments, the first preset temperature and the first preset time may be adjusted adaptively, for example, if the first preset temperature is higher, the first preset time may be reduced appropriately; in the case that the first preset time is long, the first preset temperature may be appropriately lowered.
Step 15: and doping the polysilicon layer, and introducing source gas into the diffusion chamber in the doping process to convert the polysilicon layer into a doped polysilicon layer.
The doped polysilicon layer can have a field passivation effect, a built-in electric field can be formed in the direction of the self-doped polysilicon layer pointing to the substrate, so that minority carriers escape, the concentration of minority carriers is reduced, the carrier recombination rate at the interface of the substrate is reduced, the open-circuit voltage, the short-circuit current and the filling factor of the solar cell are increased, and the photoelectric conversion efficiency of the solar cell is improved.
In some embodiments, if the substrate has an N-type doping element, the doping element in the doped polysilicon layer is an N-type doping element; if the substrate has a P-type doping element, the doping element in the doped polysilicon layer is the P-type doping element. That is, the doping element type in the doped polysilicon layer is the same as the doping element type in the substrate.
In some embodiments, if the doping element in the doped polysilicon is a P-type doping element, the source gas may include trimethyl borate, tripropyl borate, boron tribromide, or anhydrous trimethyl borate, etc., and the source gas decomposes boron oxide to react with silicon on the surface of the polysilicon layer to produce borosilicate glass, and then boron atoms diffuse into the polysilicon layer, thus forming a doped polysilicon layer doped with the P-type element; if the doping element in the doped polysilicon is an N-type doping element, the source gas may include phosphorus oxychloride, the source gas decomposes phosphorus pentoxide to react with silicon on the surface of the polysilicon layer to produce phosphosilicate glass, and then phosphorus atoms diffuse into the polysilicon layer, thus forming an N-type doped polysilicon layer.
In some embodiments, the polysilicon layer may be doped at a first preset temperature. For example, a source gas is introduced into the diffusion chamber at a first predetermined temperature to react the dopant atoms with silicon on the surface of the polysilicon layer while diffusing the dopant atoms into the polysilicon layer, thereby converting the polysilicon layer into a doped polysilicon layer.
In some embodiments, the doping process may include: performing cooling treatment to reduce the temperature of the diffusion chamber from a first preset temperature to a second preset temperature; performing deposition treatment to introduce source gas into the diffusion chamber at a second preset temperature, and keeping the temperature of the diffusion chamber at the second preset temperature within a second preset time; and performing junction pushing treatment to increase the temperature of the diffusion chamber from the second preset temperature to a third preset temperature, and keeping the temperature of the diffusion chamber at the third preset temperature within the third preset time.
That is, the temperature is reduced and the deposition is performed first, so that the polysilicon layer with partial thickness is reacted with the source gas to form the initial doped polysilicon layer with higher doping concentration, and then the temperature is raised and the junction pushing treatment is performed, so that the doping atoms in the initial doped polysilicon layer diffuse into the polysilicon layer, and finally the polysilicon layer is completely converted into the doped polysilicon layer. Therefore, the reaction degree of the source gas and the polysilicon layer is controllable at a lower temperature, which is favorable for controlling the concentration and the advancing depth of doping atoms, and the problem that the field passivation effect is reduced due to the fact that the doping atoms penetrate through the tunneling layer due to uncontrolled diffusion degree is avoided.
In some embodiments, the cooling process may be a natural cooling, i.e., without heating the diffusion chamber, so that the temperature of the diffusion chamber naturally cools to a second predetermined temperature. In some embodiments, the cooling process may also be cooled using a refrigeration device.
In some embodiments, the second preset temperature may range from 750 ℃ to 950 ℃, for example, the second preset temperature may be 750 ℃, 780 ℃, 800 ℃, 830 ℃, 860 ℃, 890 ℃, 910 ℃, or 950 ℃. In some embodiments, the second preset time may be 10min to 60min, for example, the second preset time may be 10min, 15min, 20min, 25min, 30min, 35min, 40min, 45min, 50min, 55min, or 60min.
In some embodiments, the third preset temperature may be higher than the first preset temperature. After the annealing treatment, the initial silicon layer is converted into a polysilicon layer, and the density and crystallinity of the polysilicon layer are higher than those of the initial silicon layer, and in order to make the doping atoms diffuse into the polysilicon layer with higher density more easily, a higher junction pushing temperature can be set.
In some embodiments, the third preset temperature may range from 800 ℃ to 1000 ℃, for example, the third preset temperature may be 800 ℃, 830 ℃, 850 ℃, 880 ℃, 900 ℃, 920 ℃, 960 ℃, 990 ℃, or 1000 ℃.
In some embodiments, the third preset time may be 10min to 60min, for example, the third preset time may be 10min, 15min, 20min, 25min, 30min, 35min, 40min, 45min, 50min, 55min, or 60min.
In some embodiments, the third preset temperature may also be no higher than the first preset temperature. And adjusting the third preset temperature and the third preset time to enable the doping atoms to diffuse to the surface of the polycrystalline silicon layer, which is in contact with the tunneling layer.
In some embodiments, after performing the knot pushing process, the method may further include: and performing post junction pushing treatment to increase the temperature of the diffusion chamber from the third preset temperature to the fourth preset temperature, and keeping the temperature of the diffusion chamber at the fourth preset temperature within the fourth preset time.
That is, the doping atoms can be diffused to the surface of the polysilicon layer in contact with the tunneling layer through a plurality of push-junction processes, and the doping atom concentration in the finally formed doped polysilicon layer is within a desired range. Therefore, the depth of the doping atoms can be gradually pushed into the polysilicon layer through multiple times of junction pushing, and the depth of each pushing is in a controllable range, so that the problem that the doping atoms penetrate through the tunneling layer due to too deep pushing depth is avoided.
In some embodiments, the fourth preset temperature may range from 800 ℃ to 1000 ℃, for example, the fourth preset temperature may be 800 ℃, 830 ℃, 850 ℃, 880 ℃, 900 ℃, 920 ℃, 960 ℃, 990 ℃, or 1000 ℃.
In some embodiments, the fourth preset time may be 10min to 60min, for example, the fourth preset time may be 10min, 15min, 20min, 25min, 30min, 35min, 40min, 45min, 50min, 55min, or 60min.
According to the preparation method of the passivation contact solar cell, after the tunneling layer and the initial silicon layer are formed on the substrate, the substrate with the tunneling layer and the initial silicon layer is placed into the diffusion chamber for first temperature rising treatment, and annealing treatment is carried out at a first preset temperature, so that the initial silicon layer is converted into the polycrystalline silicon layer. Therefore, the diffusion chamber required by the existing diffusion process can be utilized to anneal the initial silicon layer, new equipment is not required to be added, and the process cost is not increased. After annealing treatment, doping treatment is directly carried out without changing a chamber, so that the problem that the crystallinity of the polysilicon layer is changed in the process of cooling, changing the chamber and then heating up is avoided, and meanwhile, the process efficiency is improved. The annealing step is performed firstly, so that the mixed crystal phase structure formed by the polycrystalline structure and the amorphous structure of the initial crystalline silicon layer is converted into a uniform polycrystalline structure, and compared with the initial silicon layer, the converted polycrystalline silicon layer has higher crystallinity, so that doping atoms are not easy to gather in the polycrystalline silicon layer when doping treatment is performed by further introducing source gas, more holes in the formed doped polycrystalline silicon are avoided, and the stability and efficiency of the passivation contact solar cell are improved.
Another embodiment of the present application provides a passivation contact solar cell, which may be formed by using the method for manufacturing a passivation contact solar cell provided in the foregoing embodiment, so as to improve performance of the passivation contact solar cell. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted.
The passivation contact solar cell includes: a substrate; the tunneling layer is positioned on the surface of the substrate; the doped polysilicon layer is positioned on the surface of the tunneling layer, which is far away from the substrate.
The tunneling layer is positioned on the surface of the substrate, so that the effect of chemical passivation can be achieved, the tunneling layer can saturate dangling bonds on the surface of the substrate due to the existence of interface state defects on the surface of the substrate, the defect state density on the surface of the substrate is reduced, the recombination center on the surface of the substrate is reduced to reduce the carrier recombination rate, the interface state density on the surface of the substrate is higher, the recombination of photo-generated carriers can be promoted due to the increase of the interface state density, and the filling factor, the short-circuit current and the open-circuit voltage of the solar cell are increased so as to improve the photoelectric conversion efficiency of the solar cell; the doped polysilicon layer can have a field passivation effect, a built-in electric field can be formed in the direction of the self-doped polysilicon layer pointing to the substrate, so that minority carriers escape, the concentration of minority carriers is reduced, the carrier recombination rate at the interface of the substrate is reduced, the open-circuit voltage, the short-circuit current and the filling factor of the solar cell are increased, and the photoelectric conversion efficiency of the solar cell is improved.
In some embodiments, the passivation contact solar cell may be a tunnel oxide passivation contact solar cell, a high Wen Yizhi junction solar cell, or a back contact solar cell.
In some embodiments, the thickness of the tunneling layer may be 1nm to 3nm, such as 1nm, 1.2nm, 1.5nm, 1.8nm, 2.0nm, 2.3nm, 2.6nm, 2.8nm, or 3nm, in a direction perpendicular to the substrate surface.
In some embodiments, the thickness of the doped polysilicon layer may be 5nm to 200nm, such as 5nm, 10nm, 30nm, 60nm, 100nm, 130nm, 150nm, 180nm, 200nm, in a direction perpendicular to the substrate surface.
Fig. 4 is a laser microscope image of doped polysilicon in two passivation contact solar cells according to an embodiment of the present application. The doped polysilicon shown in fig. 4 (C) is formed by performing a doping treatment on the initial silicon layer and then performing an annealing process to convert the initial silicon layer, and the doped polysilicon shown in fig. 4 (D) is formed by performing an annealing treatment on the initial silicon layer and then performing a doping treatment to convert the initial silicon layer (i.e., the method for manufacturing the passivation contact solar cell provided in the above embodiment).
The initial silicon layers employed in fig. 4 are all amorphous silicon and are formed using the same process preparation. As can be seen from the comparison of (C) in fig. 4 and (D) in fig. 4, the surface of the doped polysilicon layer formed by the passivation contact solar cell manufacturing method provided in the above-described embodiment has almost no holes. In addition, according to the cell performance test, the minority carrier lifetime of the doped polysilicon in the passivation contact solar cell corresponding to (D) in fig. 4 is 1000us higher than the minority carrier lifetime of the doped polysilicon in the passivation contact solar cell corresponding to (C) in fig. 4; the cell conversion efficiency of the passivation contact solar cell corresponding to (D) in fig. 4 is improved by 0.2% compared to that of the passivation contact solar cell corresponding to (C) in fig. 4; the open circuit voltage of the passivation contact solar cell corresponding to (D) in fig. 4 is increased by 3mV from that of the passivation contact solar cell corresponding to (C) in fig. 4; the fill factor of the passivation contact solar cell corresponding to (D) in fig. 4 is increased by 0.1% compared to that of the passivation contact solar cell corresponding to (C) in fig. 4.
Therefore, the doped polysilicon layer formed by the preparation method of the passivation contact solar cell provided in the embodiment can not only avoid the problem of generating holes, but also improve the performance of the passivation contact solar cell.
In some embodiments, the concentration of doping atoms in the doped polysilicon layer formed by the method for manufacturing a passivated contact solar cell provided in the above embodiments is 3E+20atom/cm or more 3 For example 3E+20 atoms/cm 3 、3.5E+20atom/cm 3 、4E+20atom/cm 3 、4.5E+20atom/cm 3 、5E+20atom/cm 3 Or 5.5E+20atom/cm 3 Etc. Wherein the concentration of the dopant atoms may refer to the average concentration of the doped polysilicon layer at a plurality of different locations; alternatively, it may refer to the concentration per unit volume at any location in the doped polysilicon layer. In the doped polysilicon layer formed by the preparation method of the passivation contact solar cell provided in the embodiment, the doping atom concentration of each position is relatively uniform.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application.
Claims (9)
1. A method of manufacturing a passivated contact solar cell comprising:
forming a tunneling layer and an initial silicon layer which are sequentially stacked on the surface of a substrate, wherein the material of the initial silicon layer comprises a polycrystalline structure and an amorphous structure;
placing the substrate formed with the tunneling layer and the initial silicon layer into a diffusion chamber;
performing a first temperature raising process to raise the temperature of the diffusion chamber to a first preset temperature;
and performing an annealing treatment in the diffusion chamber for a first preset time at the first preset temperature to convert the initial silicon layer into a polysilicon layer, wherein the annealing treatment comprises: maintaining the temperature of the diffusion chamber to be the first preset temperature within the first preset time, wherein the range of the first preset time is 10-60 min, and the range of the first preset temperature is 800-1000 ℃;
doping the polysilicon layer, and introducing source gas into the diffusion chamber in the doping process so as to convert the polysilicon layer into a doped polysilicon layer; the doping treatment includes: performing cooling treatment to reduce the temperature of the diffusion chamber from the first preset temperature to a second preset temperature; performing deposition treatment to introduce the source gas into the diffusion chamber at the second preset temperature, and keeping the temperature of the diffusion chamber at the second preset temperature within a second preset time; and performing junction pushing treatment to increase the temperature of the diffusion chamber from the second preset temperature to a third preset temperature, and keeping the temperature of the diffusion chamber at the third preset temperature within a third preset time.
2. The method for manufacturing a passivation contact solar cell according to claim 1, wherein the temperature rising rate of the first temperature rising treatment is 3 ℃/min to 10 ℃/min.
3. The method of claim 1, wherein the initial silicon layer is formed by a low pressure chemical vapor deposition process.
4. The method of claim 1, wherein the third predetermined temperature is higher than the first predetermined temperature.
5. The method of manufacturing a passivated contact solar cell according to claim 1, further comprising, after the junction pushing treatment:
and performing post junction pushing treatment to increase the temperature of the diffusion chamber from the third preset temperature to a fourth preset temperature, and keeping the temperature of the diffusion chamber at the fourth preset temperature within a fourth preset time.
6. The method of claim 1, wherein the second preset temperature is in the range of 750 ℃ to 950 ℃; the second preset time is 10-60 min.
7. The method for manufacturing a passivated contact solar cell according to claim 1, characterized by further comprising, after the first temperature increasing treatment and before the annealing treatment: and performing leak detection treatment to detect whether the leak rate of the diffusion chamber is less than or equal to 5mbar/min.
8. A passivated contact solar cell characterized in that it is formed by the method for manufacturing a passivated contact solar cell according to any of claims 1-7, comprising:
a substrate;
the tunneling layer is positioned on the surface of the substrate;
and the doped polysilicon layer is positioned on the surface of the tunneling layer far away from the substrate.
9. The passivated contact solar cell of claim 8 wherein the doped polysilicon layer has a doping atomic concentration of 3e+20 atoms/cm or more 3 。
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