CN117276100A - Electronic chip bonding method and chip bonding piece - Google Patents
Electronic chip bonding method and chip bonding piece Download PDFInfo
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- CN117276100A CN117276100A CN202311289969.0A CN202311289969A CN117276100A CN 117276100 A CN117276100 A CN 117276100A CN 202311289969 A CN202311289969 A CN 202311289969A CN 117276100 A CN117276100 A CN 117276100A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The application provides an electronic chip bonding method and a chip bonding piece, wherein the method is used for sticking a chip on the surface of a packaging substrate, a circuit is arranged on the surface of the packaging substrate, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes; the method comprises the following steps: coating insulating glue on the circuit river channel, and placing the chip in the insulating glue; the electrodes of the chip face the packaging substrate, and the electrodes of the chip correspond to the circuit; and connecting the circuit with the electrode of the corresponding chip through an additive manufacturing mode. This application passes through the insulating glue with flip chip and bonds with package substrate, has solved the easy fracture of bonding wire and the not good problem of heat dissipation to form the electricity with chip electrode and circuit and be connected, need not form the solder ball on the chip bonding pad, avoid appearing the bad problem of solder joint, thereby improve reliability and the life-span of product.
Description
Technical Field
The present disclosure relates to the field of chips, and more particularly, to an electronic chip bonding method and a chip bonding member.
Background
As a post-process of semiconductor fabrication, a packaging process includes Back Grinding (Back Bonding), dicing (Dicing), die Bonding (Die Bonding), wire Bonding (Wire Bonding), molding (Molding), and the like.
Among them, the chip bonding process may adhere chips cut from a wafer to a package substrate (a lead frame or a printed circuit board) after a dicing process. Bonding processes can be classified into conventional methods and advanced methods. Conventional methods employ chip Bonding (or die attach) and Wire Bonding (Wire Bonding), while advanced methods employ flip chip Bonding (Flip Chip Bonding) techniques. Flip chip bonding technology combines chip bonding with wire bonding and connects the chip and the substrate by forming bumps (bumps) on the chip pads.
In the chip bonding process, an adhesive is first dispensed onto the package substrate. Next, the chip is placed on the substrate with its top surface facing upwards. In contrast, flip chip bonding is a more advanced technique, in which small bumps called "Solder balls" are first attached to the chip pads, and then the top of the chip is placed down on the substrate for bonding. Accordingly, various problems may occur in the existing die bonding process, such as wire breakage, die breakage, poor solder joints, etc., which may affect the reliability and lifetime of the product.
Disclosure of Invention
In view of the foregoing, the present application has been developed to provide an electronic chip bonding method and chip bonding member that overcomes the foregoing or at least partially solves the foregoing, including:
an electronic chip bonding method is used for sticking a chip on the surface of a packaging substrate, wherein a circuit is arranged on the surface of the packaging substrate, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes;
the method comprises the following steps:
coating insulating glue on the circuit river channel, and placing the chip in the insulating glue; the electrodes of the chip face the packaging substrate, and the electrodes of the chip correspond to the circuit;
and connecting the circuit with the electrode of the corresponding chip through an additive manufacturing mode.
Further, the step of connecting the circuit with the electrode of the corresponding chip by the additive manufacturing method includes:
the circuit is thickened by additive manufacturing and is electrically connected with the corresponding electrode of the chip.
Further, the step of connecting the circuit with the electrode of the corresponding chip by the additive manufacturing method includes:
and thickening the circuit and the electrode of the corresponding chip to form electric connection with each other through an additive manufacturing mode.
Further, the step of thickening the circuit by additive manufacturing and forming an electrical connection with the electrode of the corresponding chip includes:
coating a photosensitive material on the surface of the circuit, exposing and developing to expose a first target area of the circuit;
thickening the circuit on the surface of the first target area by an additive manufacturing mode;
and removing the photosensitive material.
Further, the step of coating a photosensitive material on the surface of the circuit, exposing and developing to expose the first target area of the circuit includes:
coating a photosensitive material on the surface of the circuit to form a first photosensitive mask layer and exposing the first photosensitive mask layer to form the first target area;
and removing the first photosensitive mask layer at the corresponding position through development, and exposing the first target area.
Further, the step of simultaneously thickening the circuit and the corresponding electrode of the chip to form an electrical connection with each other by an additive manufacturing method includes:
coating photosensitive materials on the surfaces of the circuits and the surfaces of the corresponding electrodes, and exposing and developing to expose a second target area of the circuits and a third target area of the electrodes;
thickening the circuit on the surface of the second target area by an additive manufacturing mode, and thickening the corresponding electrode on the surface of the third target area by an additive manufacturing mode;
and removing the photosensitive material on the circuit surface and the electrode surface.
Further, the step of coating a photosensitive material on the surface of the circuit and the corresponding electrode surface, exposing and developing to expose the second target area of the circuit and the third target area of the electrode, includes:
coating a photosensitive material on the surface of the circuit to form a second photosensitive mask layer and exposing the photosensitive material to form a second target area, and coating a photosensitive material on the surface of the electrode to form a third photosensitive mask layer and exposing the photosensitive material to form a third target area;
and removing the second photosensitive mask layer at the corresponding position through development to expose the second target area, and removing the third photosensitive mask layer at the corresponding position through development to expose the third target area.
Further, the chip electrode is 8-12 microns from the package substrate.
Further, the additive manufacturing mode comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and electroless plating.
A chip bonding part prepared by the electronic chip bonding method according to any one of the above, comprising an insulating adhesive layer, the chip and the packaging substrate;
the surface of the packaging substrate is provided with circuits, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes;
the insulating adhesive layer is arranged on the circuit river channel, the chip is arranged on the surface of the insulating adhesive layer, and the electrode of the chip is electrically connected with the circuit of the packaging substrate.
The application has the following advantages:
in the embodiment of the present application, compared to the problem that in the chip bonding process in the prior art, bonding wire breakage, chip breakage, bad welding spots and the like may occur to affect the reliability of the product, the present application provides a solution of a new chip bonding method, which specifically includes: the chip is used for being stuck to the surface of the packaging substrate, a circuit is arranged on the surface of the packaging substrate, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes; the method comprises the following steps: coating insulating glue on the circuit river channel, and placing the chip in the insulating glue; the electrodes of the chip face the packaging substrate, and the electrodes of the chip correspond to the circuit; and connecting the circuit with the electrode of the corresponding chip through an additive manufacturing mode. This application passes through the insulating glue with flip chip and bonds with package substrate, has solved the easy fracture of bonding wire and the not good problem of heat dissipation to form the electricity with chip electrode and circuit and be connected, need not form the solder ball on the chip bonding pad, avoid appearing the bad problem of solder joint, thereby improve reliability and the life-span of product.
Drawings
For a clearer description of the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method for bonding an electronic chip according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for bonding an electronic chip according to an embodiment of the present application;
FIG. 3 is a process flow diagram of an electronic chip bonding method according to an embodiment of the present disclosure;
fig. 4 is a process flow diagram of an electronic chip bonding method according to an embodiment of the present application.
Reference numerals in the drawings of the specification are as follows:
1. a chip; 11. an electrode; 2. packaging a substrate; 21. a circuit; 22. a circuit river channel; 3. and (5) packaging glue.
Detailed Description
In order to make the objects, features and advantages of the present application more comprehensible, the present application is described in further detail below with reference to the accompanying drawings and detailed description. It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The inventors found by analyzing the prior art that: the conventional chip bonding method is a forward bonding method, and is easy to have the problems of bond wire fracture and poor heat dissipation, and the advanced chip bonding method adopts flip chip bonding, so that although the problems of the conventional bonding method can be avoided, the problems of poor welding spots are easy to occur because the solder ball bumps are formed on the chip bonding pads for bonding, and therefore, the conventional chip bonding method needs to be improved.
In any embodiment of the present invention, the present invention is used to attach the chip to the surface of the package substrate. Before bonding, designing a circuit diagram, converting the circuit diagram into a PCB design, then manufacturing a PCB mask, wherein the mask comprises holes for the circuit design, then applying bonding pads and wires on a substrate, and finally welding a component to the substrate, so that a required circuit can be manufactured on the surface of the packaging substrate according to the design; wherein, be equipped with the circuit river course between the adjacent circuit, the chip is equipped with the electrode.
As an example, two electrodes are arranged on the same side of the chip, and when the two electrodes are bonded, the two electrodes are respectively electrically connected with the circuits on two sides of the circuit river channel in an additive manufacturing mode.
Referring to fig. 1, an electronic chip bonding method according to an embodiment of the present application is shown;
the method comprises the following steps:
s110, coating insulating glue 3 on the circuit river 22, and placing the chip 1 on the insulating glue 3; wherein the electrode 11 of the chip 1 faces the package substrate 2, and the electrode 11 of the chip 1 corresponds to the circuit 21;
and S120, connecting the circuit 21 with the electrode 11 of the corresponding chip 1 through an additive manufacturing mode.
In the embodiment of the present application, compared to the problem that in the chip bonding process in the prior art, bonding wire breakage, chip breakage, bad welding spots and the like may occur to affect the reliability of the product, the present application provides a solution of a new chip bonding method, which specifically includes: the chip is used for being stuck to the surface of the packaging substrate, a circuit is arranged on the surface of the packaging substrate, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes; the method comprises the following steps: coating insulating glue 3 at the position of the circuit river 22, and placing the chip 1 on the insulating glue 3; wherein the electrode 11 of the chip 1 faces the package substrate 2, and the electrode 11 of the chip 1 corresponds to the circuit 21; the circuit 21 is connected to the corresponding electrode 11 of the chip 1 by means of additive manufacturing. This application is with flip-chip 1 through insulating glue 3 with package substrate 2 bonding, has solved the easy fracture of bonding wire and the not good problem of heat dissipation to form the electricity with chip electrode 11 and circuit 21 and be connected, need not form the solder ball on the chip bonding pad, avoid appearing the bad problem of solder joint, thereby improve reliability and the life-span of product.
Next, an electronic chip bonding method in the present exemplary embodiment will be further described.
As described in the step S110, an insulating adhesive 3 is coated on the circuit river 22, and the chip 1 is placed on the insulating adhesive 3; wherein the electrode 11 of the chip 1 faces the package substrate 2, and the electrode 11 of the chip 1 corresponds to the circuit 21.
In one embodiment of the present invention, the following description may be combined to further describe "coating the insulating glue 3 on the circuit river 22 and placing the chip 1 on the insulating glue 3" in step S110; wherein the electrode 11 of the chip 1 faces the package substrate 2, and the electrode 11 of the chip 1 corresponds to the circuit 21.
It should be noted that, the insulating glue 3 is a compound glue with good electrical insulation property, and can play a role in isolation and protection in a circuit.
As an example, the insulating paste 3 includes a resin, a filler material, and a curing agent; the resin is the main component of the insulating glue and can be epoxy resin, polyurethane resin or acrylic resin; the filling material increases the strength and hardness of the insulating glue, and silica sand, alumina and the like are commonly used filling materials; the curing agent can promote the curing of the insulating adhesive, and can be an anhydride curing agent, an amino curing agent and the like.
As an example, referring to fig. 3 and 4, the insulating glue 3 is placed at the position of the circuit channel 22, then the electrodes 11 of the chip 1 are oriented to the circuit, and the chip 1 is horizontally placed on the surface of the insulating glue 3, so that the two electrodes 11 of the chip 1 are respectively in one-to-one correspondence with the circuits 21 on both sides of the circuit channel 22, and at this time, the distance between the electrodes 11 of the chip and the circuits 21 of the package substrate 3 is between 8 and 12 micrometers.
In one embodiment, the chip electrode 11 is spaced 10 microns from the package substrate.
As described in the step S120, the circuit 21 is connected to the electrode 11 of the corresponding chip 1 by an additive manufacturing method.
In an embodiment of the present invention, the specific process of "connecting the circuit 21 with the electrode 11 of the corresponding chip 1 by additive manufacturing" in step S120 may be further described in conjunction with the following description.
S121, thickening the circuit 21 by additive manufacturing, and forming an electrical connection with the electrode 11 of the corresponding chip 1.
The additive manufacturing (Additive Manufacturing, AM) is also called 3D printing, and is a manufacturing technology for manufacturing solid objects by stacking special metal materials, nonmetal materials or medical biological materials layer by means of extrusion, sintering, melting, photo-curing, spraying and the like through a software and numerical control system based on digital model files. Specifically, the additive manufacturing mode referred to in the application may be one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating and electroless plating.
As an example, referring to fig. 2 and 3, the circuit 21 of the package substrate 2 is thickened by electroplating, so that the circuit 21 is thickened to form an electrical connection with the electrode 11 of the chip 1, and the bonding between the chip electrode 11 and the circuit 21 is completed.
In one embodiment of the present invention, the specific process of step S121 "thickening the circuit 21 by additive manufacturing and forming an electrical connection with the electrode 11 of the corresponding chip 1" may be further described in conjunction with the following description.
S1211, coating a photosensitive material on the surface of the circuit 21, and exposing and developing to expose the first target area of the circuit 21.
In this embodiment, a photosensitive material is coated on the surface of the circuit 21 to form a first photosensitive mask layer and exposed to light to form the first target area; and as described in the following steps, the first photosensitive mask layer at the corresponding position is removed through development, so that the first target area is exposed.
As an example, the surface of the circuit 21 is coated with the photosensitive material, and the electroplated pattern is developed by using an exposure and development process, after development, the photosensitive material (i.e., the photosensitive material on the surface of the first target area) that has not undergone photopolymerization is subjected to plasma cleaning to avoid electroplating defects caused by residual photoresist or foreign matters, and after this process, a metal electroplating process is performed. In the electroplating process, the operation parameters include current density, plating solution flow rate, plating solution temperature and the like, and different operation parameter combinations have different electroplating rates, so that the operation parameters can be selected according to practical situations in the embodiment. After the electroplating process is completed, the photosensitive material is removed, and the photosensitive material remained on the surface is removed again in a plasma cleaning mode. The photosensitive material comprises one or more of a photoresist (including positive photoresist and negative photoresist), photosensitive polyimide resin, photosensitive sol gel or a mixture or a composition thereof, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, and has good photosensitive property.
S1212, thickening the circuit 21 on the surface of the first target area by additive manufacturing.
As an example, the circuit 21 is thickened to form an electrical connection with the chip electrode 11 at the surface of the target area by electroplating.
S1213, removing the photosensitive material.
As an example, the photosensitive material layer on the surface of the circuit 21 is removed by a photoresist remover.
In another embodiment of the present invention, the specific process of "connecting the circuit 21 with the electrode 11 of the corresponding chip 1 by additive manufacturing" in step S120 may be further described in conjunction with the following description.
S122, the circuit 21 and the electrode 11 of the corresponding chip 1 are thickened to form an electrical connection with each other by an additive manufacturing method.
As an example, referring to fig. 2 and 4, the circuit 21 of the package substrate 2 and the electrode 11 of the chip 1 are thickened at the same time by electroless plating until the circuit 21 and the electrode 11 form an electrical connection, and the bonding of the chip electrode 1 and the circuit 21 is completed.
In one embodiment of the present invention, the specific process of step S122 "thickening the circuit 21 and the corresponding electrode 11 of the chip 1 to form an electrical connection with each other simultaneously by means of additive manufacturing" may be further described in conjunction with the following description.
S1221, coating a photosensitive material on the surface of the circuit 21 and the surface of the electrode 11, exposing and developing to expose the second target area of the circuit 21 and the third target area of the electrode.
In this embodiment, a photosensitive material is coated on the surface of the circuit 21, a second photosensitive mask layer is formed and exposed to light, the second target area is formed, and a third photosensitive mask layer is formed and exposed to light, the third target area is formed, by coating the photosensitive material on the surface of the electrode 11; and removing the second photosensitive mask layer at the corresponding position through development to expose the second target area, and removing the third photosensitive mask layer at the corresponding position through development to expose the third target area.
As an example, the surface of the circuit 21 and the surface of the electrode 11 are coated with the photosensitive material, and the electroplated pattern is developed by an exposure and development process, after development, the photosensitive material (i.e., the photosensitive material on the surface of the second target area of the circuit 21 and the photosensitive material on the surface of the third target area of the electrode 11) that is not subjected to photopolymerization is subjected to plasma cleaning to avoid electroplating defects caused by residual photoresist or foreign matters, and then the metal electroplating process is performed after the process is completed. In the electroplating process, the operation parameters include current density, plating solution flow rate, plating solution temperature and the like, and different operation parameter combinations have different electroplating rates, so that the operation parameters can be selected according to practical situations in the embodiment. After the electroplating process is completed, the photosensitive material is removed, and the photosensitive material remained on the surface is removed again in a plasma cleaning mode. The photosensitive material comprises one or more of a photoresist (including positive photoresist and negative photoresist), photosensitive polyimide resin, photosensitive sol gel or a mixture or a composition thereof, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, and has good photosensitive property.
S1222, thickening the circuit 21 on the surface of the second target area by the additive manufacturing method, and thickening the corresponding electrode 11 on the surface of the third target area by the additive manufacturing method.
As an example, the circuit 21 is thickened on the surface of the second target area by electroless plating, and the electrode 11 is thickened on the surface of the third target area by electroless plating until the circuit 21 and the chip electrode 11 are electrically connected.
S1223, removing the photosensitive material on the surface of the circuit 21 and the surface of the electrode 11.
As an example, the photosensitive material layer on the surface of the circuit 21 and the surface of the electrode 11 is removed by a photoresist remover.
The application also provides a chip bonding piece obtained by bonding the electronic chip bonding method, which comprises an insulating adhesive layer, the chip 1 and the packaging substrate 2;
the surface of the packaging substrate 2 is provided with a circuit 21, a circuit river 22 is arranged between adjacent circuits 21, and the chip 1 is provided with an electrode 11;
the insulating adhesive layer is disposed on the circuit river 22, the chip 1 is disposed on the surface of the insulating adhesive layer, and the electrode 11 of the chip 1 is electrically connected with the circuit 22 of the package substrate 2.
As an example, two electrodes 11 are provided on the same side of the chip 1, the electrodes 11 of the chip 1 facing the circuit 21 and forming an electrical connection with the circuit 21 of the package substrate 2.
While preferred embodiments of the present embodiments have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the present application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail the method for bonding an electronic chip and the chip bonding member provided in the present application, and specific examples have been applied to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. An electronic chip bonding method is used for sticking a chip on the surface of a packaging substrate and is characterized in that a circuit is arranged on the surface of the packaging substrate, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes;
the method comprises the following steps:
coating insulating glue on the circuit river channel, and placing the chip in the insulating glue; the electrodes of the chip face the packaging substrate, and the electrodes of the chip correspond to the circuit;
and connecting the circuit with the electrode of the corresponding chip through an additive manufacturing mode.
2. The method of claim 1, wherein the step of connecting the circuit to the corresponding electrode of the chip by additive manufacturing comprises:
the circuit is thickened by additive manufacturing and is electrically connected with the corresponding electrode of the chip.
3. The method of claim 1, wherein the step of connecting the circuit to the corresponding electrode of the chip by additive manufacturing comprises:
and thickening the circuit and the electrode of the corresponding chip to form electric connection with each other through an additive manufacturing mode.
4. The method of claim 2, wherein the step of thickening the circuit by additive manufacturing and forming an electrical connection with the electrode of the corresponding chip comprises:
coating a photosensitive material on the surface of the circuit, exposing and developing to expose a first target area of the circuit;
thickening the circuit on the surface of the first target area by an additive manufacturing mode;
and removing the photosensitive material.
5. The method of claim 4, wherein the step of coating a photosensitive material on the surface of the circuit, exposing and developing the first target area of the circuit to light comprises:
coating a photosensitive material on the surface of the circuit to form a first photosensitive mask layer and exposing the first photosensitive mask layer to form the first target area;
and removing the first photosensitive mask layer at the corresponding position through development, and exposing the first target area.
6. The method of claim 3, wherein the step of simultaneously thickening the electrodes of the circuit and the corresponding chip to form an electrical connection with each other by additive manufacturing comprises:
coating photosensitive materials on the surfaces of the circuits and the surfaces of the corresponding electrodes, and exposing and developing to expose a second target area of the circuits and a third target area of the electrodes;
thickening the circuit on the surface of the second target area by an additive manufacturing mode, and thickening the corresponding electrode on the surface of the third target area by an additive manufacturing mode;
and removing the photosensitive material on the circuit surface and the electrode surface.
7. The method of claim 6, wherein the step of coating a photosensitive material on the surface of the circuit and the corresponding electrode surface, exposing and developing the photosensitive material to expose the second target area of the circuit and the third target area of the electrode, comprises:
coating a photosensitive material on the surface of the circuit to form a second photosensitive mask layer and exposing the photosensitive material to form a second target area, and coating a photosensitive material on the surface of the electrode to form a third photosensitive mask layer and exposing the photosensitive material to form a third target area;
and removing the second photosensitive mask layer at the corresponding position through development to expose the second target area, and removing the third photosensitive mask layer at the corresponding position through development to expose the third target area.
8. The electronic chip bonding method according to claim 1, wherein the chip electrode is 8-12 μm from the package substrate.
9. The method of claim 1, wherein the additive manufacturing method comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.
10. A die bond prepared according to the electronic die bonding method of any one of claims 1-9, comprising an insulating glue layer, the die, and the package substrate;
the surface of the packaging substrate is provided with circuits, a circuit river channel is arranged between adjacent circuits, and the chip is provided with electrodes;
the insulating adhesive layer is arranged on the circuit river channel, the chip is arranged on the surface of the insulating adhesive layer, and the electrode of the chip is electrically connected with the circuit of the packaging substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311289969.0A CN117276100A (en) | 2023-09-28 | 2023-09-28 | Electronic chip bonding method and chip bonding piece |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311289969.0A CN117276100A (en) | 2023-09-28 | 2023-09-28 | Electronic chip bonding method and chip bonding piece |
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| CN117276100A true CN117276100A (en) | 2023-12-22 |
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| CN202311289969.0A Pending CN117276100A (en) | 2023-09-28 | 2023-09-28 | Electronic chip bonding method and chip bonding piece |
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