CN210325778U - High-density chip welding structure - Google Patents
High-density chip welding structure Download PDFInfo
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- CN210325778U CN210325778U CN201921337381.7U CN201921337381U CN210325778U CN 210325778 U CN210325778 U CN 210325778U CN 201921337381 U CN201921337381 U CN 201921337381U CN 210325778 U CN210325778 U CN 210325778U
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- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The utility model relates to a high density chip welded structure, including the metal carrier, be located the metal joining region on the metal carrier, install a plurality of chips on the metal joining region, the metal material of metal carrier integration or the carrier at insulating substrate surface adhesion one deck metallic conductor, the metal joining region includes that a plurality of metal pads or many circuits walk line and a plurality of metal pad or solder mask, be equipped with the solder layer on the metal pad, be equipped with on the solder layer and help the welding layer, the circuit is walked the extreme point of line and is connected with the metal pad electricity, the solder that the metal pad passes through the solder layer and the pad or the electrode welding of high temperature and chip. The integrated metal material comprises a metal base material and a metal conductor. The height of each metal pad is equal or unequal. The utility model provides a current silver glue solder have resin material and chip coefficient of thermal expansion to mismatch, lead to bonding back chip easily with solder layering, silver powder can not 100% fill, electrically conduct and the not good scheduling problem of heat dissipation.
Description
Technical Field
The utility model relates to a chip production technical field especially relates to a high density chip welded structure.
Background
When packaging a conventional chip such as a diode, a triode, etc., the chip is usually bonded by using a resin material such as a conductive adhesive, a non-conductive adhesive, etc., so as to realize a fixing function.
The conductive adhesive mainly utilizes the viscosity of resin materials in the silver adhesive to complete the bonding of the chip, and the conduction function of the chip pin is completed through the conduction of the silver powder in the resin materials.
However, the conductive adhesive (hereinafter referred to as silver adhesive) packaging method has the following defects: the CTE (coefficient of thermal expansion) mismatch between the resin material and the chip leads to the problems that the chip is easy to be layered with the solder after being bonded, the silver powder cannot be filled by 100 percent, the electric conduction and the heat dissipation are poor, and the like, thereby limiting the development of the chip.
For chip products with strict requirements on heat dissipation, electrical conductivity and CTE, the existing solution is to use solder paste to solve the problems of delamination caused by CTE mismatch and poor electrical and heat dissipation.
However, the conventional solder paste method has the following drawbacks:
(1) the chip product processing is realized by printing solder paste through a steel mesh, and the cost is required for manufacturing the steel mesh;
(2) the thickness, the smoothness and the contraposition precision of the solder are limited to a certain extent during processing;
(3) when the chip product is repeatedly welded and processed, the problem of secondary tin melting exists, so that the reliability of the chip product is influenced.
Therefore, the solder paste and the silver paste are both limited by processing methods and equipment, the minimum size of a chip which can be realized by the solder paste and the silver paste can only reach 0.2mm or more, and the space between welding points is larger.
Aiming at the chip products with high density and high requirement on smoothness, the two solders are greatly limited. To solve the above problems, we invented a high-density die bonding structure.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an invention aim at solve current silver glue solder and have resin material and chip coefficient of thermal expansion mismatch, lead to the back chip that bonds easy with the solder layering, silver powder can not 100% fill, electrically conductive and heat dissipation scheduling problem, current soldering paste solder exists needs steel mesh printing, the steel mesh is with high costs, solder thickness, planarization and counterpoint precision have certain restriction, the chip carries out repeated welding man-hour, has the secondary to melt the tin problem to influence the problem of the reliability of chip product. The concrete solution is as follows:
the utility model provides a high density chip welded structure, includes the metal carrier, is located the metal joining region on the metal carrier, installs a plurality of chips on the metal joining region, the metal material of metal carrier for the integration or the carrier of one deck metallic conductor is attached to insulating substrate surface, the metal joining region includes that a plurality of metal pads or many circuits walk line and a plurality of metal pads or solder mask, be equipped with the solder layer on the metal pad, be equipped with on the solder layer and help the welding layer, the circuit is walked and is located under the solder mask, and the circuit is walked the extreme point and is connected with the metal pad electricity, and the solder that the metal pad passes through the solder layer and high temperature and the pad or the electrode welding of.
Optionally, the integrated metal material includes a metal base material and a metal conductor, and after the chip bonding is completed, the metal base material and the metal conductor are peeled off or the insulating base material and the metal conductor are peeled off in a physical manner.
Furthermore, the size, the thickness and the size of a bonding pad of each chip are different, the size of each chip is more than or equal to 0.15 x 0.15mm, the thickness of each chip is more than or equal to 0.08mm, and the size of each bonding pad of each chip is more than or equal to 20 x 20 mu m.
Furthermore, the size of the metal bonding pad is more than or equal to 20 x 20 μm, the height of the metal bonding pad is more than or equal to 20 μm, and the height of each metal bonding pad is equal or unequal.
Further, the solder thickness of the solder layer ranges from 3 to 5 μm, and the precision of the solder thickness is ± 1 μm.
Furthermore, the minimum width of the circuit wire is more than or equal to 20 microns, and the height of the circuit wire is more than or equal to 20 microns.
Further, the welding assistant layer is made of any one of solid, paste or liquid materials.
Further, the solder is any one of tin, indium, and a tin-copper alloy.
Further, the metal pad is any one of copper or nickel.
This scheme high density chip welded structure carries out high density chip welding according to following step:
and 10, after the chip is welded, stripping the metal base material or the insulating base material from the metal conductor in a physical mode.
When metal pads with different heights exist on the same metal carrier, the steps 1 to 6 are firstly carried out, and then the following steps are added:
step 6A, attaching a layer of light-sensitive material on the surface of the metal carrier;
step 6B, generating a plurality of patterns of the higher metal bonding pads in an exposure and development mode;
step 6C, finishing the processing of a plurality of higher metal bonding pads in an electroplating mode;
step 6D, attaching a layer of light sensation material on the surface of the metal carrier;
step 6E, generating a plurality of patterns of higher metal solders in an exposure and development mode;
step 6F, processing a plurality of higher metal solders in an electroplating or chemical plating mode, and then removing redundant light-sensitive materials through a chemical method;
and switching to the step 7 to the step 10.
Wherein, the coating method is any one of spot coating, spraying, printing and soaking.
To sum up, adopt the utility model discloses a technical scheme has following beneficial effect:
the utility model provides a current silver glue solder have resin material and chip thermal expansion coefficient to mismatch, lead to bonding back chip easy with the solder layering, silver powder can not 100% fill, electrically conductive and the not good scheduling problem of heat dissipation, current soldering paste solder existence needs steel mesh printing, the steel mesh is with high costs, solder thickness, planarization and counterpoint precision have certain restriction, the chip carries out repeated welding man-hour, there is the secondary problem of melting tin to influence the problem of the reliability of chip product. This scheme of adoption has following advantage:
(1) the processing of the ultrathin solder can be realized, and the thickness precision of the solder is controlled within +/-1 mu m;
(2) the chip after the patch welding has good smoothness, and the height range can be controlled within 5 mu m;
(3) the flip chip or the front chip interconnection of the high-density chip can be realized, the size of the bonding pad can be 20 micrometers by 20 micrometers, and the minimum distance between welding points can be about 20 micrometers;
(4) solder resist materials are coated on the circuit wiring and the metal bonding pad, so that short circuit among welding points (the bonding pads after welding) is avoided, and the alignment precision of the high-density chip is improved;
(5) the scheme can also form metal bonding pads with different heights, is suitable for special welding requirements of different thicknesses of a plurality of chips, and ensures the smoothness of the high-density chips.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed to be used in the description of the embodiments of the present invention will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive faculty.
Fig. 1 is a structural diagram of an embodiment 1 of a high-density chip bonding structure according to the present invention;
FIG. 2 is a structural diagram of a high-density chip bonding structure according to the present invention, in example 1, a raw metal solder and a chip are illustrated;
fig. 3 is a structural diagram of a high-density chip bonding structure of embodiment 2 of the present invention;
FIG. 4 is an enlarged view of the region A in FIG. 3;
fig. 5 is a structural view of a high-density chip bonding structure of the present invention, example 2, a raw metal solder and a chip;
fig. 6 is a structural view of a high-density chip bonding structure according to embodiment 3 of the present invention;
fig. 7 is a structural view of a high-density chip bonding structure of the present invention, example 3, in which no chip is mounted;
fig. 8 is a structural diagram of a high-density chip bonding structure according to embodiment 4 of the present invention.
Description of reference numerals:
1-metal carrier, 2-chip, 3-metal pad, 4-solder layer, 5-solder layer, 6-metal substrate, 7-metal conductor, 8-circuit trace, 9-solder layer, 21-thinner chip, 31-higher metal pad, 40-metal solder, 41-higher metal solder, and 61-insulating substrate.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example 1:
as shown in fig. 1 to 2, a high-density chip bonding structure includes a metal carrier 1, a metal bonding area on the metal carrier 1, and a plurality of chips 2 mounted on the metal bonding area, wherein the metal carrier 1 is an integrated metal material or a carrier (as shown in fig. 8) with a layer of metal conductor 7 attached to the surface of an insulating substrate 61, the metal bonding area includes a plurality of metal pads 3, a solder layer 4 is disposed on the metal pads 3, a solder flux layer 5 is disposed on the solder layer 4, and the metal pads 3 are bonded to pads or electrodes of the chips 2 through solder and high temperature of the solder layer 4.
Preferably, the metal carrier 1 of the present embodiment is an integrated metal material, which includes the metal base material 6 and the metal conductor 7, and after the chip 2 is soldered, the metal base material 6 and the metal conductor 7 can be physically separated.
Furthermore, the size, thickness and bonding pad size of each chip 2 are different, the size of the chip 2 is more than or equal to 0.15 × 0.15mm, the thickness of the chip 2 is more than or equal to 0.08mm, and the bonding pad size of the chip 2 is more than or equal to 20 × 20 μm.
Further, the solder layer 4 has a solder thickness of 3 to 5 μm with a precision of + -1 μm, and the solder is any of tin, indium, or a tin-copper alloy.
The metal pad 3 is any one of copper or nickel, the size of the metal pad 3 is more than or equal to 20 x 20 μm, the height of the metal pad 3 is more than or equal to 20 μm, and the height of each metal pad 3 in the embodiment is equal.
Example 2:
as shown in fig. 3 to 5, different from embodiment 1, the metal connection region further includes a plurality of circuit traces 8, the end points of the circuit traces 8 are electrically connected to the metal pads 3, the minimum width of the circuit traces 8 is greater than or equal to 20 μm, the height of the circuit traces 8 is greater than or equal to 20 μm, and the rest of the contents are completely the same as those of embodiment 1 and will not be described again.
Example 3:
as shown in fig. 6 to 7, unlike embodiment 2, a solder resist layer 9 is provided on the outer edge of the circuit trace 8 or the metal pad 3, and the solder resist layer 9 has two functions of effectively preventing short circuit of the pads of the high-density chip 2 and improving the alignment accuracy of the high-density chip 2. The rest of the contents are completely the same as embodiment 2, and are not described again.
Example 4:
as shown in fig. 8, different from embodiment 1, the metal carrier 1 of this embodiment is a carrier having a layer of metal conductor 7 attached to a surface of an insulating base material 61, the metal carrier 1 has a plurality of chips 2 with different thicknesses, and the heights of the metal pads are different, at this time, a higher metal pad 31 is stacked on a metal pad 3 (referring to a lower metal pad), a higher metal solder 41 is disposed on the higher metal pad 31, and the thicknesses of the higher metal solder 41 and the metal solder 40 (referring to the metal solder disposed on the lower metal pad 3) may be the same or different, and are determined according to the thickness and the thinness of the specific chip 2. The thinner chip 21 is mounted on the upper metal pad 31 and the upper metal solder 41. When the bonding of the chip 2 is completed, the insulating base material 61 and the metal conductor 7 can be physically peeled off. The rest of the contents are completely the same as those of embodiment 1, and are not described again.
This scheme high density chip welded structure carries out high density chip welding according to following step:
and 10, after the chip is welded, stripping the metal base material or the insulating base material from the metal conductor in a physical mode.
When the metal pads 3 with different heights exist on the same metal carrier 1, the steps 1 to 6 are firstly carried out, and then the following steps are added:
step 6A, attaching a layer of light-sensitive material on the surface of the metal carrier 1;
step 6B, generating a plurality of patterns of the higher metal pads 31 by means of exposure and development;
step 6C, finishing the processing of a plurality of higher metal pads 31 in an electroplating mode;
step 6D, attaching a layer of light sensation material on the surface of the metal carrier 1;
step 6E, generating a plurality of patterns of the higher metal solders 41 in an exposure and development mode;
step 6F, finishing the processing of a plurality of higher metal solders 41 in an electroplating or chemical plating mode, and then removing the redundant light-sensitive materials by a chemical method;
and switching to the step 7 to the step 10.
Furthermore, the flux is in any solid or paste or liquid state, and the coating method is any one of spot coating, spray coating, printing (referring to whole-plate printing) or infiltration, wherein the infiltration, spray coating and whole-plate printing coating are carried out on the surface of the metal carrier 1 without difference. The solder resist material in step 4 is also one of the light-sensitive materials, and operations such as exposure and development can be performed in the same way.
To sum up, adopt the utility model discloses a technical scheme has following beneficial effect:
the utility model provides a current silver glue solder have resin material and chip thermal expansion coefficient to mismatch, lead to bonding back chip easy with the solder layering, silver powder can not 100% fill, electrically conductive and the not good scheduling problem of heat dissipation, current soldering paste solder existence needs steel mesh printing, the steel mesh is with high costs, solder thickness, planarization and counterpoint precision have certain restriction, the chip carries out repeated welding man-hour, there is the secondary problem of melting tin to influence the problem of the reliability of chip product. This scheme of adoption has following advantage:
(1) the processing of the ultrathin solder can be realized, and the thickness precision of the solder is controlled within +/-1 mu m;
(2) the chip 2 after the surface mounting welding has good flatness, and the height range can be controlled within 5 mu m;
(3) the flip chip or the front chip interconnection of the high-density chip 2 can be realized, the size of a bonding pad can be 20 micrometers by 20 micrometers, and the minimum distance between welding points can be about 20 micrometers;
(4) solder resist materials are coated on the circuit wiring 8 and the metal bonding pad 3, so that short circuit among welding points (bonding pads after welding) is avoided, and the alignment precision of the high-density chip 2 is improved;
(5) this scheme still can form the metal pad that the height differs, is applicable to the different special welding demands of a plurality of 2 thicknesses of chip to the planarization of high density chip 2 has been guaranteed.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.
Claims (9)
1. A high-density chip bonding structure is characterized in that: including the metal carrier, be located the metal joining region on the metal carrier, install a plurality of chips on the metal joining region, the metal carrier is the carrier of one deck metallic conductor of metal material or at insulating substrate surface adhesion of integration, the metal joining region includes that a plurality of metal pads or many circuits walk line and a plurality of metal pad or solder mask, be equipped with the solder layer on the metal pad, be equipped with on the solder layer and help the welding layer, the circuit is walked and is located under the solder mask, and the terminal point and the metal pad electricity of circuit walking line are connected, and the solder and the high temperature of metal pad through the solder layer and the pad or the electrode welding of chip.
2. The high-density die bonding structure of claim 1, wherein: the integrated metal material comprises a metal base material and a metal conductor, and after the chip welding is completed, the metal base material and the metal conductor are peeled off or the insulating base material and the metal conductor are peeled off in a physical mode.
3. The high-density die bonding structure of claim 1, wherein: the size, the thickness and the size of the bonding pad of each chip are different, the size of each chip is not less than 0.15 x 0.15mm, the thickness of each chip is not less than 0.08mm, and the size of each bonding pad of each chip is not less than 20 x 20 mu m.
4. A high-density die-bonding structure according to claim 3, wherein: the size of the metal bonding pad is more than or equal to 20 x 20 mu m, the height of the metal bonding pad is more than or equal to 20 mu m, and the height of each metal bonding pad is equal or unequal.
5. The high-density die bonding structure according to claim 4, wherein: the solder thickness range of the solder layer is 3-5 μm, and the precision of the solder thickness is +/-1 μm.
6. The high-density die bonding structure according to claim 5, wherein: the minimum width of the circuit wire is more than or equal to 20 microns, and the height of the circuit wire is more than or equal to 20 microns.
7. The high-density die bonding structure of claim 6, wherein: the welding-assistant layer is made of any one of solid, paste or liquid materials.
8. The high-density die-bonding structure according to claim 7, wherein: the solder is any one of tin, indium or tin-copper alloy.
9. The high-density die-bonding structure according to claim 8, wherein: the metal pad is any one of copper or nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921337381.7U CN210325778U (en) | 2019-08-16 | 2019-08-16 | High-density chip welding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921337381.7U CN210325778U (en) | 2019-08-16 | 2019-08-16 | High-density chip welding structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210325778U true CN210325778U (en) | 2020-04-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921337381.7U Active CN210325778U (en) | 2019-08-16 | 2019-08-16 | High-density chip welding structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210325778U (en) |
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2019
- 2019-08-16 CN CN201921337381.7U patent/CN210325778U/en active Active
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