CN117253903A - Terminal protection structure of semiconductor power device and manufacturing method thereof - Google Patents

Terminal protection structure of semiconductor power device and manufacturing method thereof Download PDF

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Publication number
CN117253903A
CN117253903A CN202311218614.2A CN202311218614A CN117253903A CN 117253903 A CN117253903 A CN 117253903A CN 202311218614 A CN202311218614 A CN 202311218614A CN 117253903 A CN117253903 A CN 117253903A
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epitaxial layer
power device
field limiting
protection structure
semiconductor power
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禹小军
杭华
刘伟
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Minhua Micro Shanghai Electronic Technology Co ltd
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Minhua Micro Shanghai Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a terminal protection structure of a semiconductor power device, which surrounds the periphery of a main junction and comprises: a plurality of field limiting rings composed of second implantation regions doped with a second conductivity type; a trench isolation structure is formed between the field limiting rings, between the innermost field limiting ring and the first injection region of the main junction, and outside the outermost field limiting ring, and is composed of a dielectric layer filled in the first trench. The field limiting rings are contacted with the first epitaxial layer to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure limits the first curved surface from both sides of the first curved surface to reduce the area of the first curved surface, reduce the corner angle, and position the corners of both sides of the first curved surface below the top surface of the first epitaxial layer. The invention also provides a manufacturing method of the terminal protection structure of the semiconductor power device. The invention can improve the reverse breakdown voltage of the terminal protection structure.

Description

Terminal protection structure of semiconductor power device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacture, in particular to a terminal protection structure of a semiconductor power device; the invention also relates to a manufacturing method of the terminal protection structure of the semiconductor power device.
Background
The fast recovery diode (Fast Recovery Diode, FRD) is one of the most used power semiconductor devices in power electronic equipment as a novel power device which is recently developed, and has the advantages of good switching performance, short reverse recovery time, forward conduction voltage reduction, high current, high reverse withstand voltage, small electric leakage and the like, and is often used in parallel with three-terminal power switching devices (such as IGBT (insulated gate bipolar transistor) in a power electronic circuit, so that the fast recovery diode is used as a high-frequency and high-current follow current diode or rectifying tube, and has great development prospect and market demand. From the pressure-resistant range, the FRD less than 1200V is mainly used for variable frequency household appliances, variable frequency welders and electric vehicles; the FRD with the voltage higher than 1200V-1700V is mainly applied to industrial products such as photovoltaic inversion, high-voltage frequency converters and the like. The continuous development of power electronics and consumer electronics opens up a wide application area for semiconductor power devices, and along with the rapid growth of power electronics and consumer electronics, the requirements of reducing the cost of the power electronics and consumer electronics are increasing.
For a fast recovery diode, the reverse breakdown voltage is one of the most important parameters, which together with the maximum current capacity determines the power rating of the power electronics. The silicon-based power FRD is usually implemented by a large-area PN junction to ensure high-current operation. However, for FRD operated at high voltage, junction bending effect inevitably exists in the planar process, and the main factors affecting the breakdown voltage of the device are electric field concentration caused by junction bending of the PN junction diffusion window region and surface electric field concentration caused by interface charges, because the influence of these factors makes the actual breakdown voltage of the device be only 10% -30% of ideal. Therefore, in order to ensure that the silicon-based FRD can operate normally under high voltage, measures, i.e., junction termination protection techniques, such as Field plates (Field plates) and Field rings (Limiting Field Ring) are usually required at the outer edges of the device main junction to eliminate the effect of junction bending, weaken the surface electric Field strength, and increase the pn junction breakdown voltage of the power FRD device.
In the existing fast recovery diode, the field limiting ring of the terminal, namely PN contact surface of PN junction formed between the P+ injection region and the N-substrate is an approximately elliptic curved surface, corner parts of the curved surface of the junction can lead to the phenomenon that electric lines are concentrated and electric fields rise, and meanwhile, part of electric lines can end on the surface of the silicon epitaxial layer in a spacing region between the field limiting rings, and the two conditions can lead to reverse breakdown voltage at the place to be obviously lower than that of a main junction plane part, so that the reverse breakdown voltage of the whole device is reduced. If the flatness of the depletion layer in reverse and the termination of the power line away from the silicon-based surface can be improved, the breakdown voltage of the termination portion is made closer to that of the main junction portion, thereby improving the breakdown voltage of the entire device and improving the reverse characteristics (breakdown voltage and reverse leakage current) of the fast recovery diode.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a terminal protection structure of a semiconductor power device, which can adjust the curved surface of the junction surface of a field limiting ring so as to reduce the concentration of power lines caused by the curved surface corner of the junction surface of the field limiting ring, and can prevent the power lines from entering the top surface of an epitaxial layer between the field limiting rings, thereby reducing the rise of an electric field generated by the power lines, improving the reverse breakdown voltage of the terminal protection structure and further improving the reverse breakdown voltage of the whole semiconductor power device. Therefore, the invention also provides a manufacturing method of the terminal protection structure of the semiconductor power device.
In order to solve the technical problem, in the terminal protection structure of the semiconductor power device provided by the invention, the semiconductor power device comprises a first injection region doped with a second conductivity type, the first injection region is formed in a selected region of a first epitaxial layer doped with the first conductivity type, and the first injection region and the first epitaxial layer form a main junction.
The terminal protection structure surrounds the main junction circumference side.
The terminal protection structure includes:
a plurality of field limiting rings, each field limiting ring being comprised of a second implant region doped with a second conductivity type; the field limiting rings are arranged in the first epitaxial layer outside the first injection region and are in annular structures, and the radius of the inner side edge of each field limiting ring sequentially increases from the outer side edge of the first injection region to the outer side edge of the first injection region.
A trench isolation structure is formed between the field limiting rings, between the innermost field limiting ring and the first injection region and outside the outermost field limiting ring, the trench isolation structure is composed of a dielectric layer filled in a first trench, and the first trench is formed in the first epitaxial layer.
The field limiting rings are contacted with the first epitaxial layer to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer, thereby preventing the electric lines of the corners of the two sides of each first curved surface from concentrating and enabling the electric lines of the electric lines to be far away from the top surface of the first epitaxial layer when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
Further improvement is that the terminal protection structure further comprises:
a stop ring comprised of heavily doped regions of the first conductivity type, the stop ring being in the first epitaxial layer outside the outermost field limiting ring.
A further improvement is that there is a spacing between the inner side edge of the trench isolation structure and the outer side edge of the first implant region between the outer side edge of the first implant region and the inner side edge of the innermost field stop ring.
A further improvement is that the outside edge of the trench isolation structure between the inside edge of the stop ring and the outside edge of the outermost field stop ring is in contact with or has a spacing from the inside edge of the stop ring.
The bottom surface of the first groove and the bottom surface of the field limiting ring are leveled, so that the flatness of a depletion layer formed by depletion of each auxiliary junction is improved when the semiconductor power device is reversely biased.
Further improvement is that the terminal protection structure further comprises:
interlayer film, contact hole (CT) and front metal layer.
The top surface of the trench isolation structure and the top surface of the first epitaxial layer are flat, and the interlayer film is formed on the top surfaces of the trench isolation structure and the first epitaxial layer.
The contact hole passes through the interlayer film.
The first electrode of the main junction and the terminal field plate are formed by patterning the front metal layer.
The first injection region is connected with the first electrode through the contact hole corresponding to the top.
Each field limiting ring is connected to the corresponding terminal field plate through the corresponding contact hole at the top.
In a further improvement, the first epitaxial layer is formed on the surface of the semiconductor substrate.
The semiconductor substrate is heavily doped with a first conductivity type, and the back electrode area consists of the thinned semiconductor substrate; or the back electrode region is formed by doping the thinned semiconductor substrate with the impurity implanted by the first conductive type heavy doping.
A back electrode composed of a back metal layer is formed on the back surface of the back electrode region.
A further improvement is that the semiconductor power device comprises a fast recovery diode.
Further improvement is that the process structures of the first injection region and the second injection region are the same or the process structures of the first injection region and the second injection region are independent from each other.
A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
In order to solve the technical problem, the manufacturing method of the terminal protection structure of the semiconductor power device provided by the invention comprises the following steps:
providing a first epitaxial layer with first conductivity type doping, and forming a plurality of first trenches in selected areas of the first epitaxial layer; the first trench is located in a formation region of the terminal protection structure.
And filling a dielectric layer in each first groove to form a groove isolation structure.
Step two, performing ion implantation of a second conductivity type in a selected region of the first epitaxial layer to form a first implantation region; the first implant region and the first epitaxial layer form a main junction.
The terminal protection structure surrounds the circumference side of the main knot.
And thirdly, performing ion implantation of a second conductivity type in a selected region of the first epitaxial layer to form a plurality of second implantation regions, wherein each second implantation region is formed with a field limiting ring.
The field limiting rings are arranged in the first epitaxial layer outside the first injection region and are in annular structures, and the radius of the inner side edge of each field limiting ring sequentially increases from the outer side edge of the first injection region to the outer side edge of the first injection region.
The trench isolation structure is formed between the field limiting rings, between the innermost field limiting ring and the first implant region, and outside the outermost field limiting ring.
The field limiting rings are contacted with the first epitaxial layer to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer, thereby preventing the electric lines of the corners of the two sides of each first curved surface from concentrating and enabling the electric lines of the electric lines to be far away from the top surface of the first epitaxial layer when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
Further improvement is that after the first step is completed, before or after the second step or the third step, the method further comprises:
performing first conductivity type heavily doped ion implantation to form a stop ring in the first epitaxial layer outside the outermost field limiting ring.
The bottom surface of the first groove and the bottom surface of the field limiting ring are leveled, so that the flatness of a depletion layer formed by depletion of each auxiliary junction is improved when the semiconductor power device is reversely biased.
Further improvement is that the method further comprises the following steps:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a first electrode and a terminal field plate of the main junction.
The top surface of the trench isolation structure and the top surface of the first epitaxial layer are flat, and the interlayer film is formed on the top surfaces of the trench isolation structure and the first epitaxial layer.
The contact hole passes through the interlayer film.
The first injection region is connected with the first electrode through the contact hole corresponding to the top.
Each field limiting ring is connected to the corresponding terminal field plate through the corresponding contact hole at the top.
A further improvement is that the semiconductor power device comprises a fast recovery diode.
The further improvement is that the first injection region and the second injection region have the same process structure, and the second injection region and the third injection region are combined together to form the first injection region and the second injection region simultaneously.
Or the process structures of the first injection region and the second injection region are independent, and the second step and the third step are carried out separately.
The invention can reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer by arranging the groove isolation structure between the field limiting rings and utilizing the groove isolation structure to carry out limiting adjustment on the curved surface of the junction surface of the field limiting rings, namely the first curved surface, from the two sides of the field limiting rings, thereby reducing the electric field concentration caused by overlarge corners of the two sides of the first curved surface and the electric field concentration caused by the corners being positioned at the top surface of the first epitaxial layer, reducing the electric field rise caused by the electric field concentration and improving the reverse breakdown voltage of the terminal protection structure.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic diagram of a termination protection structure of a semiconductor power device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a terminal protection structure of a semiconductor power device according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a terminal protection structure of a semiconductor power device according to an embodiment of the present invention; in the terminal protection structure of the semiconductor power device according to the embodiment of the present invention, the semiconductor power device includes a first injection region 103 doped with a second conductivity type, the first injection region 103 is formed in a selected region of a first epitaxial layer 102 doped with the first conductivity type, and the first injection region 103 and the first epitaxial layer 102 form a main junction. The terminal protection structure surrounds the main junction circumference side.
The terminal protection structure includes:
a plurality of field limiting rings 104, each field limiting ring 104 being comprised of a second implant region doped with a second conductivity type; each field limiting ring 104 is formed in the first epitaxial layer 102 outside the first implantation region 103 and has a ring-shaped structure, and the radius of the inner edge of each field limiting ring 104 increases from the outer edge of the first implantation region 103 to the outer edge. In fig. 1, only a partial region at the outer edge of the first injection region 103 is shown, and the field limiting ring 104 has a ring-shaped structure in a top view; in fig. 1, the right-to-left direction is the inside-to-outside direction.
A trench isolation structure 105 is formed between the field limiting rings 104, between the innermost field limiting ring 104 and the first implantation region 103, and outside the outermost field limiting ring 104, the trench isolation structure 105 being composed of a dielectric layer filled in a first trench formed in the first epitaxial layer 102. In the embodiment of the present invention, the dielectric layer of the trench isolation structure 105 is an oxide layer. In other embodiments, the dielectric layer of the trench isolation structure 105 may be made of other materials, so long as an effective isolation effect is ensured.
The field limiting rings 104 are contacted with the first epitaxial layer 102 to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure 105 limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of two sides of the first curved surface, and enable the corner positions of two sides of the first curved surface to be located below the top surface of the first epitaxial layer 102, thereby preventing the electric lines of force at the corners of two sides of each first curved surface from being concentrated and enabling the electric lines of force to be far away from the top surface of the first epitaxial layer 102 when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
In an embodiment of the present invention, the terminal protection structure further includes:
a stop ring 106 consisting of a heavily doped region of the first conductivity type, said stop ring 106 being formed in said first epitaxial layer 102 outside said field limiting ring 104 outermost.
The stop ring 106, also referred to as a termination ring, is used to prevent electric fields from diffusing into the die scribe lanes. The stop ring 106 can be formed using a first conductivity type heavily doped well implantation process plus an anneal drive.
A space is provided between the inner side edge of the trench isolation structure 105 located between the outer side edge of the first implantation region 103 and the inner side edge of the innermost field stop ring 104 and the outer side edge of the first implantation region 103.
The outer edge of the trench isolation structure 105, which is located between the inner edge of the stop ring 106 and the outer edge of the outermost field stop ring 104, is in contact with or has a spacing from the inner edge of the stop ring 106.
In some preferred embodiments, the bottom surface of the first trench and the bottom surface of the field limiting ring 104 are flat, so as to improve the flatness of the depletion layer formed by depletion of each auxiliary junction when the semiconductor power device is reversely biased. After the flatness of the depletion layer is improved, the distribution of the power lines can be more uniform, so that the reverse breakdown voltage of the device can be further improved.
In the embodiment of the present invention, the process structures of the first implantation region 103 and the second implantation region are independent of each other, so that the doping of the first implantation region 103 and the second implantation region can be adjusted as required. The first implant region 103 and the second implant region are typically formed using a well implant process of the second conductivity type plus an anneal drive. In other embodiments can also be: the process structures of the first injection region 103 and the second injection region are the same; this is advantageous in terms of saving process steps.
The terminal protection structure further includes:
interlayer film 107, contact hole 108, and front metal layer.
The top surface of the trench isolation structure 105 and the top surface of the first epitaxial layer 102 are leveled, and the interlayer film 107 is formed on the top surfaces of the trench isolation structure 105 and the first epitaxial layer 102.
The contact hole 108 penetrates the interlayer film 107.
The first electrode 1091 of the main junction and the termination field plate 1092 are patterned from the front side metal layer.
The first injection region 103 is connected to the first electrode 1091 through the contact hole 108 corresponding to the top.
Each of the field limiting rings 104 is connected to a corresponding one of the termination field plates 1092 through a top corresponding one of the contact holes 108.
In some preferred embodiments, a well contact region heavily doped with the second conductivity type is further formed at the bottom of the contact hole 108 corresponding to the top of the first implantation region 103 and the field limiting ring 104, so as to realize ohmic contact with the contact hole 108 at the top.
In some embodiments, a passivation layer is also formed, and the material of the passivation layer includes silicon nitride and polyimide, which are used for protecting the semiconductor power device.
In the embodiment of the present invention, the first epitaxial layer 102 is formed on the surface of the semiconductor substrate 101.
The material of the semiconductor substrate 101 comprises silicon, and the semiconductor substrate 101 adopts an epitaxial silicon wafer or a zone-melting silicon wafer.
The semiconductor substrate 101 is heavily doped with a first conductivity type, and a back electrode region is formed by the thinned semiconductor substrate 101; alternatively, the back electrode region is composed of the thinned semiconductor substrate 101 doped with the impurity of the first conductivity type heavily doped implantation.
A back electrode composed of a back metal layer is formed on the back surface of the back electrode region.
In the embodiment of the invention, the semiconductor power device is a fast recovery diode.
In the embodiment of the invention, the first conductive type is N type, and the second conductive type is P type. At this time, the first injection region 103 is an anode region; the back electrode region is a cathode region.
In other embodiments can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The embodiment of the invention can reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer 102 by arranging the trench isolation structure 105 between the field limiting rings 104 and utilizing the trench isolation structure 105 to carry out limiting adjustment on the curved surface of the junction surface of the field limiting rings 104, namely the first curved surface, from the two sides of the field limiting rings 104, thereby reducing the electric field concentration caused by overlarge corners of the two sides of the first curved surface and the electric field concentration caused by the corners being positioned at the top surface of the first epitaxial layer 102, reducing the electric field rise caused by the electric field concentration and improving the reverse breakdown voltage of the whole semiconductor power device.
As shown in fig. 2, a flowchart of a method for manufacturing a terminal protection structure of a semiconductor power device according to an embodiment of the present invention is shown; the manufacturing method of the terminal protection structure of the semiconductor power device comprises the following steps:
step one, a first epitaxial layer 102 having a first conductivity type doping is provided.
In the method of the embodiment of the present invention, the first epitaxial layer 102 is formed on the surface of the semiconductor substrate 101.
The material of the semiconductor substrate 101 comprises silicon, and the semiconductor substrate 101 adopts an epitaxial silicon wafer. Providing the first epitaxial layer 102 corresponds to step S101 in fig. 2.
In other embodiment methods, it can also be: the semiconductor substrate 101 is a zone-melting silicon wafer.
Forming a plurality of first trenches in selected regions of the first epitaxial layer 102; the first trench is located in a formation region of the terminal protection structure.
And filling a dielectric layer in each first groove to form a groove isolation structure 105.
In the method of the embodiment of the present invention, the sub-steps of forming the first trench and the trench isolation structure 105 include:
forming a hard mask layer;
step S102 is performed, trench photolithography is performed, a forming region of the first trench is defined by using photolithography, and then the first epitaxial layer 102 is etched to form the first trench. In some preferred embodiment methods, the bottom surface of the first trench and the bottom surface of the field limiting ring 104 are leveled to improve the planarity of the depletion layer formed by depletion of each of the auxiliary junctions when the semiconductor power device is reverse biased.
Step S103 is performed to fill/polish the trenches, and the dielectric layer is used to fill each of the first trenches to form the trench isolation structure 105. Typically, the dielectric layer will also extend to the surface of the first trench outer region after filling; planarization of the dielectric layer, such as by a chemical mechanical polishing process, is required to remove the dielectric layer outside the first trench and to locate the dielectric layer only in the first trench and thereby form the trench isolation structure 105.
The method of the embodiment of the invention further comprises the following steps:
heavily doped ions of the first conductivity type are implanted to form a stop ring 106 in the first epitaxial layer 102 outside the outermost field limiting ring 104. The stop ring 106 is also referred to as a termination ring. As shown in fig. 2, the method comprises the following sub-steps:
step S104, terminating ring lithography, namely, defining the formation region of the stop ring 106 by using a lithography process.
Step S105, terminating the ring N injection. In the method of the embodiment of the invention, the first conduction type is N type, so the termination ring adopts N type injection, and the termination ring N injection can be realized by adopting a deep N well process.
Step two, performing ion implantation of a second conductivity type in a selected region of the first epitaxial layer 102 to form a first implantation region 103; the first implanted region 103 and the first epitaxial layer 102 form a main junction.
The terminal protection structure surrounds the circumference side of the main knot.
In the method of the embodiment of the invention, the second step comprises the following sub-steps:
step S108, performing photolithography on the anode region, that is, defining the first injection region 103 by using a photolithography process. In the method of the embodiment of the invention, the semiconductor power device is FRD, the first conduction type is N type, and the second conduction type is P type, so that the first injection region is 103 bit of the anode region of FRD.
Step S109, p+ implantation and annealing promotion, namely, implantation and annealing promotion of the first implantation region 103 are performed, so as to obtain the first implantation region 103. The P+ implantation is realized by adopting a P well implantation process.
Step three, performing ion implantation of a second conductivity type in the selected region of the first epitaxial layer 102 to form a plurality of second implantation regions, where each of the second implantation regions forms a field limiting ring 104.
In the method of the embodiment of the invention, the third step comprises the following sub-steps:
step S106, field limiting ring lithography, that is, defining the formation region of the field limiting ring 104 by using a lithography process.
Step S107, performing implantation and annealing propulsion of the field limiting ring P, thereby obtaining the field limiting ring 104. The field limiting ring P injection is realized by adopting a P well injection process.
In the method of the embodiment of the present invention, steps S106 and S107 can be placed before steps S108 and S109; it is also possible to finish the implantation in step S109 and the implantation in S107 separately first, and then combine the advances of steps S107 and S109 into one annealing advance implementation. The separate completion of the implantation in step S109 and the implantation in S107 enables a separate independent adjustment of the doping of the first implantation region 103 and the field limiting ring 104.
In other embodiments, step S106 and step S108 are performed simultaneously, and step S107 and step S109 are performed simultaneously, which can save process steps.
Each field limiting ring 104 is formed in the first epitaxial layer 102 outside the first implantation region 103 and has a ring-shaped structure, and the radius of the inner edge of each field limiting ring 104 increases from the outer edge of the first implantation region 103 to the outer edge.
The trench isolation structure 105 is formed between the field stop rings 104, between the innermost field stop ring 104 and the first implantation region 103, and outside the outermost field stop ring 104.
The field limiting rings 104 are contacted with the first epitaxial layer 102 to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure 105 limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of two sides of the first curved surface, and enable the corner positions of two sides of the first curved surface to be located below the top surface of the first epitaxial layer 102, thereby preventing the electric lines of force at the corners of two sides of each first curved surface from being concentrated and enabling the electric lines of force to be far away from the top surface of the first epitaxial layer 102 when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
The method of the embodiment of the invention further comprises the following steps:
an interlayer film 107, a contact hole 108, and a front side metal layer are formed, and the front side metal layer is patterned to form a first electrode 1091 and a termination field plate 1092 of the main junction.
The top surface of the trench isolation structure 105 and the top surface of the first epitaxial layer 102 are leveled, and the interlayer film 107 is formed on the top surfaces of the trench isolation structure 105 and the first epitaxial layer 102.
The contact hole 108 penetrates the interlayer film 107.
The first injection region 103 is connected to the first electrode 1091 through the contact hole 108 corresponding to the top.
Each of the field limiting rings 104 is connected to a corresponding one of the termination field plates 1092 through a top corresponding one of the contact holes 108. The following description will now be made in connection with fig. 2:
the interlayer film 107 is formed. The interlayer film 107 is an oxide layer, and the interlayer film 107 is formed by depositing an oxide dielectric layer and densifying the dielectric layer.
Then, step S110, CT photoetching and etching are carried out; a photolithography process is used to define a formation region of the contact hole 108, and then the interlayer film 107 is etched to form an opening of the contact hole 108 penetrating the interlayer film 107.
Step S111, ion implantation and annealing. For forming a well contact region at the bottom of the opening of the contact hole 108.
And step S112, front metal layer deposition.
Step S113, metal photoetching. That is, the front metal layer is patterned by using a photolithography definition and metal etching process to form the first electrode 1091 and the termination field plate 1092 of the main junction.
And step S114, front passivation layer photoetching. After the front metal layer of the top layer is formed, a passivation layer is further required to be formed, and materials of the passivation layer comprise silicon nitride and polyimide, so that the semiconductor power device is protected. And then, patterning the passivation layer by adopting a photoetching definition and etching process, and forming a lead-out area of the front metal layer of the top layer in the opening area of the passivation layer. Thus completing the fabrication of the top layer structure.
Step S115, electron irradiation and annealing.
Thereafter, a backside process is performed, including:
in step S116, thinning the back surface, thinning the semiconductor substrate 101 to a required thickness, implanting N-type impurities into the back surface, forming a field stop layer by low-temperature annealing or laser annealing, wherein the field stop layer also serves as a back electrode region. While ensuring that the surface impurity concentration is high enough to form an ohmic contact; in selecting the semiconductor substrate 101 with the deep back diffusion layer, the back side impurity implantation and annealing process may not be performed.
Step S117, forming a back metal layer on the back surface of the back electrode region, and forming a back electrode composed of the back metal layer. The back metal layer is deposited by sputtering or evaporating, and finally the back metal layer is subjected to minority carrier lifetime control process treatment to improve the reverse recovery characteristic of the diode.
Step S118, testing and scribing.
According to the embodiment of the invention, the groove isolation structures of the insulating silicide, which are equivalent to the PN junction depth of the field limiting ring, are embedded between the main junction and the field limiting ring, between the field limiting ring and between the field limiting ring and the termination ring, so that the depletion layer and the electric field distribution are flatter when the PN junction is reversely biased, and meanwhile, the electric line originally terminated on the silicon-based surface terminates the dielectric layer of the groove isolation structure, so that the breakdown voltage of the terminal part is more approximate to that of the main junction part, the breakdown voltage of the whole device is improved, and the reverse characteristic of the fast recovery diode is improved.
The method of the embodiment of the invention can be realized by changing the prior art, namely, the prior art of the field oxide layer formed on the silicon substrate surface is only changed to form the trench isolation structure, so that the device structure of the embodiment of the invention can be obtained under the prior art capability, the reverse breakdown voltage and the reverse leakage current of the fast recovery diode can be improved, the application scene of the device is increased, and the reliability of the device is enhanced.
The device provided by the embodiment of the invention has a simple structure, and the small FRD device area is used for achieving the same reliable and stable reverse bias performance (reverse breakdown voltage, reverse leakage current and the like) through the optimization of the terminal area structure, so that the cost of the FRD chip is reduced.
The trench insulating medium isolation is adopted to replace the silicon substrate surface field oxidation isolation, the whole device surface is smoother, and the reliability of the subsequent metal medium layer and the metal layer under a strong electric field can be improved.
The manufacturing process flow of the method of the embodiment of the invention is completely compatible with the existing common FRD process of the power device, a mask layer and a special process are not required to be added, and the scheme is easy to realize.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (16)

1. A termination protection structure for a semiconductor power device, the semiconductor power device comprising a second conductivity type doped first implant region formed in a selected region of a first conductivity type doped first epitaxial layer, the first implant region and the first epitaxial layer forming a main junction;
the terminal protection structure surrounds the periphery of the main junction;
the terminal protection structure includes:
a plurality of field limiting rings, each field limiting ring being comprised of a second implant region doped with a second conductivity type; the field limiting rings are arranged in the first epitaxial layer outside the first injection region and are of annular structures, and the radius of the inner side edge of each field limiting ring sequentially increases from the outer side edge of the first injection region to the outer side edge of the first injection region;
a groove isolation structure is formed among the field limiting rings, between the innermost field limiting ring and the first injection region and outside the outermost field limiting ring, the groove isolation structure is composed of a dielectric layer filled in a first groove, and the first groove is formed in the first epitaxial layer;
the field limiting rings are contacted with the first epitaxial layer to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer, thereby preventing the electric lines of the corners of the two sides of each first curved surface from concentrating and enabling the electric lines of the electric lines to be far away from the top surface of the first epitaxial layer when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
2. The termination protection structure of a semiconductor power device according to claim 1, wherein the termination protection structure further comprises:
a stop ring comprised of heavily doped regions of the first conductivity type, the stop ring being in the first epitaxial layer outside the outermost field limiting ring.
3. The termination protection structure of a semiconductor power device according to claim 1, wherein: a space is provided between the inner side edge of the trench isolation structure and the outer side edge of the first implantation region, which is located between the outer side edge of the first implantation region and the inner side edge of the innermost field limiting ring.
4. The termination protection structure of a semiconductor power device according to claim 2, wherein: the outer side edge of the trench isolation structure located between the inner side edge of the stop ring and the outer side edge of the outermost field stop ring is in contact with or has a spacing from the inner side edge of the stop ring.
5. The termination protection structure of a semiconductor power device according to claim 2, wherein: the bottom surface of the first groove is leveled with the bottom surface of the field limiting ring so as to improve the flatness of a depletion layer formed by depletion of each auxiliary junction when the semiconductor power device is reversely biased.
6. The termination protection structure of a semiconductor power device according to claim 2, wherein the termination protection structure further comprises:
interlayer film, contact hole and front metal layer;
the top surface of the trench isolation structure and the top surface of the first epitaxial layer are leveled, and the interlayer film is formed on the top surfaces of the trench isolation structure and the first epitaxial layer;
the contact hole penetrates through the interlayer film;
the first electrode of the main junction and the terminal field plate are formed by patterning the front metal layer;
the first injection region is connected with the first electrode through the contact hole corresponding to the top;
each field limiting ring is connected to the corresponding terminal field plate through the corresponding contact hole at the top.
7. The termination protection structure of a semiconductor power device according to claim 6, wherein: the first epitaxial layer is formed on the surface of the semiconductor substrate;
the semiconductor substrate is heavily doped with a first conductivity type, and the back electrode area consists of the thinned semiconductor substrate; or the back electrode region is formed by doping the thinned semiconductor substrate with the impurity implanted by the first conductive type heavy doping;
a back electrode composed of a back metal layer is formed on the back surface of the back electrode region.
8. The termination protection structure of a semiconductor power device according to claim 1, wherein: the semiconductor power device includes a fast recovery diode.
9. The termination protection structure of a semiconductor power device according to claim 1, wherein: the process structures of the first injection region and the second injection region are the same or the process structures of the first injection region and the second injection region are independent.
10. A termination protection structure of a semiconductor power device according to any one of claims 1 to 9, characterized in that: the first conductivity type is N type, the second conductivity type is P type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
11. The manufacturing method of the terminal protection structure of the semiconductor power device is characterized by comprising the following steps:
providing a first epitaxial layer with first conductivity type doping, and forming a plurality of first trenches in selected areas of the first epitaxial layer; the first groove is positioned in the forming area of the terminal protection structure;
filling a dielectric layer in each first groove to form a groove isolation structure;
step two, performing ion implantation of a second conductivity type in a selected region of the first epitaxial layer to form a first implantation region; the first injection region and the first epitaxial layer form a main junction;
the terminal protection structure surrounds the periphery of the main junction;
step three, performing ion implantation of a second conductivity type in a selected region of the first epitaxial layer to form a plurality of second implantation regions, wherein each second implantation region respectively forms a field limiting ring;
the field limiting rings are arranged in the first epitaxial layer outside the first injection region and are of annular structures, and the radius of the inner side edge of each field limiting ring sequentially increases from the outer side edge of the first injection region to the outer side edge of the first injection region;
the trench isolation structure is formed among the field limiting rings, between the innermost field limiting ring and the first injection region and outside the outermost field limiting ring;
the field limiting rings are contacted with the first epitaxial layer to form auxiliary junctions; the contact surface of the auxiliary knot is a first curved surface; the trench isolation structure limits the first curved surface from two sides of the first curved surface, so as to reduce the area of the first curved surface, reduce the corner angles of the two sides of the first curved surface and enable the corner positions of the two sides of the first curved surface to be positioned below the top surface of the first epitaxial layer, thereby preventing the electric lines of the corners of the two sides of each first curved surface from concentrating and enabling the electric lines of the electric lines to be far away from the top surface of the first epitaxial layer when the semiconductor power device is reversely biased, and improving the reverse breakdown voltage of the terminal protection structure.
12. The method for manufacturing a terminal protection structure of a semiconductor power device according to claim 11, wherein: after the first step is finished, before or after the second step or the third step, the method further comprises the following steps:
performing first conductivity type heavily doped ion implantation to form a stop ring in the first epitaxial layer outside the outermost field limiting ring.
13. The method for manufacturing a terminal protection structure of a semiconductor power device according to claim 12, wherein: the bottom surface of the first groove is leveled with the bottom surface of the field limiting ring so as to improve the flatness of a depletion layer formed by depletion of each auxiliary junction when the semiconductor power device is reversely biased.
14. The method of manufacturing a termination protection structure for a semiconductor power device according to claim 13, further comprising the steps of:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a first electrode and a terminal field plate of the main junction;
the top surface of the trench isolation structure and the top surface of the first epitaxial layer are leveled, and the interlayer film is formed on the top surfaces of the trench isolation structure and the first epitaxial layer;
the contact hole penetrates through the interlayer film;
the first injection region is connected with the first electrode through the contact hole corresponding to the top;
each field limiting ring is connected to the corresponding terminal field plate through the corresponding contact hole at the top.
15. The method for manufacturing a terminal protection structure of a semiconductor power device according to claim 11, wherein: the semiconductor power device includes a fast recovery diode.
16. The method for manufacturing a terminal protection structure of a semiconductor power device according to claim 11, wherein: the first injection region and the second injection region have the same process structure, and the second injection region and the third injection region are combined together to form the first injection region and the second injection region simultaneously;
or the process structures of the first injection region and the second injection region are independent, and the second step and the third step are carried out separately.
CN202311218614.2A 2023-09-20 2023-09-20 Terminal protection structure of semiconductor power device and manufacturing method thereof Pending CN117253903A (en)

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