CN117251015A - Dynamic chip power supply circuit and method - Google Patents
Dynamic chip power supply circuit and method Download PDFInfo
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- CN117251015A CN117251015A CN202311324247.4A CN202311324247A CN117251015A CN 117251015 A CN117251015 A CN 117251015A CN 202311324247 A CN202311324247 A CN 202311324247A CN 117251015 A CN117251015 A CN 117251015A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 claims abstract description 48
- 239000003381 stabilizer Substances 0.000 claims abstract description 23
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 18
- 230000001276 controlling effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 230000009194 climbing Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000033228 biological regulation Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000013433 optimization analysis Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention provides a dynamic chip power supply circuit and a method. The circuit of the application comprises: the input power supply switching module comprises a voltage stabilizing tube D3 and a triode Q6, and the negative electrode of the voltage stabilizing tube D3 is connected with the base electrode of the triode Q6; the linear voltage stabilizer is connected with the input power supply switching module and comprises a triode Q2, and the collector of the triode Q2 is connected with the drain of the PMOS tube Q4; and the DCDC module circuit is connected with the input power supply switching module. The advantages of the two modules are combined, the power-on time sequence during starting can be met, the low-power-consumption operation after normal starting can be met, the heating is reduced, and the endurance of the battery is greatly improved.
Description
Technical Field
The invention relates to the field of chips, in particular to a dynamic chip power supply circuit and a dynamic chip power supply method.
Background
In the power architecture of the chip itself, a linear voltage regulator is generally used, and the voltage stability is realized by forming a voltage drop between a voltage regulator tube and a triode by the linear voltage regulator. As shown in fig. 5 and 6, there is a certain timing requirement in the chip power supply, for example, when DRV outputs or VSENSE senses power input, v_out_1 needs microsecond rise time to reach the threshold, and the linear adjustment module of Q1 is used to meet the timing requirement. However, the architecture has the defect of high power consumption, the power supply efficiency of the chip power supply circuit is extremely low, if the load end is a battery, the endurance of the battery can be greatly reduced, further, the heat productivity can be more serious due to higher power consumption, and the additional heat dissipation design or the Q1 package increase is needed in the hardware design to improve the power, so that the hardware design cost is increased.
Disclosure of Invention
Therefore, the invention aims to provide a dynamic chip power supply circuit and a method, which aim to run with low power consumption and reduce heat generation after normal start and increase the endurance of a battery on the premise of meeting the power-on time sequence during start.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a first aspect of the present invention provides a dynamic chip power supply circuit comprising:
the input power supply switching module comprises a voltage stabilizing tube D3 and a triode Q6, wherein the negative electrode of the voltage stabilizing tube D3 is connected with the base electrode of the triode Q6, the voltage stabilizing tube D3 is used for detecting whether the voltage of the input power supply reaches a stable value or not and controlling the on or off of the Q6 according to the voltage so as to control the working state of a subsequent module;
the linear voltage stabilizer is connected with the input power supply switching module and comprises a triode Q2, and the collector of the triode Q2 is connected with the drain of the PMOS tube Q4;
and the DCDC module circuit is connected with the input power supply switching module.
In some embodiments, the linear voltage regulator and the DCDC module circuit are connected to a chip U3.
In some embodiments, the emitter of the triode Q6 is connected to the source of the PMOS transistor Q4, and the emitter of the triode Q2 is connected to the power input pin of the chip U3.
In some embodiments, the negative electrode of the voltage regulator D3 is connected to the base of the transistor Q8, the emitter of the transistor Q8 is connected to the ground, the collector of the transistor Q8 is connected to the first end of the resistor R14 and the gate of the PMOS transistor Q7, the second end of the resistor R14 is connected to the first end of the resistor R10 and the source of the PMOS transistor Q7, the drain of the PMOS transistor Q7 is connected to the first end of the resistor R5, the second end of the resistor R5 is connected to the second end of the resistor R12 and the base of the transistor Q5, the emitter of the transistor Q5 is connected to the second end of the resistor R12 and the ground, the collector of the transistor Q5 is connected to the first end of the resistor R6, the second end of the resistor R6 is connected to the gate of the PMOS transistor Q3, the drain of the PMOS transistor Q3 is connected to the input of the DCDC module circuit, and the output of the DCDC module circuit is connected to the power supply pin of the chip U3.
In some embodiments, the drain electrode of the PMOS transistor Q7 is connected to a first end of a resistor R13, a second end of the resistor R13 is connected to an enable end of the DCDC module circuit and a negative electrode of the regulator D6, and a positive electrode of the regulator D6 is connected to a ground end.
In some embodiments, the output terminal of the DCDC module circuit is connected to the positive electrode of the schottky diode D5, the negative electrode of the schottky diode D5 is connected to the power input pin of the chip U3, the emitter of the triode Q2 is connected to the positive electrode of the schottky diode D4, and the negative electrode of the schottky diode D4 is connected to the power input pin of the chip U3.
In some embodiments, the linear regulator adjustment pin of the chip U3 is connected to the first end of the resistor R10, the second end of the resistor R10 is connected to the base of the transistor Q2, the power input detection pin of the chip U3 is connected to the power input end and the first end of the resistor R8, the second end of the resistor R8 is connected to the first end of the resistor R4 and the second end of the resistor R6, and the second end of the resistor R4 is connected to the first section of the resistor R8 and the source of the PMOS transistor Q3.
In some embodiments, the second end of the resistor R8 is connected to the first end of the resistor R9, the emitter of the triode Q6, and the source of the PMOS transistor Q4, the second end of the resistor R9 is connected to the first end of the resistor R7, the collector of the triode Q6, and the gate of the PMOS transistor Q4, the second end of the resistor R7 is connected to the ground and the first end of the resistor R11, and the second end of the resistor R11 is connected to the positive electrode of the regulator D3 and the base of the triode Q8.
The application also provides a dynamic chip power supply method, which comprises the following steps:
when the input voltage is lower than the regulated value, the linear voltage stabilizer is conducted, and the output voltage of the linear voltage stabilizer supplies power for the chip;
when the input voltage is higher than the voltage stabilizing value, the DCDC module circuit is conducted, and the output voltage of the DCDC module circuit supplies power for the chip.
In some embodiments, the method further comprises the steps of:
in the power supply climbing process, the DCDC module circuit is cut off, and is conducted by the linear voltage stabilizer and outputs voltage to supply power for the chip;
after the chip is normally started, the linear voltage stabilizer is cut off, and the DCDC module circuit is conducted and outputs voltage to supply power for the chip.
According to the dynamic chip power supply circuit and the dynamic chip power supply method, the working voltage is provided for the chip through dynamic switching between the linear voltage stabilizer and the DCDC module circuit, different voltages are input to the input power supply switching module, corresponding modules in the linear voltage stabilizer and the DCDC module circuit are switched to work, the advantages of the two modules are combined, the power-on time sequence during starting can be met, the low-power-consumption operation after normal starting can be met, the heating is reduced, and the cruising ability of the battery is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a dynamic chip power supply circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a dynamic chip power supply circuit in the prior art;
FIG. 3 is a flowchart of an embodiment of a dynamic chip power method according to an embodiment of the present invention;
FIG. 4 is a flowchart of an embodiment of a dynamic chip power method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a prior art chip power supply;
fig. 6 is a schematic diagram of a power supply of a chip in the prior art.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear and obvious, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Aiming at the problems that in the prior art, the power supply efficiency of a chip power supply circuit is low, if a load end is a battery, the cruising ability of the battery can be greatly reduced, and further, the heating value can be more serious due to larger power consumption, and the power is improved by the additional heat dissipation design or the Q1 package is increased in the hardware design, so that the hardware design cost is increased.
Referring to fig. 5 and 6, as shown in fig. 5 and 6, the power architecture of the chip itself has a certain time sequence requirement in the power supply of U1, for example, when DRV outputs or VSENSE senses power input, v_out_1 needs microsecond rising time to reach a threshold, and the linear adjustment module of Q1 is used to meet the time sequence requirement. However, this architecture has the disadvantage of high power consumption, for example: if the operating current of U1 is 20ma, V1 is 50V, v_out_1=8v, the power consumption of the chip itself is as follows:
P_U1＝V_OUT_1*I＝8V*0.02A＝0.16W
P_Q1＝(V1-V_OUT_1)*0.02A＝(50-8)*0.02＝0.84W
η＝P_U1/P_tot＝0.16W/(0.02*50)＝16％；
the following disadvantages are calculated from the above:
the power supply efficiency of the chip power supply circuit is extremely low;
if the load end is a battery, the endurance of the battery is greatly reduced;
the power consumption of the Q1 is larger, the heating value is also serious, and an additional heat dissipation design is needed in the hardware design or the package of the Q1 is increased to improve the power, so that the hardware design cost is increased.
Some terms and functions that may appear are explained below:
an input power supply switching module: this module plays a key role in controlling the switching of the input power. The voltage stabilizing tube D3 is used for detecting whether the voltage of the input power supply reaches a stable value or not and controlling the on or off of the triode Q6 according to the voltage, so as to control the working state of the subsequent module.
Linear voltage stabilizer: the module is connected with the input power supply switching module, the linear voltage stabilizer can provide stable voltage for the chip, and the linear voltage stabilizer is faster to power on relative to a DCDC module circuit, can meet the power on time sequence requirement, and has the defect of high power consumption.
DCDC module circuit: the module circuit is connected with the input power supply switching module, and the DCDC module circuit is a circuit design for converting input voltage into stable output voltage required by the chip. It is typically composed of a dc/dc converter that converts the voltage of one dc power source to another dc voltage power source. In the application, the characteristic of low power consumption is mainly utilized, and the disadvantage of the method is slow power-on and cannot meet the power-on time sequence.
In fig. 5, VSENSE is a power input detection pin of the chip, DRV is a linear regulator regulation pin, v_out_1 is an input pin of the power supply, and R2 is a total input end of the power supply. When the VSENSE senses the power input when the power input exists, the Q1 is powered by the DRV control output V_OUT_1 for the rear stage U1, and the R2 is a resistor and is mainly used for limiting current and transferring dissipation power.
The following describes in detail a specific technical scheme of the embodiment of the present application:
embodiment one:
the present invention provides a dynamic chip power supply circuit, please refer to fig. 2, comprising:
the input power supply switching module 200 comprises a voltage stabilizing tube D3 and a triode Q6, wherein the negative electrode of the voltage stabilizing tube D3 is connected with the base electrode of the triode Q6, the voltage stabilizing tube D3 is used for detecting whether the voltage of the input power supply reaches a stable value or not and controlling the on or off of the Q6 according to the voltage so as to control the working state of a subsequent module;
the linear voltage stabilizer 300 is connected with the input power supply switching module 200, the linear voltage stabilizer 300 comprises a triode Q2, and the collector of the triode Q2 is connected with the drain of a PMOS tube Q4;
and a DCDC module circuit 400, wherein the DCDC module circuit 400 is connected to the input power switching module 200.
Referring to fig. 1, the linear voltage regulator 300 and the DCDC module circuit 400 are connected to a chip U3500.
Referring to fig. 1, an emitter of the triode Q6 is connected to a source of the PMOS transistor Q4, and an emitter of the triode Q2 is connected to a power input pin of the chip U3500.
Referring to fig. 1, the negative electrode of the voltage regulator D3 is connected to the base of the transistor Q8, the emitter of the transistor Q8 is connected to the ground, the collector of the transistor Q8 is connected to the first end of the resistor R14 and the gate of the PMOS transistor Q7, the second end of the resistor R14 is connected to the first end of the resistor R10 and the source of the PMOS transistor Q7, the drain of the PMOS transistor Q7 is connected to the first end of the resistor R5, the second end of the resistor R5 is connected to the second end of the resistor R12 and the base of the transistor Q5, the emitter of the transistor Q5 is connected to the second end of the resistor R12 and the ground, the collector of the transistor Q5 is connected to the first end of the resistor R6, the second end of the resistor R6 is connected to the gate of the PMOS transistor Q3, the drain of the PMOS transistor Q3 is connected to the input terminal of the DCDC module circuit 400, and the output terminal of the DCDC module circuit 400 is connected to the 3500 power input pin of the chip U.
Referring to fig. 1, the drain of the PMOS transistor Q7 is connected to a first end of a resistor R13, a second end of the resistor R13 is connected to an enable end of the DCDC module circuit 400 and a negative electrode of a regulator tube D6, and a positive electrode of the regulator tube D6 is connected to a ground end.
Referring to fig. 1, an output end of the DCDC module circuit 400 is connected to an anode of a schottky diode D5, a cathode of the schottky diode D5 is connected to a power input pin of the chip U3500, an emitter of the triode Q2 is connected to an anode of a schottky diode D4, and a cathode of the schottky diode D4 is connected to a power input pin of the chip U3500.
Referring to fig. 1, the regulation pin of the linear voltage regulator 300 of the chip U3500 is connected to the first end of the resistor R10, the second end of the resistor R10 is connected to the base of the transistor Q2, the power input detection pin of the chip U3500 is connected to the power input 100 and the first end of the resistor R8, and the power input detection pin of the chip U3500 is at the input end of the DCDC module circuit 400, so that the chip U3500 can sense the input voltage of the battery end and provide power for the regulation pin of the linear voltage regulator 300. The second end of the resistor R8 is connected with the first end of the resistor R4 and the second end of the resistor R6, and the second end of the resistor R4 is connected with the first section of the resistor R8 and the source electrode of the PMOS tube Q3.
Referring to fig. 1, a second end of the resistor R8 is connected with a first end of the resistor R9, an emitter of the triode Q6 and a source of the PMOS transistor Q4, the second end of the resistor R9 is connected with a first end of the resistor R7, a collector of the triode Q6 and a gate of the PMOS transistor Q4, a second end of the resistor R7 is connected with a ground end and a first end of the resistor R11, and a second end of the resistor R11 is connected with an anode of the regulator D3 and a base of the triode Q8. The working principle is as follows:
when the input voltage is lower than the regulated value of D3: the voltage regulator tube D3 is cut off, the triode Q6 is cut off, the PMOS tube Q4 is conducted, at the moment, V3 does not reach the voltage stabilizing value of the voltage regulator tube D3, so the triode Q8 is cut off, at the moment, the potential of the resistor R10 is DRV voltage, at the moment, the PMOS tube Q4 supplies power for the triode Q2, and the output voltage supplies power for the chip U3.
At the moment, the PMOS tube Q7 is not conducted, so that the triode Q5 is cut off, the PMOS tube Q3 is also cut off, the EN potential of the DCDC is 0V, and the DCDC module is not provided with power input, is not enabled, does not work and has extremely low power consumption;
when the V3 input voltage is higher than the regulated value of D3: at this time, the voltage stabilizing tube D3 is conducted, the triode Q6 is conducted, the PMOS tube Q4 is turned off, and the triode Q2 has no power input, so that the linear voltage stabilizer stops working;
the triode Q8 is conducted, so that the PMOS tube Q7 is conducted, the triode Q5 is conducted, the PMOS tube Q3 is also conducted to be a DCDC module input power supply, DRV is input to an EN pin of DCDC, and the DCDC module circuit starts to work;
the two power supplies complete the power supply switching at diode D4 and diode D5.
The present application was then subjected to performance optimization analysis:
DCDC input 50V, output 8V:
P_BUCK_OUT＝8V*0.02A＝0.16W；
if the efficiency of the designed DCDC module circuit is 80%, the input parameters of DCDC are as follows:
P_DCDC_I N＝0.16W/0.8＝0.2W；
I_DCDC_I N＝0.2W/50V＝4mA；
compared with the scheme of FIG. 5, the power consumption is reduced to 1/5 of the original power consumption, the power consumption of the chip is greatly reduced, and if V3 is a battery, the cruising ability of the chip U3 is greatly improved, so that the optimization effect is considerable.
Embodiment two:
referring to fig. 4, in the process of starting the chip and after starting, the method for supplying power to the dynamic chip provided by the invention further comprises the following steps:
s100, in the power supply climbing process;
s200, conducting by a linear voltage stabilizer and outputting voltage to supply power for the chip;
s300, after the chip is started normally;
s400, the DCDC module circuit is conducted and outputs voltage to supply power for the chip.
It can be understood that, by utilizing the voltage induction characteristic of the VSENSE pin and the action characteristic of the DRV pin of the power supply U3, a DCDC module circuit and a linear voltage stabilizer circuit are skillfully combined together, and can be adjusted by external input voltage, so that the two circuits are smoothly switched. The problem of high power consumption is solved, so that the power consumption of the chip is reduced, and the problem of heating of peripheral devices is solved; the Q2 circuit module also solves the defect that DCDC is electrified slowly and cannot meet the electrifying time sequence, and the cruising ability of the battery can be greatly improved.
When the designer desires the V3 power source to be within a certain low voltage range, please refer to fig. 3, which includes the following steps:
s110, when the input voltage is lower than a voltage stabilizing value;
s210, conducting by the linear voltage stabilizer and outputting voltage to supply power for the chip.
It can be understood that the linear voltage stabilizer is conducted and outputs voltage to supply power to the chip, so as to meet the power timing requirement of the chip U3, and ensure that the chip U3 can be normally started to enter the NORMAL mode.
When the designer desires the V3 power source to be within a certain high voltage range, please refer to fig. 3, which includes the following steps:
s310, when the input voltage is higher than the voltage stabilizing value;
s410, the DCDC module circuit is turned on and outputs voltage to supply power to the chip,
it can be appreciated that the input power supply switching module and the DCDC module circuit are adopted, and a proper working mode can be selected according to the input voltage, so that the power supply efficiency is improved. In particular, in a high-voltage range, the DCDC module circuit supplies power, so that the power consumption is lower, and the energy loss is effectively reduced.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and thus do not limit the scope of the claims of the present invention. Those skilled in the art will appreciate that many modifications are possible in which the invention is practiced without departing from its scope or spirit, e.g., features of one embodiment can be used with another embodiment to yield yet a further embodiment. Any modification, equivalent replacement and improvement made within the technical idea of the present invention should be within the scope of the claims of the present invention.
Claims (10)
1. A dynamic chip power supply circuit, comprising:
the input power supply switching module comprises a voltage stabilizing tube D3 and a triode Q6, wherein the negative electrode of the voltage stabilizing tube D3 is connected with the base electrode of the triode Q6, the voltage stabilizing tube D3 is used for detecting whether the voltage of the input power supply reaches a stable value or not and controlling the on or off of the Q6 according to the voltage so as to control the working state of a subsequent module;
the linear voltage stabilizer is connected with the input power supply switching module and comprises a triode Q2, and the collector of the triode Q2 is connected with the drain of the PMOS tube Q4;
and the DCDC module circuit is connected with the input power supply switching module.
2. The dynamic chip power supply circuit of claim 1, wherein the linear voltage regulator and the DCDC module circuit are connected to a chip U3.
3. The dynamic chip power supply circuit according to claim 2, wherein an emitter of the triode Q6 is connected to a source of the PMOS transistor Q4, and an emitter of the triode Q2 is connected to a power input pin of the chip U3.
4. A dynamic chip power supply circuit according to claim 3, wherein the negative electrode of the voltage regulator D3 is connected to the base of the transistor Q8, the emitter of the transistor Q8 is connected to the ground, the collector of the transistor Q8 is connected to the first end of the resistor R14 and the gate of the PMOS transistor Q7, the second end of the resistor R14 is connected to the first end of the resistor R10 and the source of the PMOS transistor Q7, the drain of the PMOS transistor Q7 is connected to the first end of the resistor R5, the second end of the resistor R5 is connected to the second end of the resistor R12 and the base of the transistor Q5, the emitter of the transistor Q5 is connected to the second end of the resistor R12 and the ground, the collector of the transistor Q5 is connected to the first end of the resistor R6, the second end of the resistor R6 is connected to the gate of the PMOS transistor Q3, the drain of the PMOS transistor Q3 is connected to the input of the DCDC module circuit, and the output of the DCDC module is connected to the input pin of the power supply circuit U3.
5. The dynamic chip power supply circuit according to claim 4, wherein the drain electrode of the PMOS transistor Q7 is connected to a first end of a resistor R13, a second end of the resistor R13 is connected to an enable end of the DCDC module circuit and a negative electrode of a regulator D6, and a positive electrode of the regulator D6 is connected to a ground end.
6. The dynamic chip power supply circuit according to claim 5, wherein an output terminal of the DCDC module circuit is connected to an anode of a schottky diode D5, a cathode of the schottky diode D5 is connected to a power input pin of the chip U3, an emitter of the triode Q2 is connected to an anode of a schottky diode D4, and a cathode of the schottky diode D4 is connected to a power input pin of the chip U3.
7. The dynamic chip power supply circuit according to claim 6, wherein the linear regulator adjustment pin of the chip U3 is connected to the first end of the resistor R10, the second end of the resistor R10 is connected to the base of the transistor Q2, the power input detection pin of the chip U3 is connected to the power input end and the first end of the resistor R8, the second end of the resistor R8 is connected to the first end of the resistor R4 and the second end of the resistor R6, and the second end of the resistor R4 is connected to the first section of the resistor R8 and the source of the PMOS transistor Q3.
8. The dynamic chip power supply circuit according to claim 7, wherein a second end of the resistor R8 is connected to a first end of the resistor R9, an emitter of the transistor Q6, and a source of the PMOS transistor Q4, a second end of the resistor R9 is connected to a first end of the resistor R7, a collector of the transistor Q6, and a gate of the PMOS transistor Q4, a second end of the resistor R7 is connected to a ground terminal and a first end of the resistor R11, and a second end of the resistor R11 is connected to an anode of the regulator D3 and a base of the transistor Q8.
9. The dynamic chip power supply method is characterized by comprising the following steps of:
when the input voltage is lower than the regulated value, the linear voltage stabilizer is conducted, and the output voltage of the linear voltage stabilizer supplies power for the chip;
when the input voltage is higher than the voltage stabilizing value, the DCDC module circuit is conducted, and the output voltage of the DCDC module circuit supplies power for the chip.
10. The method of dynamic chip power supply according to claim 9, further comprising the steps of:
in the power supply climbing process, the DCDC module circuit is cut off, and is conducted by the linear voltage stabilizer and outputs voltage to supply power for the chip;
after the chip is normally started, the linear voltage stabilizer is cut off, and the DCDC module circuit is conducted and outputs voltage to supply power for the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311324247.4A CN117251015A (en) | 2023-10-12 | 2023-10-12 | Dynamic chip power supply circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311324247.4A CN117251015A (en) | 2023-10-12 | 2023-10-12 | Dynamic chip power supply circuit and method |
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| Publication Number | Publication Date |
|---|---|
| CN117251015A true CN117251015A (en) | 2023-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311324247.4A Pending CN117251015A (en) | 2023-10-12 | 2023-10-12 | Dynamic chip power supply circuit and method |
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| CN (1) | CN117251015A (en) |
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- 2023-10-12 CN CN202311324247.4A patent/CN117251015A/en active Pending
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