CN117238738A - Vertical structure vacuum channel transistor based on wide bandgap material and preparation method thereof - Google Patents
Vertical structure vacuum channel transistor based on wide bandgap material and preparation method thereof Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000000903 blocking effect Effects 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 13
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 12
- 229910002601 GaN Inorganic materials 0.000 claims description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 7
- 239000010980 sapphire Substances 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 3
- 239000002090 nanochannel Substances 0.000 abstract description 3
- 230000004044 response Effects 0.000 abstract description 3
- 230000005641 tunneling Effects 0.000 abstract description 3
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Abstract
The invention discloses a vertical structure vacuum channel transistor based on a wide band gap material and a preparation method thereof, wherein the transistor comprises the following components: the semiconductor device comprises a substrate, a first electrode, a first dielectric layer, a second electrode, a gate blocking dielectric, a second dielectric layer, a third electrode and a plurality of channels; the method comprises the steps of sequentially arranging a substrate, a first electrode, a first dielectric layer, a second electrode, a gate blocking dielectric, a second dielectric layer and a third electrode from bottom to top; the invention can make the transistor smaller in size compression, the dimension of the vacuum nano channel is smaller than the average free path of electrons in air, so that the transportation of carriers in the channel meets the field electron emission or tunneling mode, and the invention has high response speed and high cut-off frequency; the channel is concave inwards, so that collision between electrons and the dielectric layer is reduced, and stability of the device is improved.
Description
Technical Field
The invention relates to the technical field of vacuum electronic devices, in particular to a vertical structure vacuum channel transistor based on a wide forbidden band material and a preparation method thereof.
Background
As integrated circuits continue to shrink, the size of transistors gradually approaches the nanometer scale, but at the nanometer scale, transistors encounter some physical limitations and challenges. For example, with extremely small dimensions, problems such as quantum effects and leakage of transistors become more pronounced, resulting in increased power consumption and reduced performance. To overcome these problems, researchers have begun to explore new nano-transistor technologies, where nano-vacuum channel transistors are a field of great interest.
Nano-vacuum channel transistor (NVCT) is a novel transistor technology. The basic principle of NVCT technology is to create a vacuum channel at the nanoscale, allowing electrons to be transported in vacuum. The movement of electrons in vacuum is less impeded, and NVCT is excellent in high frequency applications because there is no scattering and interaction of charge carriers in vacuum, and electrons can move more freely than in conventional semiconductor transistors. The vacuum environment can reduce interaction of electrons and impurities, so that the nano vacuum channel transistor has better stability and reliability under the high radiation environment. Nanotechnology can achieve extremely small dimensions of devices, and thus nanovacuum channel transistors have the potential to achieve higher density integrated circuits, thereby increasing the functionality and performance of the devices. However, NVCT technology also faces a number of technical challenges, such as how to achieve a stable vacuum environment, how to effectively control the movement of electrons, etc. The new structure is thus designed and viable manufacturing methods and material choices are found to make NVCT a viable technique.
Disclosure of Invention
The invention aims to: the invention aims to provide a vertical structure vacuum channel transistor based on a wide band gap material and a preparation method thereof, which reduce gate leakage current through innovation of a transistor structure, lead a device to be miniaturized and be convenient for on-chip integration, and facilitate research on influence of different emitter materials and morphologies on device performance.
The technical scheme is as follows: the invention relates to a vertical structure vacuum channel transistor based on a wide band gap material, which comprises: the semiconductor device comprises a substrate, a first electrode, a first dielectric layer, a second electrode, a gate blocking dielectric, a second dielectric layer, a third electrode and a plurality of channels; the method comprises the steps of sequentially arranging a substrate, a first electrode, a first dielectric layer, a second electrode, a gate blocking dielectric, a second dielectric layer and a third electrode from bottom to top; a plurality of channels penetrate through the first electrode, the first dielectric layer, the second electrode, the gate blocking dielectric and the second dielectric layer; the first electrode, the second electrode and the third electrode are connected with an external circuit through wires.
Further, the first electrode is used as a cathode, and the specific material is N-type silicon-doped gallium nitride.
Further, the second electrode is used as a gate electrode, and the specific material is a conductive material which is easy to oxidize and can form a compact oxide layer.
Further, the third electrode is used as an anode, and the specific material is a metal material which is not easy to oxidize, such as gold, platinum, and the like.
Further, the substrate is made of sapphire, silicon carbide and the like.
Further, the first dielectric layer and the second dielectric layer are made of silicon oxide, aluminum oxide or hafnium oxide.
Further, the gate blocking dielectric is made of the same material as the first dielectric layer.
Further, the thickness of the second electrode is 5-10 nm; the thickness of the first dielectric layer is 10-12 nm, and the thickness of the second dielectric layer is 40-45 nm.
Further, the total thickness of the first dielectric layer, the second electrode and the second dielectric layer is smaller than 80nm.
The invention relates to a preparation method of a vertical structure vacuum channel transistor based on a wide band gap material, which comprises the following steps:
(1) Preparation of a first electrode: preparing an N-type gallium nitride epitaxial layer on a sapphire, silicon or silicon carbide substrate through a gallium nitride epitaxial process;
(2) Preparing a first dielectric layer: preparing a first dielectric layer on the first electrode by a magnetron sputtering or chemical vapor deposition method;
(3) Preparing a second electrode: preparing a conductive material which is easy to oxidize and can form a compact oxide layer on the first dielectric layer by a magnetron sputtering or electron beam evaporation method, and taking the conductive material as a second electrode of a transistor grid electrode;
(4) Preparing a second dielectric layer: preparing a layer of medium on the second electrode by a magnetron sputtering or chemical vapor deposition method, wherein the medium layer covers the opening and the upper surface of the second electrode and completely covers the step at the opening of the second electrode, the medium layer serves as a gate blocking medium, and then a layer of medium is prepared on the gate blocking medium, and the medium layer serves as a second medium layer which is different from the material of the first medium layer;
(5) And (3) preparing a third electrode: preparing a third electrode on the second dielectric layer through a magnetron sputtering or electron beam evaporation process;
(6) Vacuum channel preparation: forming a vertical channel in the center of the device by ICP etching and using ion-enhanced etching, and chemically etching the second dielectric layer to obtain a nano vacuum channel with etching width of 20-30 nm, wherein the channel penetrates through the first dielectric layer, the second electrode, the gate barrier dielectric layer and the second dielectric layer;
(7) Preparing a gate blocking medium: and (3) placing the device in an oxygen atmosphere for high-temperature annealing, and forming an oxide film on the contact surface of the side wall of the second electrode and the channel to serve as a gate blocking medium.
The beneficial effects are that: compared with the prior art, the invention has the following remarkable advantages: the transistor can be compressed in size, the dimension of the vacuum nano channel is smaller than the average free path of electrons in air, so that the transportation of carriers in the channel meets the field electron emission or tunneling mode, and the vacuum nano channel has high response speed, high cut-off frequency and high reliability; the grid electrode of the transistor structure is surrounded by the dielectric layer, so that the leakage current of the grid electrode can be effectively reduced; the channel is concave inwards, so that collision between electrons and the dielectric layer is reduced, and stability of the device is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a transistor structure according to the present invention;
FIG. 2 is a schematic top view of a transistor vacuum channel array according to the present invention;
FIG. 3 is a schematic diagram of the transistor structure of the present invention;
fig. 4 is a schematic cross-sectional view of a transistor recess structure according to the present invention.
Description of the embodiments
The technical scheme of the invention is further described below with reference to the accompanying drawings.
As shown in fig. 1-2, an embodiment of the present invention provides a vertical structure vacuum channel transistor based on a wide bandgap material, including: the semiconductor device comprises a substrate 1, a first electrode 2, a first dielectric layer 3, a second electrode 4, a gate blocking dielectric 5, a second dielectric layer 6, a third electrode 7 and a plurality of channels 8; the method comprises the steps that a substrate 1, a first electrode 2, a first dielectric layer 3, a second electrode 4, a gate blocking dielectric 5, a second dielectric layer 6 and a third electrode 7 are arranged in sequence from bottom to top; a plurality of channels 8 penetrate through the first electrode 2, the first dielectric layer 3, the second electrode 4, the gate blocking dielectric 5 and the second dielectric layer 6; the first electrode 2, the second electrode 4 and the third electrode 7 are connected to an external circuit through wires.
The first electrode 2 is used as a cathode, and the specific material is N-type silicon-doped gallium nitride. The second electrode 4 serves as a gate electrode, and a specific material is a conductive material which is easily oxidized and can form a dense oxide layer. The third electrode 7 serves as an anode (collector), and is made of a metal material which is not easily oxidized, such as gold or platinum. The substrate 1 is made of sapphire, silicon carbide and the like. The first dielectric layer 3 and the second dielectric layer 6 are made of insulating materials such as silicon oxide, aluminum oxide or hafnium oxide. The gate blocking dielectric 5 is made of the same material as the first dielectric layer 3. The thickness of the second electrode 4 is 5-10 nm; the thickness of the first dielectric layer 3 is 10-12 nm, and the thickness of the second dielectric layer 6 is 40-45 nm. The total thickness of the first dielectric layer 3, the second electrode 4 and the second dielectric layer 6 is less than 80nm; the transportation of carriers in the channel meets the field electron emission or tunneling mode, and has the technical advantages of high response speed, high cut-off frequency, high reliability and the like;
as shown in fig. 3, when a bias voltage is applied to the transistor, va is a voltage between the cathode and the anode, vg is a voltage between the cathode and the gate, and when the field intensity of the cathode emission surface is increased by applying the voltage, the potential barrier of electrons is lowered, and field emission occurs by easily breaking off the potential barrier. When the device is simulated, when the anode voltage with the constant grid voltage is changed within a certain range, the field emission current is hardly affected; when the anode voltage is unchanged, the gate voltage is changed, and the field emission current is changed. The device controls electron emission by changing the grid voltage and the anode voltage, thereby realizing the modulation function of channel current.
As shown in fig. 4, this embodiment also provides a vertical structure vacuum channel transistor based on a wide bandgap material, including: a wide bandgap material based vertical structure vacuum channel transistor comprising: the substrate 1, the first electrode 2, the first dielectric layer 3, the second electrode 4, the gate blocking dielectric 5, the second dielectric layer 6, the third electrode 7, a plurality of channels 8 and grooves 9; the method comprises the steps that a substrate 1, a first electrode 2, a first dielectric layer 3, a second electrode 4, a gate blocking dielectric 5, a second dielectric layer 6 and a third electrode 7 are arranged in sequence from bottom to top; a plurality of channels 8 penetrate through the first electrode 2, the first dielectric layer 3, the second electrode 4, the gate blocking dielectric 5 and the second dielectric layer 6; the recess 9 is formed by etching the first electrode 2; the first electrode 2, the second electrode 4 and the third electrode 7 are connected to an external circuit through wires. The gate leakage current can be reduced and the field emission current can be improved by changing the structure of the first electrode 2. In addition, the channel 8 with the array structure can increase the effective area for electron emission or collection and improve the current emission capability of the device.
The first electrode 2 is used as a cathode, and the specific material is N-type silicon-doped gallium nitride. The second electrode 4 serves as a gate electrode, and a specific material is a conductive material which is easily oxidized and can form a dense oxide layer. The third electrode 7 serves as an anode (collector), and is made of a metal material which is not easily oxidized, such as gold or platinum. The substrate 1 is made of sapphire, silicon carbide and the like. The first dielectric layer 3 and the second dielectric layer 6 are made of insulating materials such as silicon oxide, aluminum oxide or hafnium oxide. The gate blocking dielectric 5 is made of the same material as the first dielectric layer 3. The thickness of the second electrode 4 is 5-10 nm; the thickness of the first dielectric layer 3 is 10-12 nm, and the thickness of the second dielectric layer 6 is 40-45 nm. The total thickness of the first dielectric layer 3, the second electrode 4 and the second dielectric layer 6 is less than 80nm.
The embodiment of the invention also provides a preparation method of the vertical structure vacuum channel transistor based on the wide band gap material, which comprises the following steps:
(1) Preparation of a first electrode: preparing an N-type gallium nitride epitaxial layer on a sapphire, silicon or silicon carbide substrate through a gallium nitride epitaxial process;
(2) Preparing a first dielectric layer: preparing a first dielectric layer on the first electrode by a magnetron sputtering or chemical vapor deposition method;
(3) Preparing a second electrode: preparing a conductive material which is easy to oxidize and can form a compact oxide layer on the first dielectric layer by a magnetron sputtering or electron beam evaporation method, and taking the conductive material as a second electrode of a transistor grid electrode;
(4) Preparing a second dielectric layer: preparing a layer of medium on the second electrode by a magnetron sputtering or chemical vapor deposition method, wherein the medium layer covers the opening and the upper surface of the second electrode and completely covers the step at the opening of the second electrode, the medium layer serves as a gate blocking medium, and then a layer of medium is prepared on the gate blocking medium, and the medium layer serves as a second medium layer which is different from the material of the first medium layer;
(5) And (3) preparing a third electrode: preparing a third electrode on the second dielectric layer through a magnetron sputtering or electron beam evaporation process;
(6) Vacuum channel preparation: forming a vertical channel in the center of the device by ICP etching and using ion-enhanced etching, and chemically etching the second dielectric layer to obtain a nano vacuum channel with etching width of 20-30 nm, wherein the channel penetrates through the first dielectric layer, the second electrode, the gate barrier dielectric layer and the second dielectric layer;
(7) Preparing a gate blocking medium: and (3) placing the device in an oxygen atmosphere for high-temperature annealing, and forming an oxide film on the contact surface of the side wall of the second electrode and the channel to serve as a gate blocking medium.
Claims (10)
1. A wide bandgap material based vertical structure vacuum channel transistor, comprising: the semiconductor device comprises a substrate (1), a first electrode (2), a first dielectric layer (3), a second electrode (4), a gate blocking dielectric (5), a second dielectric layer (6), a third electrode (7) and a plurality of channels (8); the method comprises the steps that a substrate (1), a first electrode (2), a first dielectric layer (3), a second electrode (4), a gate blocking dielectric (5), a second dielectric layer (6) and a third electrode (7) are arranged in sequence from bottom to top; a plurality of channels (8) penetrate through the first electrode (2), the first dielectric layer (3), the second electrode (4), the gate blocking dielectric (5) and the second dielectric layer (6); the first electrode (2), the second electrode (4) and the third electrode (7) are connected with an external circuit through leads.
2. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the first electrode (2) is used as a cathode, and the specific material is N-type silicon-doped gallium nitride.
3. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the second electrode (4) is used as a grid electrode, and a specific material is a conductive material which is easy to oxidize and can form a compact oxide layer.
4. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the third electrode (7) is used as an anode, and the material is gold or platinum.
5. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the substrate (1) is made of sapphire, silicon or silicon carbide.
6. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the first dielectric layer (3) and the second dielectric layer (6) are made of silicon oxide, aluminum oxide or hafnium oxide.
7. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the grid blocking medium (5) is made of the same material as the first medium layer (3).
8. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the thickness of the second electrode (4) is 5-10 nm; the thickness of the first dielectric layer (3) is 10-12 nm, and the thickness of the second dielectric layer (6) is 40-45 nm.
9. A wide bandgap material based vertical structure vacuum channel transistor as claimed in claim 1, wherein: the total thickness of the first dielectric layer (3), the second electrode (4) and the second dielectric layer (6) is smaller than 80nm.
10. A method of fabricating a wide bandgap material based vertical structure vacuum channel transistor according to claim 1, comprising the steps of:
(1) Preparation of a first electrode: preparing an N-type gallium nitride epitaxial layer on a sapphire, silicon or silicon carbide substrate through a gallium nitride epitaxial process;
(2) Preparing a first dielectric layer: preparing a first dielectric layer on the first electrode by a magnetron sputtering or chemical vapor deposition method;
(3) Preparing a second electrode: preparing a conductive material which is easy to oxidize and can form a compact oxide layer on the first dielectric layer by a magnetron sputtering or electron beam evaporation method, and taking the conductive material as a second electrode of a transistor grid electrode;
(4) Preparing a second dielectric layer: preparing a layer of medium on the second electrode by a magnetron sputtering or chemical vapor deposition method, wherein the medium layer covers the opening and the upper surface of the second electrode and completely covers the step at the opening of the second electrode, the medium layer serves as a gate blocking medium, and then a layer of medium is prepared on the gate blocking medium, and the medium layer serves as a second medium layer which is different from the material of the first medium layer;
(5) And (3) preparing a third electrode: preparing a third electrode on the second dielectric layer through a magnetron sputtering or electron beam evaporation process;
(6) Vacuum channel preparation: forming a vertical channel in the center of the device by ICP etching and using ion-enhanced etching, and chemically etching the second dielectric layer to obtain a nano vacuum channel with etching width of 20-30 nm, wherein the channel penetrates through the first dielectric layer, the second electrode, the gate barrier dielectric layer and the second dielectric layer;
(7) Preparing a gate blocking medium: and (3) placing the device in an oxygen atmosphere for high-temperature annealing, and forming an oxide film on the contact surface of the side wall of the second electrode and the channel to serve as a gate blocking medium.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180286621A1 (en) * | 2017-03-31 | 2018-10-04 | Palo Alto Research Center Incorporated | Semiconductor-free vacuum field effect transistor fabrication and 3d vacuum field effect transistor arrays |
| CN109801830A (en) * | 2018-12-30 | 2019-05-24 | 中国电子科技集团公司第十二研究所 | A kind of vacuum channel transistor and preparation method thereof |
| CN113506824A (en) * | 2020-09-10 | 2021-10-15 | 安藤善文 | Vacuum channel field effect transistor, method of manufacturing the same, and semiconductor device |
| CN115497785A (en) * | 2022-09-13 | 2022-12-20 | 南通职业大学 | Grid-shaped air channel transistor and preparation method thereof |
| CN116469764A (en) * | 2023-04-25 | 2023-07-21 | 西安交通大学 | Vertical structure field emission transistor and preparation method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180286621A1 (en) * | 2017-03-31 | 2018-10-04 | Palo Alto Research Center Incorporated | Semiconductor-free vacuum field effect transistor fabrication and 3d vacuum field effect transistor arrays |
| CN109801830A (en) * | 2018-12-30 | 2019-05-24 | 中国电子科技集团公司第十二研究所 | A kind of vacuum channel transistor and preparation method thereof |
| CN113506824A (en) * | 2020-09-10 | 2021-10-15 | 安藤善文 | Vacuum channel field effect transistor, method of manufacturing the same, and semiconductor device |
| CN115497785A (en) * | 2022-09-13 | 2022-12-20 | 南通职业大学 | Grid-shaped air channel transistor and preparation method thereof |
| CN116469764A (en) * | 2023-04-25 | 2023-07-21 | 西安交通大学 | Vertical structure field emission transistor and preparation method thereof |
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