CN117222234B - Semiconductor device based on UCie interface - Google Patents
Semiconductor device based on UCie interface Download PDFInfo
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- CN117222234B CN117222234B CN202311473581.6A CN202311473581A CN117222234B CN 117222234 B CN117222234 B CN 117222234B CN 202311473581 A CN202311473581 A CN 202311473581A CN 117222234 B CN117222234 B CN 117222234B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 18
- 239000012792 core layer Substances 0.000 claims description 4
- 238000013473 artificial intelligence Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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Abstract
The application provides a semiconductor device based on UCie interface, including: the system comprises an SoC module and a storage module; the SoC module comprises an SoC crystal grain, and at least one first UCIe interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure; the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; the second interconnection structure does not comprise a silicon intermediate layer, so that the memory capacity, scale, yield and performance of the AI chip can be improved, and the cost and the thermal interference risk are reduced.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device based on a uci interface.
Background
Currently mainstream AI (Artificial Intelligence ) powerful chips typically use HBM (High Bandwidth Memory ) as a storage device. Fig. 1 is a schematic diagram of a conventional AI chip package structure, and as shown in fig. 1, the conventional AI chip package structure has the following problems in the application process:
1. HBMs must be placed in close proximity to Die edges along the SoC (System on a Chip), while HBM typically has a 12mm side size, and within a limited SoC side size, the number of HBMs that can be connected is limited, resulting in limited memory capacity.
2. The DRAM (Dynamic Random Access Memory ) structure of the HBM is sensitive to heat, and in order to ensure that the HBM can work normally, the AI (Artificial Intelligence ) chip requires high cooling cost, and the temperature difference between the HBM and the SoC can cause thermal x-talk (thermal interference) problems.
3. The HBM host IP (intellectual property core ) on the SoC must remain the same technology as the SoC and the HBM IP area reaches 30mm 2 Occupies a larger area proportion of the SoC.
4. The interconnection between the HBM and the SoC adopts a Si Interposer, and the size of the Interposer can only support 3-4 reticles at present, so that the scale of the whole chip is limited. The 2.5D package using an interposer is more expensive than the standard package, and suffers from the shortage of CoWos productivity and long production period. Also, for connection to the silicon interposer, the chip is designed with micro bumps that cannot be fully tested at a safer level, which also presents yield issues.
Disclosure of Invention
The application provides a semiconductor device based on a UCie interface, which is used for solving the problems of limited memory capacity and chip scale, high cost, thermal interference risk and low yield of the packaging structure of the conventional AI chip.
The application provides a semiconductor device based on UCie interface, including:
the system comprises an SoC module and a storage module;
the SoC module comprises an SoC crystal grain, and at least one first UCie interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure;
the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; wherein the second interconnect structure does not include a silicon interposer.
According to the semiconductor device based on the UCie interface, the first interconnection structure is a rewiring layer.
According to the semiconductor device based on the UCie interface, the second interconnection structure is a combination of a rewiring layer and an organic substrate.
According to the semiconductor device based on the UCie interface, the second interconnection structure is a rewiring layer.
According to the semiconductor device based on the UCie interface, the first interconnection structure is an embedded crystal grain.
According to the semiconductor device based on the UCie interface, the second interconnection structure is an organic substrate.
According to the semiconductor device based on the UCie interface, the second interconnection structure is a rewiring layer.
According to the semiconductor device based on the UCie interface, for any memory unit, the total UCie bandwidth corresponding to the second UCie interface IP in the combined crystal grain is matched with the bandwidth of the HBM stack crystal grain, and accordingly, the number of interface groups in the second UCie interface IP is calculated based on the line rate and the data bit width of the HBM stack crystal grain and a single interface group.
According to the semiconductor device based on the UCie interface, for any joint grain, the interface group included in the second UCie interface IP is arranged in a single column along the edge of the joint grain, and when the length of the single column exceeds that of the HBM IP, the semiconductor device is split into multiple columns to be closely arranged.
According to the semiconductor device based on the UCie interface, the organic substrate is of a multi-layer structure and comprises a high-speed signal wiring layer, a core layer, a power signal layer and a ground signal layer.
The application provides a semiconductor device based on UCie interface, includes: the system comprises an SoC module and a storage module; the SoC module comprises an SoC crystal grain, and at least one first UCie interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure; the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; the second interconnection structure does not comprise a silicon intermediate layer, and SoC and HBM can be decoupled by adopting a combined crystal grain, so that the memory capacity, the chip scale, the yield and the performance of the AI chip are improved, and the cost and the thermal interference risk are reduced.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a package structure of a conventional AI chip;
fig. 2 is a schematic structural diagram of a semiconductor device based on uci interface provided in the present application;
FIG. 3 is one of the schematic views of the interconnection patterns of the semiconductor device provided herein;
FIG. 4 is a second schematic illustration of an interconnection scheme for a semiconductor device provided herein;
FIG. 5 is a third schematic illustration of an interconnection scheme for a semiconductor device provided herein;
FIG. 6 is a schematic diagram of an interconnection scheme for a semiconductor device provided herein;
FIG. 7 is a schematic view of the internal structure of the joint die provided herein;
fig. 8 is a graph comparing the packaging effect of the semiconductor device provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 2 is a schematic structural diagram of a semiconductor device based on uci (Universal Chiplet Interconnect Express, universal chiplet interconnect channel) interface provided in the present application, as shown in fig. 2, including:
the system comprises an SoC module and a storage module;
the SoC module comprises an SoC crystal grain, and at least one first UCie interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure;
the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; wherein the second interconnect structure does not include a silicon interposer.
Specifically, as can be seen from fig. 1 and the foregoing, in the conventional AI chip packaging structure, the SoC and the HBM must be coupled together, and the processes are the same, based on which, the problems of limited memory capacity, high cooling cost, thermal interference, large area occupied by the HBM IP by the SoC, limitation of the whole chip scale due to the fact that the interconnection between the HBM and the SoC can only adopt Si interser, short productivity, long production cycle, yield and the like are caused. Aiming at the problems, the application finds that only the SoC and the HBM can be decoupled, based on the problems, the semiconductor device based on the UCIe interface in the embodiment of the application is provided, a joint die (M2 LINK for short later) is formed by adopting an interface IP (namely a second UCIe interface IP) conforming to the international standard UCIe protocol and the HBM IP, and meanwhile, a first UCIe interface IP is added at the edge of the SoC die, so that the HBM IP is moved out of the SoC die, and the decoupling between the SoC and the HBM memory is realized. Because uci may support standard 2D package interconnection (i.e., an organic substrate is adopted), the second uci interface IP on the joint die and the first uci interface IP on the SoC die may not need to be interconnected through a silicon interposer, the HBM IP on the joint die is interconnected with the HBM stack (i.e., HBM stack die) through a first interconnect structure, and the HBM IP and the second uci interface IP are interconnected through an on-chip bus (e.g., AMBA AXI4.0 bus), so that data exchange between the SoC and the HBM memory of the main chip may be realized. Through the whole scheme, the tight coupling framework between the existing HBM memory and the existing SoC crystal grains can be broken through, and decoupling of the SoC memory and the existing HBM memory is achieved. It is understood that the HBM stack Die includes a Base Die (i.e., base Die) and a plurality of semiconductor memory dies stacked on the Base Die. The base die and the plurality of semiconductor memory dies may be coupled using a coupling structure of through silicon vias and metal electrodes (i.e., micro bumps) such as solder.
More specifically, for the arrangement of the interconnection structures, fig. 3 is one of schematic diagrams of the interconnection manner of the semiconductor device provided in the present application, as shown in fig. 3, where the first interconnection structure is a redistribution layer (i.e. ReDistribution Layer, RDL layer), and the second interconnection structure is a combination of the redistribution layer and the organic substrate (i.e. Organic Substrate). The UCIe (namely the second UCIe interface IP) on the combined crystal grain and the UCIe (the first UCIe interface IP) on the SoC can be interconnected through the RDL layer and the organic substrate without a silicon intermediate layer, the HBM IP on the combined crystal grain is interconnected with the HBM stack signal through the RDL layer and is packaged in an RDL-based package, and the second UCIe interface IP and the HBM IP are interconnected through an on-chip bus, so that the data exchange between the SoC of the main chip and the HBM memory can be realized. It will be appreciated that the first interconnect structure and the second interconnect structure surfaces are each provided with a solder structure (i.e., a circular structure in fig. 3) to connect the die to the corresponding interconnect structure. It is noted that the organic substrate has a multi-layer structure, including a high-speed signal routing layer, a core layer (core layer), a power signal layer and a ground signal layer, and the specific layer number and functional distribution thereof can be flexibly adjusted according to actual design requirements.
Because the signal density supportable by the RDL layer during interconnection is higher than that of the organic substrate, the interconnection between the grains can be realized by combining the RDL layer and the organic substrate, so that the number of layers of the organic substrate is reduced, and the technical threshold and the cost are reduced. Fig. 4 is a second schematic diagram of an interconnection manner of the semiconductor device provided in the present application, as shown in fig. 4, where the first interconnection structure and the second interconnection structure are both redistribution layers, based on which uci on a joint die (i.e., the second uci interface IP) and uci on an SoC (the first uci interface IP) may be interconnected through an RDL layer, and HBM IP on the joint die may also be interconnected through an RDL layer and HBM stack signals. Meanwhile, signals among the three grains, namely the combined grain, the HBM stack grain and the SoC grain, can be distributed in the RDL layer and the organic substrate for interconnection according to the requirement of signal integrity, so that the whole chip memory expansion is realized.
In addition, as the performance increases, the number of signals increases, and the routing density requirements increase further, for which case the embodiments of the present application further improve the interconnect structure. Specifically, fig. 5 is a third schematic diagram of an interconnection manner of the semiconductor device provided in the present application, as shown in fig. 5, the first interconnection structure is an Embedded Die (i.e., an Embedded Die), and the second interconnection structure is an organic substrate. Based on this, a higher density of signal interconnections between HBM IP and HBM Stack can be achieved, while uci on the joint die (i.e., second uci interface IP) and uci on the SoC (first uci interface IP) can still be interconnected through the organic substrate. Fig. 6 is a schematic diagram of an interconnection manner of the semiconductor device provided in the present application, and as shown in fig. 6, the first interconnection structure is an embedded die, and the second interconnection structure is a redistribution layer. Based on the above, on the basis of achieving the higher-density interconnection effect, as the performance of the RDL layer is better, smaller bump pitch can be adopted when the RDL is adopted for interconnection, so that the size of the combined crystal grain can be further reduced, the bandwidth matching with the HBM can be realized in a smaller crystal grain area, and the optimization of the performance and the cost can be achieved.
It is noted that for any memory cell, the total bandwidth of uci corresponding to the second uci interface IP in the joint die matches the bandwidth of the HBM stack die, and accordingly, the number of interface groups in the second uci interface IP is calculated based on the line rate and data bit width of the HBM stack die and the single interface group.
Specifically, when adding uci interfaces to expand the memory capacity and bandwidth of AI large chips, considering the influence on performance, uci of multiple modules (i.e. interface groups) must be used to match the bandwidth of HBM, and meanwhile, the problems of IP area, implementation complexity, cost and the like need to be considered. In performing bandwidth matching, the number of interface groups in the second uci interface IP needs to be calculated based on the HBM stack die and the line rate and data bit width of the individual interface groups. Taking HBM3 memory with a line rate of 6.4Gbps and a data bit width of 1024 bits as an example, one HBM3 has a maximum bandwidth of 6.4×1024=819 GB, one module of uci with standard package has a data bit width of 16 bits and a line rate of 32Gbps as a maximum, so that the total uci bandwidth of one module is 32×16=64 GB, and then 819/64=13 modules of uci is needed for matching the bandwidth of HBM3, and about 14 modules of uci is needed in consideration of bandwidth utilization and other problems.
On the basis of the above, the embodiment of the present application further optimizes the setting manner of the second uci interface IP to reduce the area of the combined grains to the maximum extent, specifically, for any combined grain, the interface group included in the second uci interface IP is arranged in a single column along the edge of the combined grain, and when the length of the single column exceeds the HBM IP, the interface group is split into multiple columns to be closely arranged.
Fig. 7 is a schematic diagram of the internal structure of the combined die provided in the present application, and as shown in fig. 7, if uci of 14 modules is completely placed along the edge of the die during floorplan (i.e. planar layout) planning of the combined die, the surface width of the die occupied by uci reaches 18-19 mm, and the width of HBM IP is only 8.2mm, which is in close proximity with the formed shape, so that a large amount of waste of the area of the combined die is caused, which is not beneficial to cost control of the die. Based on this, the embodiment of the application considers the rationality of floorplan, and puts the uci of 14 modules along the edge of the grain in a two-column manner, so that the uci occupies half of the grain surface width, which is about 10mm.
In summary, in the semiconductor device based on the uci interface according to the embodiment of this application, the SoC and the HBM are decoupled by adopting the joint die, so that the process of HBM IP and the process of SoC may be different, and when the SoC performs process iteration, the joint die may remain unchanged in the original process, so that flexibility is improved, chip iteration time is shortened, and overall cost is reduced. In addition, the chip scale is not limited by the size of the silicon interposer any more, and the chip scale is enlarged. Meanwhile, a silicon intermediate layer is not needed, so that the packaging cost is greatly reduced. The RDL layer and the organic substrate layer are adopted for grain interconnection, and a chip enterprise has more selection space when packaging is realized.
More importantly, the UCie interface interconnection in the combined crystal grain can support a distance of up to 25mm, more HBM stacks can be connected through distance adjustment when the UCie interface interconnection is interconnected with the SoC, and the increase of the memory capacity can improve the chip performance. Fig. 8 is a comparison chart of packaging effects of the semiconductor device provided by the application, and as shown in fig. 8, researches show that the semiconductor device based on the uci interface in the embodiment of the application can improve the HBM size from 96GB to 128GB and improve the memory capacity by 33% under the same SoC scale. In addition, the joint crystal grain is adopted to decouple the SoC and the HBM, so that the distance between the DRAM and the SoC is increased, the DRAM can be cooled in a targeted manner, the cooling cost is reduced, meanwhile, the thermal X-talk between the SoC and the HBM is also greatly improved, the SoC can achieve higher main frequency, and the performance is improved.
The semiconductor device based on the UCie interface provided by the embodiment of the application comprises: the system comprises an SoC module and a storage module; the SoC module comprises an SoC crystal grain, and at least one first UCie interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure; the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; the second interconnection structure does not comprise a silicon intermediate layer, and SoC and HBM can be decoupled by adopting a combined crystal grain, so that the memory capacity, the chip scale, the yield and the performance of the AI chip are improved, and the cost and the thermal interference risk are reduced.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. A uci interface-based semiconductor device comprising:
the system comprises an SoC module and a storage module;
the SoC module comprises an SoC crystal grain, and at least one first UCie interface IP is integrated at the edge of the SoC crystal grain; the storage module comprises at least one storage unit matched with the first UCie interface IP; the storage unit comprises a combined grain and an HBM stack grain, the combined grain comprises an HBM IP and a second UCIe interface IP, the HBM IP and the second UCIe interface IP are interconnected through an on-chip bus, and the HBM IP is in signal interconnection with the HBM stack grain through a first interconnection structure;
the first UCIe interface IP in the SoC crystal grain is in signal interconnection with the second UCIe interface IP in the matched storage unit through a second interconnection structure; wherein the second interconnect structure does not include a silicon interposer.
2. The uci interface based semiconductor device of claim 1, wherein the first interconnect structure is a redistribution layer.
3. The uci interface based semiconductor device of claim 2, wherein the second interconnect structure is a combination of a redistribution layer and an organic substrate.
4. The uci interface based semiconductor device of claim 2, wherein the second interconnect structure is a redistribution layer.
5. The uci interface-based semiconductor device of claim 1, wherein the first interconnect structure is an embedded die.
6. The uci interface based semiconductor device of claim 5, wherein the second interconnect structure is an organic substrate.
7. The uci interface based semiconductor device of claim 5, wherein the second interconnect structure is a redistribution layer.
8. The uci interface based semiconductor device of claim 1 wherein for any memory cell, the total bandwidth of uci corresponding to a second uci interface IP in the joint die matches the bandwidth of the HBM stack die, and the number of interface groups in the second uci interface IP is calculated based on the line rate and data bit width of the HBM stack die and the individual interface groups.
9. The uci interface based semiconductor device according to claim 8, wherein the second uci interface IP comprises interface groups that are arranged in a single column along the edge of the joint die for any joint die, and split into multiple columns that are closely arranged when the single column length exceeds the HBM IP.
10. The uci interface-based semiconductor device according to claim 3 or 6, wherein the organic substrate is a multi-layered structure comprising a high-speed signal trace layer, a core layer, a power signal layer, and a ground signal layer.
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| WO2023056876A1 (en) * | 2021-10-08 | 2023-04-13 | 寒武纪(西安)集成电路有限公司 | Longitudinal stacked chip, integrated circuit device, board, and manufacturing method therefor |
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