CN115036303A

CN115036303A - Calculation microsystem based on TSV primary integration and LTCC secondary integration

Info

Publication number: CN115036303A
Application number: CN202210699535.7A
Authority: CN
Inventors: 赵超; 郭雁蓉; 匡乃亮; 赵国良; 李庆
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2022-06-20
Filing date: 2022-06-20
Publication date: 2022-09-09

Abstract

The invention discloses a calculation micro-system based on TSV primary integration and LTCC secondary integration, which comprises a CPU micro-module, a NAND micro-module, an SSD micro-module, an FPGA micro-module, a first DDR3 micro-module and a second DDR3 micro-module; the CPU micro module and the FPGA micro module adopt a 2.5D-TSV integration process to electrically connect the bare chip to the LTCC substrate; the NAND micro-module, the first DDR3 micro-module and the second DDR3 micro-module are all stacked in a multi-chip isomorphic mode by adopting a 3D-TSV reconfiguration integration process and are electrically connected with the LTCC substrate; the SSD micro-module adopts a 2.5D-TSV and 3D-TSV mixed integration process to perform multi-chip heterogeneous stacking and is electrically connected with the LTCC substrate; the NAND micro-module is used for big data storage, and the first DDR micro-module and the second DDR micro-module are used for high-speed data caching. The satellite load information processing capacity can be greatly improved, and the requirements of high reliability and small size are met.

Description

Calculation microsystem based on TSV primary integration and LTCC secondary integration

Technical Field

The invention belongs to the field of semiconductor integration, and particularly belongs to a calculation microsystem based on TSV primary integration and LTCC secondary integration.

Background

The complex space radiation environment, limited satellite-to-satellite energy and satellite-to-ground data transmission bandwidth always restrict the application service capability of the satellite, and are the main pain points for the development of the satellite industry. How to improve the intelligent level of the satellite and enable the satellite to better and more quickly transmit more valuable information to the ground is the key point for improving the value of the whole industrial chain of the satellite. The traditional satellite mainly adopts low-performance aerospace-level components, the technology of the components is relatively conservative, the processing capacity is poor, and the intelligent level is low, so that the application service capacity of the traditional satellite cannot meet the requirement of intelligent operation of the current business.

The microsystem is a modular product with system level functions, which is formed by organically integrating various chips. The application of the microsystem technology can provide great assistance for a microsatellite, but is limited by the current process limitation of an anti-radiation component, and the yield of the existing high-performance microsystem product for space application can not be large enough to meet the requirements of small-volume high-performance application represented by a star chain, a micro-nano satellite and the like.

The conventional satellite mainly adopts complete machine products of low-performance aerospace-level components and PCB assembly technology, and the products have the advantages of relatively conservative technology, poorer processing capability, lower intelligent level, large volume and heavy weight and are not enough to meet the application requirements of the future microsatellite.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a calculation micro-system based on TSV primary integration and LTCC secondary integration, which can greatly improve the satellite load information processing capacity and meet the requirements of high reliability and small size.

In order to achieve the purpose, the invention provides the following technical scheme:

a calculation micro-system based on TSV primary integration and LTCC secondary integration comprises a CPU micro-module, a NAND micro-module, an SSD micro-module, an FPGA micro-module, a first DDR3 micro-module and a second DDR3 micro-module;

the CPU micro module and the FPGA micro module adopt a 2.5D-TSV integration process to electrically connect a bare chip to the LTCC substrate;

the NAND micro-module, the first DDR3 micro-module and the second DDR3 micro-module are all stacked in a multi-chip isomorphic mode by adopting a 3D-TSV reconstruction integration process and are electrically connected with the LTCC substrate;

the SSD micro-module adopts a 2.5D-TSV and 3D-TSV mixed integration process to perform multi-chip heterogeneous stacking and is electrically connected with the LTCC substrate;

the CPU micro module and the FPGA micro module perform bidirectional data interaction through a bidirectional high-speed serial bus; the SSD micro-module and the FPGA micro-module perform bidirectional data interaction through a bidirectional high-speed serial bus; the CPU micro module and the second DDR3 micro module perform bidirectional data interaction through a parallel bus; the FPGA micro-module and the first DDR3 micro-module perform bidirectional data interaction through a parallel bus; the NAND micro-module and the SSD micro-module perform bidirectional data interaction through a parallel bus;

the NAND micro-module is used for big data storage, and the first DDR micro-module and the second DDR micro-module are used for high-speed data caching.

Preferably, a CPU bare chip in the CPU micro module is in an inverted form; the CPU micro-module adopts a 2.5D-TSV silicon substrate as an intermediate layer to connect a CPU bare chip to an LTCC substrate.

Preferably, the NAND micro-module is formed by stacking and integrating 8 layers of NAND FLASH chips and 1 layer of IPD passive termination chips, wherein a NAND FLASH bare chip is embedded in a TSV silicon substrate and is reconstructed through RDL rewiring, and layers are vertically interconnected through micro bumps.

Preferably, the FPGA bare chip in the FPGA micro-module is in an inverted form; the FPGA micro-module adopts a 2.5D-TSV silicon substrate as an intermediary layer to connect the FPGA bare chip to the LTCC substrate.

Preferably, the second DDR3 micro-module is formed by stacking and integrating a 3-layer DDR3 memory chip and a 1-layer IPD passive termination chip, the DDR3 bare chip is embedded in the TSV silicon substrate, reconfigured by RDL rewiring, and vertically interconnected by micro bumps between layers.

Preferably, the first DDR micro module is formed by stacking and integrating a 5-layer DDR3 memory chip and a 1-layer IPD passive termination chip, a DDR3 bare chip is embedded in a TSV silicon substrate and is reconfigured through RDL rewiring, and layers are vertically interconnected through micro bumps.

Preferably, the SSD micro-module comprises an SSD controller chip and a DDR3 bare chip, the SSD controller chip is mounted on the 2.5D-TSV silicon substrate in a flip-chip manner, the DDR3 bare chip is reconfigured embedded in the TSV silicon substrate, and stacked by the interlayer micro-bumps to form the heterogeneous micro-module.

Preferably, the LTCC substrate is a high-expansion low-temperature co-fired ceramic substrate, and copper is adopted as a multilayer metal wiring layer inside the LTCC substrate.

Preferably, the bottom of the LTCC substrate is provided with a pin, the pin is a high lead soldering column, and the pin is welded on a bonding pad at the bottom of the LTCC substrate.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides a calculation microsystem based on TSV primary integration and LTCC secondary integration, and the product performance volume ratio of the microsystem is improved by more than one order of magnitude through a novel high-performance processor, large-capacity storage, application of a super-large-scale FPGA and a TSV and LTCC secondary integration process. By applying the 3D stacked memory based on the TSV embedding reconstruction process, the memory capacity and the integration density of a system are greatly improved, and the overall performance of a product reaches or even exceeds the performance of the current industrial-level space product; all chips adopt anti-radiation and anti-radiation design and process and packaged anti-radiation reinforcement to ensure the anti-radiation performance of the microsystem, so that the anti-single particle and anti-total dose performance of the microsystem reaches the performance of a traditional space electronic system, and the application reliability and the service life of a product in space are ensured; the microsystem product realized based on the micro-assembly process has high electrical performance and high reliability, has a small volume of 50mm multiplied by 6mm, and the satellite based on the microsystem has lower volume weight and lower application cost.

Furthermore, based on the integration process of the TSV micro module, the thermal resistance of each chip is guaranteed to be extremely small under the condition that the integration density of the system is greatly improved, the internal junction temperature is lower during working, the service life of a product is longer, in addition, the small salient points are converted into the large salient points through the TSV silicon substrate, and the welding yield of a large area array of multiple components can be greatly improved.

Furthermore, the novel ceramic substrate based on high expansion low temperature co-firing has better CTE (coefficient of thermal expansion) matching property on the premise of meeting multilayer wiring and ultrahigh signal rate, can ensure lower thermal stress and higher reliability by material transition with the bare chip and the PCB (printed circuit board).

Furthermore, the application based on the high-lead welding column can reduce the thermodynamic stress from the PCB to the ceramic tube shell, so that the welding spot is not separated in a long-term thermal cycle environment, and the reliability is higher.

Drawings

FIG. 1 is a schematic diagram of a computational microsystem based on TSV primary integration and LTCC secondary integration according to the present invention;

in the drawings: 1 is the CPU micromodule, 2 is the NAND micromodule, 3 is the SSD micromodule, 4 is the FPGA micromodule, 5 is the LTCC base plate, 6 is first DDR3 micromodule, 7 is the pin, 8 is second DDR3 micromodule.

Detailed Description

The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.

As shown in fig. 1, the computing micro-system based on TSV primary integration and LTCC secondary integration of the present invention includes a CPU micro-module 1, a NAND micro-module 2, an SSD micro-module 3, an FPGA micro-module 4, an LTCC substrate 5, a first DDR3 micro-module 6, and a second DDR3 micro-module 8.

The CPU micro module 1 and the FPGA micro module 4 adopt a 2.5D-TSV integration process to electrically connect a bare chip to the LTCC substrate 5; the NAND micro-module 2, the first DDR3 micro-module 6 and the second DDR3 micro-module 8 are all stacked in a multi-chip isomorphic mode by adopting a 3D-TSV reconstruction integration process and are electrically connected with the LTCC substrate 5; the SSD micro-module 3 adopts a 2.5D-TSV and 3D-TSV mixed integration process to perform multi-chip heterogeneous stacking, and is electrically connected with the LTCC substrate 5.

The CPU micro module 1 and the FPGA micro module 4 carry out bidirectional data interaction through a bidirectional high-speed serial bus; the SSD micro-module 3 and the FPGA micro-module 4 perform bidirectional data interaction through a bidirectional high-speed serial bus; the CPU micro module 1 and the second DDR3 micro module 8 carry out bidirectional data interaction through a parallel bus; the FPGA micro-module 4 and the first DDR3 micro-module 6 perform bidirectional data interaction through a parallel bus; the NAND micro-module 2 and the SSD micro-module 3 carry out bidirectional data interaction through a parallel bus;

the NAND micro-module 2 is used for big data storage, and the first DDR micro-module 6 and the second DDR micro-module 8 are used for high-speed data caching.

The CPU micro-module 1 adopts a TSV silicon substrate as an intermediate layer, a CPU bare chip is in flip-chip welding on the TSV silicon substrate to form the CPU micro-module, and the micro-module is in flip-chip welding on the LTCC substrate; the NAND micro-module 2 realizes 8+1 stacking through TSV embedding reconstruction, namely stacking integration of 8 layers of NAND FLASH chips and 1 layer of IPD passive termination chips, vertical interconnection between layers is realized through micro bumps, and interconnection between the lowest layer and the LTCC substrate is realized through solder balls; the SSD micro-module 3 realizes the stacking of the SSD controller chip and the DDR3 chip by two layers of 2.5D-TSV silicon substrates in a POP mode; the FPGA micro-module 4 adopts a TSV silicon substrate as an intermediate layer, an FPGA bare chip is subjected to flip-chip welding on the 2.5D-TSV silicon substrate to form the FPGA micro-module, and the micro-module is subjected to flip-chip welding on the LTCC substrate; the LTCC substrate 5 is formed by sintering copper as a plurality of metal wiring layers at a low temperature.

The first DDR3 micro-module 6 is formed by stacking five DDR3 silicon substrates and one IPD chip, firstly, a cavity is formed in the TSV silicon substrate, a DDR3 bare chip is embedded in the cavity, an active TSV silicon substrate is formed through RDL rewiring, namely, a TSV reconstruction process is carried out, and the silicon substrate of the five reconstructed DDR3 bare chip and the IPD chip are interconnected through interlayer micro-bumps; the second DDR3 micro module 8 and the first DDR3 micro module 6 are integrated in the same method, except that the active silicon substrate is integrated into 3 layers; the pin 7 is a high lead solder column, and the pin 7 is soldered on a pad of the LTCC substrate 5.

The high performance computing microsystem of the present invention starts with high performance processing, high bandwidth interconnect and high density storage.

The high-performance processing chip can not be separated, and in the invention, the design of a new generation of multi-core anti-irradiation processor, a super-large-scale irradiation-resistant FPGA and a high-performance high-reliability SSD controller is selected to achieve the high-efficiency fusion of general calculation, parallel calculation and rapid storage. The selected new generation of anti-radiation processor is an 8-core processor, the single-core processing dominant frequency reaches 1.5GHz, each CPU core is of a double-emission structure and is provided with an independent primary 32KB data cache and a 32KB instruction cache, 8 CPU cores share a 1MB secondary cache, the fixed-point performance is 24GIPS, the floating point is 48GFLOPS, the built-in reconfigurable neural network acceleration engine has high-energy-efficiency intelligent processing capability and 8TOPS processing capability, and a 4MB high-capacity memory is integrated inside the CPU core.

The parallel computing adopts a customized co-processing unit based on the FPGA, the FPGA is 6900 ten thousand gates and has irradiation resistance, the co-processing unit based on the customized specific application in the FPGA is realized by adopting a SIMD (single instruction multiple data) structure processor core, the processor core consists of a decoding control unit, an arithmetic logic unit, a memory access management unit, a tracking cache unit and a configurable timer unit, and the operational performance reaches 100 GFLOPS.

The high-performance high-reliability SSD controller is of a dual-core structure, the kernel adopts an ARMv7R structure and an 8-level assembly line, a single ALU unit is realized in the assembly line, and the execution of double instruction streams can be realized by efficiently using effective resources. And designing a tightly coupled memory port and integrating a private Cache memory to realize low-delay access to the on-chip memory. The transmission control part is a control arbitration and cache management mechanism of a data path in the whole controller, and mainly comprises a DMA module which is used for controlling data transmission between peripheral equipment and TCM, OCM. AES and SM4 encryption modes are supported on the data path.

In the invention, the CPU and the FPGA realize bidirectional transmission through SRIO 4X, the SSD controller and the FPGA realize bidirectional transmission through PCIe 4X, and the bandwidth reaches 40 Gbps; DDR3 buses are adopted between the CPU and the DDR3 memory, between the FPGA and the DDR3 memory, and between the SSD controller and the DDR3 memory.

In the invention, the high-density storage comprises a DDR3 fast large-capacity memory and a NAND FLASH super-large-capacity memory unit, and a plurality of radiation-resistant DDR3 memories and a radiation-resistant NAND FLASH memory are integrated in a microsystem to form large data storage.

According to the invention, the novel high-performance CPU, FPGA and SSD controller chips are adopted to improve the performance of the micro-system product by more than one order of magnitude, the storage capacity and the integration density of the system are greatly improved by the application of the 3D stacked memory based on the TSV embedding reconstruction process, and the overall performance of the product reaches or even exceeds the performance of the current industrial space product.

All the chips adopt anti-irradiation and anti-irradiation chips and packaged anti-irradiation reinforcement to ensure the anti-irradiation performance of the microsystem, so that the anti-single particle and anti-total dose performance of the microsystem can reach the performance of a traditional space electronic system, and the application reliability and the service life of a product in space are ensured; the integration process based on the TSV micro-module ensures that the thermal resistance of each chip is extremely small under the condition that the integration density of the system is greatly improved, the internal junction temperature is lower during working, the service life of a product is longer, and in addition, the small salient point and the large salient point are converted through the TSV silicon substrate, so that the welding yield of a multi-component large-area array can be greatly improved.

The novel ceramic substrate based on the LTCC has better CTE (coefficient of thermal expansion) matching property on the premise of meeting multilayer wiring and 10Gbps signal rate, and can ensure lower thermal stress and higher reliability due to transition between the novel ceramic substrate and a bare chip and a PCB (printed circuit board).

The high-lead welding column based application can reduce the thermodynamic stress from the PCB to the ceramic tube shell, so that the welding spot is not separated in a long-term thermal cycle environment, and the reliability is higher.

The microsystem product realized based on the micro-assembly process has high electrical performance and high reliability, has a small volume of 50mm multiplied by 6mm, and the satellite based on the microsystem has lower volume weight and lower application cost.

Claims

1. A calculation micro-system based on TSV primary integration and LTCC secondary integration is characterized by comprising a CPU micro-module (1), a NAND micro-module (2), an SSD micro-module (3), an FPGA micro-module (4), a first DDR3 micro-module (6) and a second DDR3 micro-module (8);

the CPU micro module (1) and the FPGA micro module (4) adopt a 2.5D-TSV integration process to electrically connect a bare chip to the LTCC substrate (5);

the NAND micro-module (2), the first DDR3 micro-module (6) and the second DDR3 micro-module (8) are all stacked in a multi-chip isomorphic mode by adopting a 3D-TSV reconstruction integration process and are electrically connected with the LTCC substrate (5);

the SSD micro-module (3) adopts a 2.5D-TSV and 3D-TSV mixed integration process to perform multi-chip heterogeneous stacking, and is electrically connected with the LTCC substrate (5);

the CPU micro module (1) and the FPGA micro module (4) carry out bidirectional data interaction through a bidirectional high-speed serial bus; the SSD micro-module (3) and the FPGA micro-module (4) carry out bidirectional data interaction through a bidirectional high-speed serial bus; the CPU micro module (1) and the second DDR3 micro module (8) carry out bidirectional data interaction through a parallel bus; the FPGA micro-module (4) and the first DDR3 micro-module (6) perform bidirectional data interaction through a parallel bus; the NAND micro-module (2) and the SSD micro-module (3) perform bidirectional data interaction through a parallel bus;

the NAND micro module (2) is used for big data storage, and the first DDR micro module (6) and the second DDR micro module (8) are used for high-speed data caching.

2. The TSV primary integration and LTCC secondary integration based computing microsystem as claimed in claim 1, wherein a CPU bare chip in the CPU micromodule (1) is in a flip-chip form; the CPU micro module (1) adopts a 2.5D-TSV silicon substrate as an intermediate layer to connect a CPU bare chip to the LTCC substrate (5).

3. The micro computing system based on TSV and LTCC secondary integration of claim 1, wherein the NAND micro module (2) is a stacked integration of 8 NAND FLASH chips and 1 IPD passive termination chip, NAND FLASH bare chips are embedded in TSV silicon substrate and reconfigured by RDL rewiring and vertical interconnection between layers is done by micro bumps.

4. The TSV primary integration and LTCC secondary integration based computing microsystem as claimed in claim 1, wherein the FPGA micromodule (4) has a flip-chip FPGA bare chip; the FPGA micro module (4) adopts a 2.5D-TSV silicon substrate as an intermediary layer to connect the FPGA bare chip to the LTCC substrate (5).

5. The computing microsystem based on primary TSV integration and secondary LTCC integration of claim 1, wherein the second DDR3 micromodule (8) is a stacked integration of 3-layer DDR3 memory chips and 1-layer IPD passive termination chips, DDR3 bare chips are embedded in TSV silicon substrate, reconfigured by RDL rewiring, and vertically interconnected by microbumps between layers.

6. The micro computing system based on TSV primary integration and LTCC secondary integration of claim 1, wherein the first DDR micro module (6) is a stacked integration of a 5-layer DDR3 memory chip and a 1-layer IPD passive termination chip, DDR3 bare chips are embedded in a TSV silicon substrate and reconfigured by RDL rewiring, and vertical interconnection is performed between layers by micro bumps.

7. The micro computing system based on TSV primary integration and LTCC secondary integration of claim 1, wherein the SSD micro-module (3) comprises an SSD controller chip and a DDR3 bare chip, the SSD controller chip is mounted in a flip-chip manner on a 2.5D-TSV silicon substrate, and the DDR3 bare chip is reconfigured in the TSV silicon substrate and stacked through interlayer micro-bumps to form a heterogeneous micro-module.

8. The micro computing system based on the primary TSV and LTCC integration of claim 1, wherein the LTCC substrate (5) is a high expansion low temperature co-fired ceramic substrate, and copper is adopted inside the LTCC substrate (5) as a multilayer metal wiring layer.

9. The micro computing system based on TSV primary integration and LTCC secondary integration as claimed in claim 1, wherein the bottom of the LTCC substrate (5) is provided with pins (7), the pins (7) are high lead solder columns, and the pins (7) are soldered on pads on the bottom of the LTCC substrate (5).