CN117155373A - Fast transient buffer - Google Patents
Fast transient buffer Download PDFInfo
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- CN117155373A CN117155373A CN202310550306.3A CN202310550306A CN117155373A CN 117155373 A CN117155373 A CN 117155373A CN 202310550306 A CN202310550306 A CN 202310550306A CN 117155373 A CN117155373 A CN 117155373A
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- fast transient
- transient buffer
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- 239000000872 buffer Substances 0.000 title claims abstract description 59
- 230000001052 transient effect Effects 0.000 title claims abstract description 52
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01825—Coupling arrangements, impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Logic Circuits (AREA)
Abstract
The present invention provides a fast transient buffer comprising: the flip voltage follower is coupled between the input end and the output end of the fast transient buffer; and a first MOS transistor coupled to the flipped voltage follower and the output terminal of the fast transient buffer, wherein the first MOS transistor adjusts the output voltage in a direction opposite to a direction in which the flipped voltage follower adjusts the output voltage of the output terminal.
Description
Technical Field
The present invention relates to fast transient (fast-transient) buffers.
Background
With the development of semiconductor technology, low power consumption and low voltage circuit designs require fast transient buffers.
Disclosure of Invention
The present invention provides a fast transient buffer.
In one embodiment, the present invention provides a fast transient buffer comprising: the flip voltage follower is coupled between the input end and the output end of the fast transient buffer; and a first MOS transistor coupled to the flipped voltage follower and the output terminal of the fast transient buffer, wherein the first MOS transistor adjusts the output voltage in a direction opposite to a direction in which the flipped voltage follower adjusts the output voltage of the output terminal.
Drawings
Fig. 1 depicts a fast transient buffer 100 according to an exemplary embodiment of the invention.
Fig. 2 depicts details of the fast transient buffer 100 according to an exemplary embodiment of the invention.
Fig. 3 depicts details of a fast transient buffer 100 according to another exemplary embodiment of the invention.
Fig. 4 depicts another buffer according to an exemplary embodiment of the present invention.
Fig. 5 depicts another buffer according to an exemplary embodiment of the present invention.
Detailed Description
The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined with reference to the appended claims.
Fig. 1 depicts a fast transient buffer 100 according to an exemplary embodiment of the invention.
The fast transient buffer 100 includes a flipped voltage follower (flipped voltage follower) 102, a MOS transistor (e.g., a metal oxide semiconductor field effect transistor, also simply referred to as a MOSFET) 104, and a bias circuit 106. The flip-flop voltage follower 102 is coupled between the input terminal Vin and the output terminal Vo of the fast transient buffer 100. The MOS transistor 104 is coupled to the flip-flop 102 and the output Vo of the fast transient buffer 100. The bias circuit 106 is coupled to the flipped voltage follower 102 and is also capable of biasing the MOS transistor 104 through the flipped voltage follower 102.
According to such a design, the MOS transistor 104 regulates the output voltage (also labeled Vo) of the fast transient buffer 100 in a direction opposite to the direction in which the output voltage (Vo) caused by the flipped voltage follower 102 regulates.
In an exemplary embodiment in which the flip voltage follower 102 is provided to quickly adjust the overshoot (overshoot) of the output voltage Vo, the MOS transistor 104 is provided to quickly adjust the undershoot (undershoot) of the output voltage Vo.
In the exemplary embodiment in which the flip voltage follower 102 is provided to rapidly adjust the undershoot of the output voltage Vo, the MOS transistor 104 is provided to rapidly adjust the overshoot of the output voltage Vo.
Compared with the problem that the traditional flip-flop voltage follower can only quickly adjust overshoot (or undershoot), the MOS transistor 104 is a simple device which can effectively adjust the output voltage Vo, so that the defect of the traditional flip-flop voltage follower is overcome. The MOS transistor 104 is a low power and fast solution.
Fig. 2 depicts details of the fast transient buffer 100 according to an exemplary embodiment of the invention.
The MOS transistor 104 is implemented by a first MOS transistor Ml (which is PMOS). The first MOS transistor M1 comprises a gate terminal coupled to the flip-flop 102, a drain terminal coupled to the output terminal Vo of the fast transient buffer, and a source terminal coupled to the power terminal.
The flip-flop voltage follower 102 includes a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. The second MOS transistor M2 and the third MOS transistor M3 are two NMOS. The second MOS transistor M2 includes a gate terminal coupled to the input terminal Vin of the fast transient buffer 102, a source terminal coupled to the output terminal Vo of the fast transient buffer 102, and a drain terminal coupled to the gate terminal of the first MOS transistor M1. The third MOS transistor M3 includes a drain terminal coupled to the source terminal of the second MOS transistor M2, a gate terminal coupled to the drain terminal of the second MOS transistor M2 through the fourth MOS transistor M4, and a source terminal coupled to the ground terminal. The fourth MOS transistor M4 is a PMOS, and comprises a source terminal coupled to the drain terminal of the second MOS transistor M2 and a drain terminal coupled to the gate terminal of the third MOS transistor M3. The flipped voltage follower 102 further includes a first current source I1 and a second current source I2. The first current source I1 is coupled to a connection terminal between the gate terminal of the first MOS transistor M1, the drain terminal of the second MOS transistor M2 and the source terminal of the fourth MOS transistor M4 for providing a first current (also denoted as I1). The second current source I2 is coupled to a connection terminal between the drain terminal of the fourth MOS transistor M4 and the gate terminal of the third MOS transistor M3, and is configured to sink (sink) a second current (also denoted as I2). In addition to the bias currents I1 and I2, a bias circuit 106 is also proposed in this example.
The regulation of the output voltage Vo by the preferably biased (well biased) circuits 102 and 104 is fast.
In response to the overshoot of the output voltage Vo, the overshoot is reflected to the gate terminal of the third MOS transistor M3 through the second MOS transistor M2 and the fourth MOS transistor M4. The third MOS transistor (NMOS) M3 is thus turned on to sink current from the output terminal Vo. Thus, the overshoot of the output voltage Vo is quickly regulated.
In response to the undershoot of the output voltage Vo, the undershoot is reflected to the gate terminal of the first MOS transistor Ml through the second MOS transistor M2. The first MOS transistor (PMOS) M1 is thus turned on to supply current to the output Vo. Therefore, the undershoot of the output voltage Vo is quickly adjusted.
Further details of the biasing circuit 106 are presented in fig. 2 and discussed herein. The bias circuit 106 is coupled to the gate terminal of the fourth MOS transistor M4, and may further bias the first MOS transistor M1 through the fourth MOS transistor M4. As shown, the bias circuit 106 includes a fifth MOS transistor M5 (i.e., diode-connected PMOS) and a sixth MOS transistor M6 (i.e., another diode-connected PMOS). The fifth MOS transistor M5 and the sixth MOS transistor M6 are connected in series between the power supply terminal and the gate terminal of the fourth MOS transistor M4. The bias circuit 106 further includes a third current source I3 coupled to a connection between the drain terminal of the sixth transistor M6 and the gate terminal of the fourth transistor M4 to sink a third current (also denoted as I3).
The bias circuit 106 biases the gate terminal of the fourth MOS transistor M4 at a bias voltage (VDD-2 Vgs), where VDD is the power supply voltage of the power supply terminal and Vgs is the voltage difference between the gate terminal and the source terminal (i.e., the gate-source voltage difference) of the fifth/sixth MOS transistor M5/M6. After the bias voltage (VDD-2 Vgs) is increased by the gate-source voltage difference Vgs of the fourth MOS transistor M4, another bias voltage (VDD-Vgs) is generated and supplied to the gate terminal of the first MOS transistor M1. Therefore, the first MOS transistor M1 is preferably biased. The quiescent current flowing through the first MOS transistor M1 may be the same as the third current I3. The third current I3 may be set to be much lower than the first current I1. The proposed buffer provided with the first MOS transistor M1 is a low power design.
Fig. 3 depicts details of a fast transient buffer 100 according to another exemplary embodiment of the invention.
As shown in fig. 3, the first MOS transistor M1 is an NMOS, and the source terminal of the first MOS transistor M1 is connected to the ground terminal. The second MOS transistor M2 and the third MOS transistor M3 are two PMOS. The source terminal of the third MOS transistor M3 is coupled to the power supply terminal. The fourth MOS transistor M4 is an NMOS. The first current source I1 is coupled to a connection terminal among the gate terminal of the first MOS transistor M1, the drain terminal of the second MOS transistor M2, and the source terminal of the fourth MOS transistor M4, and is configured to sink the first current I1. The second current source I2 is coupled to a connection terminal between the drain terminal of the fourth MOS transistor M4 and the gate terminal of the third MOS transistor M3 for providing a second current I2. The circuits 102 and 104, which are preferably biased (due to currents I1, I2 and bias circuit 106), quickly adjust the output voltage Vo.
In response to the undershoot of the output voltage Vo, the undershoot is reflected to the gate terminal of the third MOS transistor M3 through the second MOS transistor M2 and the fourth MOS transistor M4. The third MOS transistor (PMOS) M3 is thus turned on to supply current to the output Vo. Therefore, the undershoot of the output voltage Vo is quickly adjusted.
In response to the overshoot of the output voltage Vo, the overshoot is punched out to the gate terminal of the first MOS transistor Ml by the second MOS transistor M2. Accordingly, the first MOS transistor (NMOS) M1 is turned on to sink current from the output terminal Vo. Thus, the overshoot of the output voltage Vo is quickly regulated.
In fig. 3, the fifth MOS transistor M5 is a diode-connected NMOS, and the sixth MOS transistor M6 is another diode-connected NMOS. The fifth MOS transistor M5 and the sixth MOS transistor M6 are connected in series between the gate terminal and the ground terminal of the fourth MOS transistor M4. The third current source I3 is coupled to a connection terminal between the drain terminal of the sixth transistor M6 and the gate terminal of the fourth transistor M4 to provide a third current I3. In this way, the bias circuit 106 biases the gate terminal of the fourth MOS transistor M4 to the bias voltage 2Vgs. After lowering the bias voltage 2Vgs by the gate-source voltage difference Vgs of the fourth MOS transistor M4, another bias voltage Vgs is generated and supplied to the gate terminal of the first MOS transistor M1. Therefore, the first MOS transistor M1 is preferably biased. The quiescent current flowing through the first MOS transistor M1 may be the same as the third current I3. The third current I3 may be set to be much lower than the first current I1. The proposed buffer equipped with the first MOS transistor M1 is a low power consumption design.
To implement a Low-dropout regulator (LDO), some modifications are made to the circuits shown in FIGS. 2 and 3.
Fig. 4 depicts another buffer, which is a low drop out regulator (LDO) modified from the circuit shown in fig. 3, according to an exemplary embodiment of the present invention.
The LDO shown in fig. 4 further comprises a seventh MOS transistor M7. The seventh MOS transistor M7 is a diode-connected NMOS connected between the input terminal Vin and the gate terminal of the second MOS transistor M2 so as to boost the input voltage Vin with the gate-source polar difference Vgs of the seventh transistor M7. Therefore, the gate voltage level of the second MOS transistor M2 is (vin+vgs). When the gate voltage level (vin+vgs) of the second MOS transistor M2 is lowered by the gate-source difference Vgs of the second MOS transistor M2, the output voltage Vo follows Vin.
Fig. 4 also shows a fourth current source I4 coupled to the drain terminal of the seventh MOS transistor M7 to provide a fourth current (also denoted I4). In the exemplary embodiment, the fourth current I4 is equal to the first current I1, and the seventh MOS transistor M7 is the same size as the second MOS transistor M2.
Fig. 5 depicts another buffer, which is a low drop out regulator (LDO) modified from the circuit shown in fig. 4, according to an exemplary embodiment of the present invention.
Referring to the LDO shown in fig. 5, the seventh MOS transistor M7 is a diode-connected PMOS connected between the input terminal Vin and the gate terminal of the second MOS transistor M2 so as to reduce the input voltage Vin using the gate-source difference Vgs of M7. Therefore, the gate voltage level of the second MOS transistor M2 is (Vin-Vgs). When the gate voltage (Vin-Vgs) of the second MOS transistor M2 is increased by the gate-source difference Vgs of the second MOS transistor M2, the output voltage Vo follows Vin.
In fig. 5, a fourth current source I4 is coupled to the drain terminal of the seventh MOS transistor M7 to sink the fourth current I4. In the exemplary embodiment, the fourth current I4 is equal to the first current I1, and the seventh MOS transistor M7 is the same size as the second MOS transistor M2.
Any buffer or voltage regulator comprising a flipped voltage follower provided with the proposed first MOS transistor Ml should be considered within the scope of the invention.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to one of ordinary skill in the art). The scope of the appended claims is therefore to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (19)
1. A fast transient buffer comprising:
the flip voltage follower is coupled between the input end and the output end of the fast transient buffer; and
a first MOS transistor coupled to the flipped voltage follower and the output terminal of the fast transient buffer,
wherein the first MOS transistor adjusts the output voltage in a direction opposite to the direction in which the flipped voltage follower adjusts the output voltage of the output terminal.
2. The fast transient buffer of claim 1, wherein:
the gate terminal of the first MOS transistor is coupled to the flip-flop voltage follower, and the drain terminal is coupled to the output terminal of the fast transient buffer.
3. The fast transient buffer of claim 2, wherein:
the flip voltage follower comprises a second MOS transistor and a third MOS transistor;
the gate terminal of the second MOS transistor is coupled to the input terminal of the fast transient buffer, the source terminal of the second MOS transistor is coupled to the output terminal of the fast transient buffer, and the drain terminal of the second MOS transistor is coupled to the gate terminal of the first MOS transistor; and
the drain terminal of the third MOS transistor is coupled to the source terminal of the second MOS transistor, and the gate terminal of the third MOS transistor is coupled to the drain terminal of the second MOS transistor.
4. The fast transient buffer of claim 3, further comprising:
and the bias circuit is coupled with the flip voltage follower.
5. The fast transient buffer of claim 4, wherein:
the flip-flop voltage follower further comprises a fourth MOS transistor coupled between the drain terminal of the second MOS transistor and the gate terminal of the third MOS transistor;
the source terminal of the fourth MOS transistor is coupled to the drain terminal of the second MOS transistor, and the drain terminal of the fourth MOS transistor is coupled to the gate terminal of the third MOS transistor; and
the bias circuit is coupled to the gate terminal of the fourth MOS transistor to further bias the first MOS transistor through the fourth MOS transistor.
6. The fast transient buffer of claim 5, wherein:
the first MOS transistor is PMOS, and the source electrode end of the first MOS transistor is coupled with the power supply end;
the second MOS transistor is NMOS;
the third MOS transistor is NMOS, and the source electrode end of the third MOS transistor is coupled with the grounding end; and
the fourth MOS transistor is PMOS.
7. The fast transient buffer of claim 6, wherein the flipped voltage follower further comprises:
a first current source coupled to a connection terminal between the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor and the source terminal of the fourth MOS transistor to provide a first current; and
and a second current source coupled to a connection terminal between the drain terminal of the fourth MOS transistor and the gate terminal of the third MOS transistor for absorbing a second current.
8. The fast transient buffer of claim 7, wherein the biasing circuit comprises:
a fifth MOS transistor, which is a PMOS of a diode connection method; and
a sixth MOS transistor, which is a diode-connected PMOS;
wherein the fifth MOS transistor and the sixth MOS transistor are coupled in series between the gate terminal and the power terminal of the fourth MOS transistor.
9. The fast transient buffer of claim 8, wherein the biasing circuit further comprises:
and a third current source coupled to a connection terminal between the drain terminal of the sixth MOS transistor and the gate terminal of the fourth MOS transistor for absorbing a third current.
10. The fast transient buffer of claim 7, further comprising:
a seventh MOS transistor, which is a diode-connected NMOS, is coupled between the input terminal of the fast transient buffer and the gate terminal of the second MOS transistor, for boosting an input voltage received by the fast transient buffer through the input terminal.
11. The fast transient buffer of claim 7, further comprising:
and a fourth current source coupled to the drain terminal of the seventh MOS transistor for providing a fourth current.
12. The fast transient buffer of claim 11, wherein:
the fourth current is equal to the first current; and
the seventh MOS transistor is the same size as the second MOS transistor.
13. The fast transient buffer of claim 5, wherein:
the first MOS transistor is NMOS, and the source electrode end of the first MOS transistor is coupled with the grounding end;
the second MOS transistor is PMOS;
the third MOS transistor is a PMOS, and the source terminal of the third MOS transistor is coupled to the power supply terminal; and
the fourth MOS transistor is an NMOS.
14. The fast transient buffer of claim 13, wherein the flipped voltage follower further comprises:
a first current source coupled to the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor, and the source terminal of the fourth MOS transistor to sink a first current; and
and a second current source coupled to a connection terminal between the drain terminal of the fourth MOS transistor and the gate terminal of the third MOS transistor for providing a second current.
15. The fast transient buffer of claim 14, wherein the biasing circuit comprises:
a fifth MOS transistor, which is a diode-connected NMOS; and
a sixth MOS transistor, which is a diode-connected NMOS;
wherein the fifth MOS transistor and the sixth MOS transistor are coupled in series between the gate terminal of the fourth MOS transistor and the ground terminal.
16. The fast transient buffer of claim 15, wherein the biasing circuit further comprises:
and a third current source coupled to a connection terminal between the drain terminal of the sixth MOS transistor and the gate terminal of the fourth MOS transistor for providing a third current.
17. The fast transient buffer of claim 15, further comprising:
the seventh MOS transistor is a diode-connected PMOS, and is coupled between the input terminal of the fast transient buffer and the gate terminal of the second MOS transistor, for reducing the input voltage received by the fast transient buffer through the input terminal.
18. The fast transient buffer of claim 14, further comprising:
and a fourth current source coupled to the drain terminal of the seventh MOS transistor for sinking a fourth current.
19. The fast transient buffer of claim 18, wherein:
the fourth current is equal to the first current; and
the seventh MOS transistor is the same size as the second MOS transistor.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/347,599 | 2022-06-01 | ||
| US18/299,852 | 2023-04-13 | ||
| US18/299,852 US20230396246A1 (en) | 2022-06-01 | 2023-04-13 | Fast-transient buffer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117155373A true CN117155373A (en) | 2023-12-01 |
Family
ID=88884936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310550306.3A Pending CN117155373A (en) | 2022-06-01 | 2023-05-16 | Fast transient buffer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117155373A (en) |
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2023
- 2023-05-16 CN CN202310550306.3A patent/CN117155373A/en active Pending
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