CN117153692A - Rhenium disulfide-tellurium heterojunction field effect transistor and preparation method and application thereof - Google Patents

Rhenium disulfide-tellurium heterojunction field effect transistor and preparation method and application thereof Download PDF

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CN117153692A
CN117153692A CN202311066353.7A CN202311066353A CN117153692A CN 117153692 A CN117153692 A CN 117153692A CN 202311066353 A CN202311066353 A CN 202311066353A CN 117153692 A CN117153692 A CN 117153692A
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electrode
type
tellurium
substrate
nano
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孙一鸣
朱玲玉
陈薪好
黎飞
赵一铭
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South China Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

Abstract

The invention relates to a rhenium disulfide-tellurium heterojunction field effect transistor and a preparation method and application thereof, wherein the field effect transistor comprises a p-type tellurium nanosheet arranged on a substrate, an n-type rhenium disulfide thin layer which is arranged in a cross manner with the p-type tellurium nanosheet, a first electrode and a second electrode which are respectively arranged at two ends of the p-type tellurium nanosheet, and a third electrode and a fourth electrode which are respectively arranged at two ends of the n-type rhenium disulfide thin layer; when the first electrode and the second electrode are respectively used as a source electrode and a drain electrode, the third electrode or the fourth electrode is used as a grid electrode; when the third electrode and the fourth electrode are respectively used as a source electrode and a drain electrode, the first electrode or the second electrode is used as a grid electrode, and the p-type JFET and the n-type JFET are integrated in the same structure, so that the switching of the p-type JFET and the n-type JFET is realized through the selection of different electrodes, the low power consumption and the high mobility are realized, and the cost is saved; the method is simple and easy to operate, does not involve preparation of a dielectric layer, avoids complex dielectric engineering, and improves device performance.

Description

Rhenium disulfide-tellurium heterojunction field effect transistor and preparation method and application thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a rhenium disulfide-tellurium heterojunction field effect transistor, and a preparation method and application thereof.
Background
Two-dimensional transition metal chalcogenides (TMDs) have received much attention for their excellent physicochemical properties, and their suitable band gap and excellent photoelectric properties have become a research hotspot at home and abroad. ReS (ReS) 2 As one of TMDs, it has more outstanding structural and performance characteristics than other materials, due to its direct bandgap electronic structure and high mobility, which do not vary with the number of layers, reS 2 Has important significance for preparing field effect transistors with excellent performance. The chalcogen element two-dimensional tellurium nanosheets realize high carrier mobility and strong in-plane anisotropy due to the unique helical chain structure, and become potential materials for preparing high-performance field effect transistors.
The technological characteristics of JFET are that it is simple and has no complex dielectric engineering requirement, so that it can be used in extensive application. In addition, the JFET can achieve an ideal subthreshold swing of 60mV/dec as compared with the MOSFET, and has better performance in the low-power consumption field than the MOSFET. The work of the JFET made of the two-dimensional semiconductor material is reported at present, but the structure of the JFET is single. The p-type field effect transistor and the n-type field effect transistor are integrated in the same structure to form the multifunctional device, and the integration can promote more comprehensive and efficient device design and has huge potential application in the exploration and development of the field of low-power-consumption multifunctional devices.
Disclosure of Invention
Aiming at the defect that the prior multifunctional junction field effect transistor device integrating a p-type field effect transistor and an n-type field effect transistor into the same structure is rare, the primary aim of the invention is to provide a rhenium disulfide-tellurium heterojunction field effect transistor and a preparation method thereof, and the device is formed by a p-type Te nano-sheet and an n-type ReS 2 Thin layers partially overlapping to form a hetero-layerA mass junction, a first electrode and a second electrode are respectively arranged at two ends of the Te nano-sheet, and a ReS is arranged at the two ends of the Te nano-sheet 2 A third electrode and a fourth electrode are respectively arranged at two ends of the thin layer, and when the first electrode and the second electrode are respectively used as a source electrode and a drain electrode, the third electrode or the fourth electrode is used as a grid electrode; when the third electrode and the fourth electrode are used as a source electrode and a drain electrode respectively, the first electrode or the second electrode is used as a grid electrode. The arrangement of the structure integrates the p-type JFET and the n-type JFET in the same structure, so that the p-type JFET and the n-type JFET are switched through the selection of different electrodes, and the preparation of the multifunctional device with low power consumption, high mobility and cost saving is realized.
The invention provides a preparation method of a rhenium disulfide-tellurium heterojunction field effect transistor, which comprises the following steps:
after cleaning, siO was removed by mechanical stripping 2 ReS on Si substrate 2 A layer;
obtaining a solution containing p-type Te nano-sheets with the thickness ranging from 50nm to 100nm by a hydrothermal synthesis method, and spin-coating the solution on SiO 2 On a Si substrate, then soaking the substrate in an organic solvent for a certain time to perform oxidation thinning to obtain a thinned p-type Te nano-sheet;
selecting target ReS by dry transfer process 2 Transferring a thin layer onto the Te nano-plate to enable ReS 2 The thin layer is partially overlapped with Te nano-sheet to form ReS 2 A Te heterojunction;
preparing a first electrode and a second electrode at two ends of Te nano-plate, and preparing a first electrode and a second electrode at two ends of Te nano-plate in ReS 2 And preparing a third electrode and a fourth electrode at two ends of the thin layer to obtain the field effect transistor based on rhenium disulfide/tellurium junction.
Further, in the hydrothermal synthesis method, sodium tellurite and polyvinylpyrrolidone are mixed in a ratio of 52.4:1 is dissolved in a certain volume of deionized water, 4ml of ammonia water and 2ml of hydrazine hydrate are dripped into the deionized water to be mixed to obtain a simple substance tellurium precursor, the precursor is placed in a reaction kettle liner, and the reaction is carried out for 24 hours at the temperature of 180 ℃ to obtain a solution containing Te nano-sheets with the thickness of 50-100 nm.
Further, in the spin coating, the spin coating is performed at a low speed of 500rpm for 15s, followed by the spin coating at a high speed of 2000rpm for 15s.
In the thinning method, the organic solvent is absolute ethyl alcohol or acetone, the soaking time is 2-10 days, and the thickness of the thinned Te nano-sheet is 1-20 nm.
Further, in the dry transfer process, a target ReS is selected 2 Thin layer, reS on transfer platform with PVA/PDMS 2 Transferring the thin layer onto Te nano-sheet, heating at 90-110 deg.C, separating PDMS and PVA, then separating PVA and SiO by using dimethyl sulfoxide at 60 deg.C 2 A Si substrate, and cleaning the substrate with deionized water, and drying with nitrogen gun to obtain ReS 2 A Te heterojunction.
The invention provides a rhenium disulfide-tellurium heterojunction field effect transistor, which comprises a substrate, a p-type tellurium nanosheet arranged on the substrate, an n-type rhenium disulfide thin layer arranged on the p-type tellurium nanosheet in a crossing way with the p-type tellurium nanosheet, a first electrode and a second electrode respectively arranged at two ends of the p-type tellurium nanosheet, and a third electrode and a fourth electrode respectively arranged at two ends of the n-type rhenium disulfide thin layer;
when the first electrode and the second electrode are respectively used as a source electrode and a drain electrode, the third electrode or the fourth electrode is used as a grid electrode; or when the third electrode and the fourth electrode are respectively used as a source electrode and a drain electrode, the first electrode or the second electrode is used as a grid electrode.
Further, the thickness of the p-type tellurium nanosheets is 1-20 nm, and the thickness of the n-type rhenium disulfide thin layers is 10-50 nm.
Further, the substrate is SiO 2 and/Si substrate, wherein the substrate is used as a bottom gate.
Further, au electrodes are selected for the first electrode, the second electrode, the third electrode and the fourth electrode.
The invention also provides application of the rhenium disulfide-tellurium heterojunction field effect transistor in an integrated circuit.
The invention has at least the following beneficial effects:
the invention is synthesized by hydrothermal methodPreparing a solution containing p-type tellurium nano-sheets, spreading the p-type tellurium nano-sheets on a substrate through spin coating, obtaining the p-type tellurium nano-sheets on the substrate after intercalation thinning, and then carrying out mechanical stripping and dry transfer process to obtain n-type ReS 2 Transferring the thin layer onto the p-type tellurium nano-sheet to enable the ReS to be 2 The thin layer is partially overlapped with Te nano-sheet to form ReS 2 Te heterojunction, first and second electrodes prepared at two ends of Te nano-sheet, reS 2 And preparing a third electrode and a fourth electrode at two ends of the thin layer to obtain the junction field effect transistor. The preparation method is simple and easy to operate, does not involve the preparation of a dielectric layer, avoids complex dielectric engineering, and has the advantages of ReS without dangling bonds on the surface 2 Van der Waals heterojunction formed by preparing and constructing thin layer and Te nano-sheet two-dimensional material avoids hysteresis caused by interface defect when a polycrystalline medium layer is contacted with the surface of a semiconductor, so that the stability of a circuit is improved when the junction field effect transistor is applied to an integrated circuit.
The junction field effect transistor of the invention combines a p-type tellurium nano-sheet and an n-type ReS 2 The thin layers are partially overlapped to form a heterojunction by a first electrode and a second electrode or a ReS at two ends of the tellurium nano-sheet 2 The third electrode and the fourth electrode at the two ends of the thin layer are selected, the p-type JFET or the n-type JFET is constructed, the multifunctional junction field effect transistor with the p-type JFET and the n-type JFET integrated in the same structure is realized, the bottom gate regulation is introduced, the channel carrier concentration is regulated by applying fixed bottom gate voltage while the junction gate regulation, the device is promoted to realize more effective on and off, the effect of reducing subthreshold swing is achieved, the junction field effect transistor has low subthreshold swing, high on-off ratio and carrier mobility, low power consumption is realized, and the cost is saved.
Drawings
Fig. 1 is a perspective view showing the overall structure of a junction field effect transistor according to an embodiment of the present invention.
FIG. 2 shows output curves of current as a function of source-drain voltage for different top gate voltages when electrode 1 and electrode 2 are used as source and drain and electrode 3 or electrode 4 is used as gate, according to an embodiment.
FIG. 3 shows the transfer curves of the current with the gate voltage under different bias voltages when the electrode 1 and the electrode 2 are used as the source and the drain and the electrode 3 or the electrode 4 is used as the gate, in one embodiment.
Fig. 4 shows output curves of current with source-drain voltage at different top gate voltages when electrode 3 and electrode 4 are used as source and drain and electrode 1 or 2 is used as gate, according to an embodiment.
FIG. 5 shows a graph of the current transfer with top gate voltage for different bias voltages when electrode 3 and electrode 4 are used as source and drain and electrode 1 or 2 is used as gate, in one embodiment.
FIG. 6 shows an embodiment in which electrodes 3 and 4 are used as source and drain electrodes, a silicon substrate is used as bottom gate, and a bottom gate voltage V BG At=20v, the current varies with the top gate voltage at different biases.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Based on the embodiments of the present invention, other embodiments that may be obtained by those of ordinary skill in the art without making any inventive effort are within the scope of the present invention. The experimental methods described in the following examples are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, are commercially available from the public sources.
Spatially relative terms, such as "under", "below", "lower", "above", "upper" and the like, may be used herein to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures.
In addition, the use of terms such as "first," "second," etc. to describe various elements, layers, regions, sections, etc. are not intended to be limiting. The use of "having," "containing," "including," etc. are open ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly dictates otherwise.
FIG. 1 shows a second embodiment of the present inventionSchematic three-dimensional structure of sulfide-tellurium heterojunction field effect transistor, which is arranged on substrate, and SiO is selected as substrate 2 a/Si substrate or other suitable insulating substrate. In a preferred embodiment, the substrate is a silicon substrate 8, and the surface of the silicon substrate 8 is provided with SiO 2 Insulating layer 7, siO 2 The thickness of the insulating layer was 300nm.
The p-type Te nano-plate 5 is arranged on the SiO 2 The thickness of the p-type Te nano-plate 5 is 1nm to 50nm on the surface of the insulating layer 7. Weighing 0.5g of polyvinylpyrrolidone, 0.1g of sodium tellurite, 4ml of ammonia water and 2ml of hydrazine hydrate, sequentially dissolving the mixture in 33ml of deionized water, mixing to obtain a simple substance tellurium precursor solution, pouring the precursor solution into a lining of a hydrothermal reaction kettle, placing the lining in a drying box, setting the temperature of the hydrothermal reaction to be 180 ℃, and reacting for 24 hours to obtain a solution containing simple substance Te nano-sheets with the thickness ranging from 50nm to 100nm after the reaction.
1ml of the solution containing the simple substance Te nano-plate is taken and dripped on a silicon wafer (namely SiO 2 The Si substrate), the silicon wafer is rotated at a low speed of 500rpm for 15s, and then the silicon wafer is rotated at a high speed of 2000rpm for 15s, so that the Te nano-sheets are uniformly distributed on the silicon wafer. And (3) soaking the silicon wafer uniformly distributed with the Te nano-sheets in an organic solvent for 2-10 days. The organic solvent is absolute ethyl alcohol or acetone, in the preferred embodiment, the organic solvent is absolute ethyl alcohol, the soaking time is preferably one week, the absolute ethyl alcohol dissolves the polyvinylpyrrolidone coated with Te, and the Te is thinned by intercalation, so that the Te nano-sheet with the thickness of 1-50 nm after thinning is obtained.
ReS 2 A thin layer 6 is arranged on the Te nano-sheet 5, and ReS 2 The thickness of the thin layer 6 is 10nm to 50nm. Firstly sequentially ultrasonically cleaning SiO with acetone, isopropanol and deionized water 2 The Si substrates were each sonicated for 5min, then blow-dried with a nitrogen gun, and clean, smooth surfaces were observed under an optical microscope. Next, the SiO after cleaning was taped out by mechanical stripping 2 Adhesion of ReS on Si substrate 2 A layer. Then soaking the substrate in acetone to remove residual gum, washing with deionized water, drying, and selecting thickness under an optical microscopeReS of 10-50 nm 2 A thin layer. ReS is carried out through a three-dimensional micro-region transfer platform 2 Transferring thin layer onto PVA/PDMS, transferring onto Te nano-sheet, separating PDMS and PVA at 100deg.C, soaking substrate into dimethyl sulfoxide, and heating at 60deg.C to separate PVA and SiO 2 A Si substrate. Then the substrate is cleaned by deionized water, and the ReS is prepared after the substrate is dried by a nitrogen gun 2 A Te heterojunction.
Subsequently, spin-coating a photoresist with a thickness of about 4 μm on the silicon wafer, heating for 4 minutes and drying under the condition of no light at 100 ℃; respectively in ReS by a maskless ultraviolet lithography system 2 Photoetching exposure electrode patterns at two ends of the thin layer and the Te nano-plate; then adopting an electron beam vacuum coating system to evaporate a 50nm Au layer, obtaining an electrode 1 and an electrode 2 at two ends of the Te nano-sheet, and obtaining a gold-silver alloy film on the surface of the Te nano-sheet 2 The electrodes 3 and 4 are obtained at both ends of the thin layer, resulting in a ReS-based 2 A Te junction field effect transistor.
The junction field effect transistor prepared by the method uses Te nano-sheets as conducting channels, uses electrode 1 and electrode 2 as source electrode and drain electrode respectively to receive Te electric signals, and uses ReS 2 And forming a depletion region in the overlapping region with Te, and regulating and controlling the width of the depletion region by using the electrode 3 or the electrode 4 as a grid electrode to change the channel switching state to form the p-type JFET. At this time, the output curve of the current with the source-drain voltage is shown in fig. 2, and the transfer curve of the current with the gate voltage is shown in fig. 3.
With ReS 2 Thin layer as conductive channel and electrode 3 and electrode 4 as source and drain respectively to receive ReS 2 Te and ReS 2 The overlapping area forms a depletion region, the electrode 1 or the electrode 2 is used as a grid electrode, the width of the depletion region is regulated and controlled, and the channel switching state is changed to form the n-type JFET. At this time, the output curve of the current with the source-drain voltage is shown in fig. 4, and the transfer curve of the current with the gate voltage is shown in fig. 5.
Electrode 3 and electrode 4 are respectively used as source electrode and drain electrode, electrode 1 or electrode 2 is used as gate electrode, silicon substrate is used as bottom gate, and bottom gate voltage V BG When=20v, noThe transfer curve of current with top gate voltage under the same bias is shown in fig. 6. Compared with fig. 5, after the positive bias is applied to the bottom gate silicon substrate, the saturation current is increased by nearly one time under the same bias, so that the maximum value of transconductance under the same bias is also increased, and the corresponding subthreshold swing is reduced.
The rhenium disulfide-tellurium heterojunction field effect transistor integrates a p-type JFET and an n-type JFET, and realizes a multifunctional device with low power consumption, high mobility and cost saving. In specific application, the electrode 1 and the electrode 2 can be selected as a source electrode and a drain electrode respectively, and the electrode 3 or the electrode 4 can be selected as a grid electrode according to the requirements of different device types, in this case, negative bias can be selectively applied on the bottom gate silicon substrate so as to further change the concentration of carriers through the bottom gate and improve the threshold voltage of the p-type JFET. Or electrode 3 and electrode 4 are selected as source and drain, respectively, and electrode 1 or electrode 2 is selected as gate, in which case a positive bias voltage may be selectively applied to the bottom gate silicon substrate to further change the concentration of carriers through the bottom gate, raising the threshold voltage of the n-type JFET.
The above examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principle of the present invention should be made in the equivalent manner, and the embodiments are included in the protection scope of the present invention.

Claims (10)

1. The preparation method of the rhenium disulfide-tellurium heterojunction field effect transistor is characterized by comprising the following steps of:
after cleaning, siO was removed by mechanical stripping 2 ReS on Si substrate 2 A layer;
obtaining a solution containing p-type Te nano-sheets with the thickness ranging from 50nm to 100nm by a hydrothermal synthesis method, and spin-coating the solution on SiO 2 On a Si substrate, then soaking the substrate in an organic solvent for a certain time to perform oxidation thinning to obtain a thinned p-type Te nano-sheet;
selecting target ReS by dry transfer process 2 Transferring a thin layer onto the Te nano-plate to enable ReS 2 The thin layer is partially overlapped with Te nano-sheet to form ReS 2 A Te heterojunction;
preparing a first electrode and a second electrode at two ends of Te nano-plate, and preparing a first electrode and a second electrode at two ends of Te nano-plate in ReS 2 And preparing a third electrode and a fourth electrode at two ends of the thin layer to obtain the field effect transistor based on rhenium disulfide/tellurium junction.
2. The preparation method according to claim 1, wherein in the hydrothermal synthesis method, sodium tellurite and polyvinylpyrrolidone are mixed in a ratio of 52.4:1 is dissolved in a certain volume of deionized water, 4ml of ammonia water and 2ml of hydrazine hydrate are dripped into the deionized water to be mixed to obtain a simple substance tellurium precursor, the precursor is placed in a reaction kettle liner, and the reaction is carried out for 24 hours at the temperature of 180 ℃ to obtain a solution containing Te nano-sheets with the thickness of 50-100 nm.
3. The production method according to claim 1 or 2, wherein in the spin coating, spin coating is performed at a low speed of 500rpm for 15s, followed by spin coating at a high speed of 2000rpm for 15s.
4. The preparation method of claim 3, wherein in the thinning method, absolute ethyl alcohol or acetone is selected as the organic solvent, the soaking time is 2-10 days, and the thickness of the thinned Te nano-plate is 1-20 nm.
5. The method according to claim 3, wherein the target ReS is selected in the dry transfer process 2 Thin layer, reS on transfer platform with PVA/PDMS 2 Transferring the thin layer onto Te nano-sheet, heating at 90-110 deg.C, separating PDMS and PVA, then separating PVA and SiO by using dimethyl sulfoxide at 60 deg.C 2 A Si substrate, and cleaning the substrate with deionized water, and drying with nitrogen gun to obtain ReS 2 A Te heterojunction.
6. The rhenium disulfide-tellurium heterojunction field effect transistor is characterized by comprising a substrate, a p-type tellurium nanosheet arranged on the substrate, an n-type rhenium disulfide thin layer arranged on the p-type tellurium nanosheet in a crossing manner with the p-type tellurium nanosheet, a first electrode and a second electrode respectively arranged at two ends of the p-type tellurium nanosheet, and a third electrode and a fourth electrode respectively arranged at two ends of the n-type rhenium disulfide thin layer;
when the first electrode and the second electrode are respectively used as a source electrode and a drain electrode, the third electrode or the fourth electrode is used as a grid electrode; or when the third electrode and the fourth electrode are respectively used as a source electrode and a drain electrode, the first electrode or the second electrode is used as a grid electrode.
7. The junction field effect transistor according to claim 6, wherein the thickness of the p-type tellurium nanoplatelets is 1 to 20nm and the thickness of the n-type rhenium disulfide thin layer is 10 to 50nm.
8. The junction field effect transistor according to claim 6 or 7, wherein the substrate is made of SiO 2 and/Si substrate, wherein the substrate is used as a bottom gate.
9. The junction field effect transistor according to claim 6 or 7, wherein Au electrode is selected for each of the first electrode, the second electrode, the third electrode and the fourth electrode.
10. Use of a rhenium-tellurium disulfide heterojunction field effect transistor as claimed in any of claims 6 to 9 in an integrated circuit.
CN202311066353.7A 2023-08-23 2023-08-23 Rhenium disulfide-tellurium heterojunction field effect transistor and preparation method and application thereof Pending CN117153692A (en)

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