CN117111679A - Low-dropout linear voltage regulator - Google Patents

Abstract

Embodiments of the present disclosure provide a low dropout linear regulator. The low dropout linear regulator includes: error amplifier, output power tube, voltage division feedback circuit, and voltage buffer. The non-inverting input end of the error amplifier is coupled to the first end of the voltage division feedback circuit, the inverting input end of the error amplifier is coupled to the reference signal end, and the output end of the error amplifier is coupled to the voltage buffer through the first node. The voltage buffer is coupled to the control electrode of the output power tube through the second node. The first pole of the output power tube is coupled with the first voltage end, and the second pole of the output power tube is coupled with the second end of the voltage division feedback circuit and the output end of the low dropout linear voltage regulator. The voltage buffer is configured to control a voltage difference between the first node and the second node.

Description

Low-dropout linear voltage regulator

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to low dropout linear regulators.

Background

Low dropout linear regulators (Low Dropout Regulator, LDOs for short) are widely used in integrated circuits for providing a supply voltage required inside the integrated circuits. Fig. 1 shows an exemplary circuit diagram of an LDO 100. As shown in fig. 1, LDO 100 may include an error amplifier, an output power transistor Mpout, a first resistor R1, and a second resistor R2. The output out of the LDO 100 may be coupled to a load (shown in fig. 1 as a load current source Iout). For an ultra-low quiescent current LDO with a quiescent current of the order of hundred nanoamperes, the sum of the resistances of the first resistor R1 and the second resistor R2 is typically greater than 100mΩ, and the aspect ratio of the output power transistor Mpout of the LDO is typically large to provide the output current and lower output impedance of the LDO. The source drain current Ids of the output power transistor Mpout is approximately equal to the load current Iout (i.e., the current of the load current source Iout). When the load current iout=0a, the source drain current Ids of the output power transistor Mpout is usually only tens nanoamperes, and the source gate voltage Vsg of the output power transistor Mpout is small and approaches 0V. In the example of fig. 1, the output power transistor Mpout is a PMOS transistor. When the PMOS transistor is at the fast process corner or at a high temperature, the source gate voltage Vsg of the output power transistor Mpout becomes smaller, and the gate (node pgate) voltage of the output power transistor Mpout may be approximately equal to the source voltage Vcc of the output power transistor Mpout. In an ultralow quiescent current LDO, the ultralow quiescent current makes the LDO very suitable for low power consumption occasions. The ultra-low quiescent current LDO includes a low voltage ultra-low quiescent current LDO. The low-voltage ultralow quiescent current LDO can accept lower working voltage and is applied to occasions with lower input voltage.

Disclosure of Invention

Embodiments described herein provide a low dropout linear regulator.

According to a first aspect of the present disclosure, a low dropout linear regulator is provided. The low dropout linear regulator includes: error amplifier, output power tube, voltage division feedback circuit, and voltage buffer. The non-inverting input terminal of the error amplifier is coupled to the first terminal of the voltage division feedback circuit. The inverting input terminal of the error amplifier is coupled to the reference signal terminal. The output end of the error amplifier is coupled with the voltage buffer through the first node. The voltage buffer is coupled to the control electrode of the output power tube through the second node. The first pole of the output power tube is coupled with the first voltage end. The second pole of the output power tube is coupled with the second end of the voltage division feedback circuit and the output end of the low dropout linear voltage regulator. The voltage buffer is configured to control a voltage difference between the first node and the second node. Wherein, the voltage buffer includes: a first current source circuit, a first control circuit, a current mirror circuit, a load current mirror circuit, and a second control circuit. The first current source circuit is configured to supply a first constant current from an output terminal of the first current source circuit to the first control circuit. The first control circuit is configured to control a voltage difference between the first node and the second node, and to provide a first distributed current to the current mirror circuit via the third node according to a voltage of the first node, a voltage of the second node, and a first constant current. The current mirror circuit is configured to generate a first mirror current of the first distributed current and to provide the first mirror current to the second control circuit. The load current mirror circuit is configured to generate a second mirror current from a load current of the low dropout linear regulator and to provide the second mirror current to the second control circuit via the fourth node. The second control circuit is configured to control a voltage difference between the first node and the second node according to the first mirror current and the second mirror current.

In some embodiments of the present disclosure, the first control circuit includes: a first transistor and a second transistor. The control electrode of the first transistor is coupled to the first node. The first electrode of the first transistor is coupled to the output terminal of the first current source circuit. The second pole of the first transistor is coupled to the third node. The control electrode of the second transistor is coupled to the second electrode and the second node of the second transistor. The first electrode of the second transistor is coupled to the output terminal of the first current source circuit.

In some embodiments of the present disclosure, the aspect ratio of the first transistor is N times the aspect ratio of the second transistor. N is greater than 1.

In some embodiments of the present disclosure, a current mirror circuit includes: a third transistor, a fourth transistor, and a voltage control circuit. The control electrode of the third transistor is coupled with the second electrode of the third transistor and the control electrode of the fourth transistor. The first electrode of the third transistor is coupled to the first voltage terminal. The second pole of the third transistor is coupled to the third node. The first electrode of the fourth transistor is coupled to the first voltage terminal. The second pole of the fourth transistor is coupled to the first end of the voltage control circuit. The second terminal of the voltage control circuit is coupled to the second node. The voltage control circuit is configured to control a voltage of the second pole of the fourth transistor such that the fourth transistor operates in the linear region and to pass a source-drain current of the fourth transistor to the second node.

In some embodiments of the present disclosure, the fourth transistor has a width to length ratio K times the width to length ratio of the third transistor. K is greater than 1.

In some embodiments of the present disclosure, the voltage control circuit includes: a fifth transistor, a sixth transistor, and a second current source circuit. The control electrode of the fifth transistor is coupled to the output end of the second current source circuit. The first pole of the fifth transistor is coupled to the second pole of the fourth transistor. The second pole of the fifth transistor is coupled to the second node. The control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the output terminal of the second current source circuit. The first electrode of the sixth transistor is coupled to the first voltage terminal. The second current source circuit is configured to supply a second constant current from an output terminal of the second current source circuit to the sixth transistor.

In some embodiments of the present disclosure, the fifth transistor has a width to length ratio J times that of the sixth transistor. J is greater than 1.

In some embodiments of the present disclosure, a load current mirror circuit includes: and a seventh transistor. The control electrode of the seventh transistor is coupled to the control electrode of the output power transistor. The first pole of the seventh transistor is coupled to the first voltage terminal. The second pole of the seventh transistor is coupled to the fourth node.

In some embodiments of the present disclosure, the aspect ratio of the output power transistor is m times the aspect ratio of the seventh transistor. m is greater than 1.

In some embodiments of the present disclosure, the second control circuit includes: eighth, ninth, tenth, and eleventh transistors. The control electrode of the eighth transistor is coupled to the first node. The first pole of the eighth transistor is coupled to the fourth node. The second pole of the eighth transistor is coupled to the control pole of the ninth transistor and the second pole. The control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor. The first pole of the ninth transistor is coupled to the second voltage terminal. The first pole of the tenth transistor is coupled to the second voltage terminal. The second pole of the tenth transistor is coupled to the control pole of the eleventh transistor and the second pole. The control electrode of the eleventh transistor is coupled to the control electrode of the output power transistor. The first pole of the eleventh transistor is coupled to the fourth node.

In some embodiments of the present disclosure, the low dropout linear regulator is a low voltage ultra low quiescent current LDO.

According to a second aspect of the present disclosure, a low dropout linear regulator is provided. The low dropout linear regulator includes: an error amplifier, an output power transistor, a first resistor, a second resistor, a first current source circuit, a second current source circuit, and first to eleventh transistors. Wherein the non-inverting input of the error amplifier is coupled to the second end of the first resistor and the first end of the second resistor. The inverting input terminal of the error amplifier is coupled to the reference signal terminal. The output end of the error amplifier is coupled with the control electrode of the first transistor and the control electrode of the eighth transistor. The control electrode of the output power transistor is coupled to the control electrode of the second transistor, the control electrode of the seventh transistor and the control electrode of the eleventh transistor. The first pole of the output power tube is coupled with the first voltage end. The second pole of the output power tube is coupled with the first end of the first resistor and the output end of the low-dropout linear regulator. The second end of the second resistor is coupled to the second voltage end. The first electrode of the first transistor is coupled to the output terminal of the first current source circuit. The second pole of the first transistor is coupled to the control pole of the third transistor and the second pole. The control electrode and the second electrode of the second transistor are coupled to the second electrode of the fifth transistor. The first electrode of the second transistor is coupled to the output terminal of the first current source circuit. The first current source circuit is configured to supply a first constant current from an output terminal of the first current source circuit to the first transistor and the second transistor. The first electrode of the third transistor is coupled to the first voltage terminal. The control electrode of the fourth transistor is coupled to the control electrode of the third transistor. The first electrode of the fourth transistor is coupled to the first voltage terminal. The second pole of the fourth transistor is coupled to the first pole of the fifth transistor. The control electrode of the fifth transistor is coupled to the control electrode of the sixth transistor and the second electrode. The second pole of the sixth transistor is coupled to the output terminal of the second current source circuit. The first electrode of the sixth transistor is coupled to the first voltage terminal. The second current source circuit is configured to supply a second constant current from an output terminal of the second current source circuit to the sixth transistor. The first pole of the seventh transistor is coupled to the first voltage terminal. The second pole of the seventh transistor is coupled to the first pole of the eighth transistor and the first pole of the eleventh transistor. The second pole of the eighth transistor is coupled to the control pole of the ninth transistor and the second pole. The control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor. The first pole of the ninth transistor is coupled to the second voltage terminal. The first pole of the tenth transistor is coupled to the second voltage terminal. The second pole of the tenth transistor is coupled to the control pole of the eleventh transistor and the second pole.

In some embodiments of the present disclosure, the aspect ratio of the first transistor is N times the aspect ratio of the second transistor. N is greater than 1.

In some embodiments of the present disclosure, the fourth transistor has a width to length ratio K times the width to length ratio of the third transistor. K is greater than 1.

In some embodiments of the present disclosure, the fifth transistor has a width to length ratio J times that of the sixth transistor. J is greater than 1.

In some embodiments of the present disclosure, the aspect ratio of the output power transistor is m times the aspect ratio of the seventh transistor. m is greater than 1.

In some embodiments of the present disclosure, the low dropout linear regulator is a low voltage ultra low quiescent current LDO.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary circuit diagram of an LDO;

FIG. 2 is an exemplary circuit diagram of an error amplifier;

FIG. 3 is an exemplary circuit diagram of a low dropout linear regulator;

FIG. 4 is a schematic block diagram of a low dropout linear regulator according to an embodiment of the present disclosure; and

Fig. 5 is an exemplary circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure.

In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical and the on-current directions between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the transistor is referred to as the control pole and the remaining two terminals of the transistor are referred to as the first pole and the second pole, respectively. The transistors employed in the embodiments of the present disclosure are primarily MOS (Metal Oxide Semiconductor ) transistors. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 2 shows an exemplary circuit diagram of the error amplifier in the example of fig. 1. In the example of fig. 2, the transistors mp+, mp-, mp1, mp2, mp1c, mp2c are PMOS transistors. The transistors Mn1c, mn2c, mn1, mn2 are NMOS transistors. The control electrode of the transistor mp+ is coupled to the feedback signal terminal V _FB . Transistor Mp-Is coupled to the reference signal terminal V _REF . The current source It supplies a constant current It to the transistor mp+ and the transistor Mp-. The drains of the transistor Mp2c and the transistor Mn2c are coupled to the node pgate. The source of the transistor Mp1 and the source of the transistor Mp2 are coupled to the voltage terminal Vcc.

Referring to fig. 1, when the load current iout=0a, the gate (node pgate) voltage (which may be expressed in context as Vpgate) of the output power transistor Mpout may be approximately equal to the source voltage Vcc of the output power transistor Mpout. When the voltage difference between Vpgate and Vcc is small, both the transistor Mp2 and the transistor Mp2c inside the error amplifier in fig. 2 will enter the linear region, which will reduce the output impedance of the error amplifier, thereby affecting the dc open loop gain Av of the error amplifier. The open loop gain Av may be reduced to a few tenths or hundredths of the original. Because (V) _FB –V _REF ) X av=vpgate, V when the open loop gain Av decreases _FB –V _REF And the difference of (c) becomes large, so that the output voltage accuracy of the LDO becomes poor.

In view of the above, fig. 3 proposes a low dropout linear regulator 300. As shown in fig. 3, a voltage buffer is interposed between the output terminal eaout of the error amplifier and the gate (node pgate) of the output power transistor Mp out in order to maintain the voltage Veaout of the output terminal eaout of the error amplifier at a proper voltage difference from Vpgate when the voltage difference from Vpgate to Vcc is small so as to prevent the transistor Mp2 and the transistor Mp2c inside the error amplifier in fig. 2 from entering the linear region.

The voltage buffer in fig. 3 consists of a current source Is and a transistor Mpb. The current source Is supplies a current Is to the transistor Mpb. The transistor Mpb may be implemented as a PMOS transistor. The voltage Veaout of the output eaout of the error amplifier=vpgate-vsg_mpb. Where vsg_mpb represents the source gate voltage of transistor Mpb. To avoid Veaout being close to Vpgate, vsg_Mpb can be increased. The magnitude of vsg_mpb depends on the current Is and the aspect ratio of transistor Mpb. To increase vsg_mpb, the current Is may be increased or the aspect ratio of the transistor Mpb may be decreased. For ultra-low quiescent current LDOs, the current Is cannot be very large. Reducing the aspect ratio of the transistor Mpb will result in a high impedance at node pgate, which will degrade the stability of the LDO with the pole formed by the high capacitance at node pgate. Thus, in the example of FIG. 3, veaout is not avoided from being close to Vpgate by increasing Vsg_Mpb.

Further, the minimum operation voltage Vcc of fig. 3 is larger than vsg_mpout (the source gate voltage of the transistor Mpout in fig. 3) +vsg_mpb (the source gate voltage of the transistor Mpb in fig. 3) +vdsat_mn2 (the overdrive voltage of the transistor Mn2 in fig. 2) +vdsat_mn2c (the overdrive voltage of the transistor Mn2c in fig. 2). Assuming that the source gate voltages of the transistors Mpout and Mpb need to reach 0.8V and the overdrive voltages of the transistors Mn2 and Mn2c need to reach 0.2V, vcc needs to be above 2.0V, so the circuit structure of fig. 3 is not suitable for the low-voltage LDO.

Embodiments of the present disclosure provide a low dropout linear regulator. Fig. 4 shows a schematic block diagram of a low dropout linear regulator 400 according to an embodiment of the present disclosure. As shown in fig. 4, the low dropout linear regulator 400 may include: an error amplifier, an output power transistor Mpout, a voltage division feedback circuit 460, and a voltage buffer. The non-inverting input of the error amplifier may be coupled to a first end of the voltage division feedback circuit 460. The inverting input of the error amplifier may be coupled to the reference signal terminal V _REF . The output terminal of the error amplifier may be coupled to the voltage buffer via a first node eaout. The voltage buffer may be coupled to the control electrode of the output power transistor Mpout via the second node pgate. The first pole of the output power tube Mpout may be coupled to the first voltage terminal V1. The second pole of the output power tube Mpout may be coupled to the second end of the voltage division feedback circuit and the output end out of the low dropout linear regulator. The voltage division feedback circuit 460 may include: a first resistor R1 and a second resistor R2. A first terminal of the first resistor R1 (as a second terminal of the voltage division feedback circuit 460) is coupled to the output terminal out of the low dropout linear regulator. The second end of the first resistor R1 (as the first end of the voltage division feedback circuit 460) is coupled to the first end of the second resistor R2. The second terminal of the second resistor R2 is coupled to the second voltage terminal V2. The output out of the low dropout linear regulator may be coupled to an external load, shown in fig. 4 as a load current source Iout. The voltage buffer may be configured to control a voltage difference between the first node eaout and the second node pgate (the voltage difference discussed herein refers to a voltage The absolute value of the difference) such that the voltage difference between the voltage Veaout of the first node eaout and the voltage V1 of the first pole of the output power transistor Mpout is greater than the first voltage threshold. The first voltage threshold is set to avoid that the transistor Mp2 and the transistor Mp2c inside the error amplifier in fig. 2 enter the linear region.

In the example of fig. 4, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The output power transistor Mpout is implemented with PMOS transistors.

The voltage buffer may include: a first current source circuit 410, a first control circuit 420, a current mirror circuit 430, a load current mirror circuit 440, and a second control circuit 450.

The first current source circuit 410 may be coupled to the first control circuit 420. The first current source circuit 410 may be configured to provide a first constant current I1 from an output of the first current source circuit 410 to the first control circuit 420.

The first control circuit 420 may be coupled to the first current source circuit 410, the current mirror circuit 430, the load current mirror circuit 440, the second control circuit 450, the first node eaout and the second node pgate. The first control circuit 420 may be configured to: when the voltage difference (|vpgate-v1|) between the voltage Vpgate of the second node pgate and the voltage V1 of the first pole of the output power transistor Mpout is smaller than the second voltage threshold, the voltage difference between the first node eaout and the second node pgate is controlled to be larger than the third voltage threshold so that the voltage difference between Veaout and V1 is larger than the first voltage threshold. This prevents the transistor Mp2 and the transistor Mp2c inside the error amplifier in fig. 2 from entering the linear region. The first control circuit 420 may also be configured to: the first distribution current I11 is provided to the current mirror circuit 430 via the third node N3 according to the voltage of the first node eaout, the voltage of the second node pgate, and the first constant current I1.

The current mirror circuit 430 may be coupled to the first control circuit 420, the load current mirror circuit 440, the second control circuit 450, the second node pgate, and the first voltage terminal V1. The current mirror circuit 430 may be configured to generate a first mirror current I11 'of the first distributed current I11 and provide the first mirror current I11' to the second control circuit 450.

The load current mirror circuit 440 may be coupled to the first control circuit 420, the current mirror circuit 430, the second control circuit 450, the second node pgate and the first voltage terminal V1. The load current mirror circuit 440 may be configured to generate a second mirror current Iout 'from the load current Iout of the low dropout linear regulator 400 and to provide the second mirror current Iout' to the second control circuit 450 via the fourth node N4.

The second control circuit 450 may be coupled to the first control circuit 420, the current mirror circuit 430, the load current mirror circuit 440, the first node eaout, and the second node pgate. The second control circuit 450 may be configured to: when the voltage difference between the voltage Vpgate of the second node pgate and the voltage V1 of the first pole of the output power transistor Mpout is greater than the second voltage threshold, the voltage difference between the first node eaout and the second node pgate is controlled to be greater than the fourth voltage threshold and less than the third voltage threshold according to the first mirror current I11 'and the second mirror current Iout', so that the voltage difference between Veaout and V1 is greater than the first voltage threshold. This prevents the transistor Mp2 and the transistor Mp2c inside the error amplifier in fig. 2 from entering the linear region.

Fig. 5 shows an exemplary circuit diagram of a low dropout linear regulator 500 according to an embodiment of the present disclosure. As shown in fig. 5, the first current source circuit 510 may include a current source I1. The first control circuit 520 may include: a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to the first node eaout. A first pole of the first transistor M1 is coupled to the output terminal of the first current source circuit 510. The second pole of the first transistor M1 is coupled to the third node N3. The control electrode of the second transistor M2 is coupled to the second electrode of the second transistor M2 and the second node pgate. A first pole of the second transistor M2 is coupled to the output terminal of the first current source circuit 510. The first current source circuit 510 may provide a first constant current I1 to the first transistor M1 and the second transistor M2.

The current mirror circuit 530 may include: a third transistor M3, a fourth transistor M4, and a voltage control circuit 531. The control electrode of the third transistor M3 is coupled to the second electrode of the third transistor M3 and the control electrode of the fourth transistor M4. The first pole of the third transistor M3 is coupled to the first voltage terminal V1. The second pole of the third transistor M3 is coupled to the third node N3. The first pole of the fourth transistor M4 is coupled to the first voltage terminal V1. The second pole of the fourth transistor M4 is coupled to the first terminal of the voltage control circuit 531. The second terminal of the voltage control circuit 531 is coupled to the second node pgate. The voltage control circuit 531 may be configured to: the voltage of the second pole of the fourth transistor M4 is controlled such that the fourth transistor M4 operates in the linear region and the source-drain current of the fourth transistor M4 is transferred to the second node pgate.

The voltage control circuit 531 may include: a fifth transistor M5, a sixth transistor M6, and a second current source circuit. The control electrode of the fifth transistor M5 is coupled to the output terminal of the second current source circuit. The first pole of the fifth transistor M5 (as the first terminal of the voltage control circuit 531) is coupled to the second pole of the fourth transistor M4. A second terminal of the fifth transistor M5 (as a second terminal of the voltage control circuit 531) is coupled to the second node pgate. The control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6 and the output terminal of the second current source circuit. The first pole of the sixth transistor M6 is coupled to the first voltage terminal V1. The second current source circuit may include a current source I2 and be configured to: the second constant current I2 is supplied from the output terminal of the second current source circuit to the sixth transistor M6.

The load current mirror circuit 540 may include: and a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the control electrode of the output power transistor Mpout. The first pole of the seventh transistor M7 is coupled to the first voltage terminal V1. The second pole of the seventh transistor M7 is coupled to the fourth node N4. Thus, the seventh transistor M7 and the output power transistor Mpout form a current mirror.

The second control circuit 550 may include: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the eighth transistor M8 is coupled to the first node eaout. The first pole of the eighth transistor M8 is coupled to the fourth node N4. The second pole of the eighth transistor M8 is coupled to the control pole of the ninth transistor M9 and the second pole. The control electrode of the ninth transistor M9 is coupled to the control electrode of the tenth transistor M10. The first pole of the ninth transistor M9 is coupled to the second voltage terminal V2. The first pole of the tenth transistor M10 is coupled to the second voltage terminal V2. The second pole of the tenth transistor M10 is coupled to the control pole of the eleventh transistor M11 and the second pole. The control electrode of the eleventh transistor M11 is coupled to the control electrode of the output power transistor Mpout. The first pole of the eleventh transistor M11 is coupled to the fourth node N4. In the second control circuit 550, the ninth transistor M9 may constitute a current mirror with the tenth transistor M10.

In the example of fig. 5, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, and the output power transistor Mpout are PMOS transistors. The first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M10 are NMOS transistors. The width-to-length ratio of the first transistor M1 is N times the width-to-length ratio of the second transistor M2. The width-to-length ratio of the fourth transistor M4 is K times the width-to-length ratio of the third transistor M3. The width-to-length ratio of the fifth transistor M5 is J times the width-to-length ratio of the sixth transistor M6. The width-to-length ratio of the output power transistor Mpout is M times the width-to-length ratio of the seventh transistor M7. Wherein N, K, J and m are both greater than 1.

In the case where the load current iout=0a or less than the first current threshold value, vpgate is approximately equal to V1 (as described above, at this time (|vpgate-v1|) less than the second voltage threshold value). Here, the first current threshold is a current value such that the gate voltage of the output power transistor Mpout is approximately equal to the source voltage. At this time, the eleventh transistor M11 is turned off, and the second transistor M2 is turned on. The substrates of the first and second transistors M1 and M2 may be grounded to increase the turn-on voltages Vthn of the first and second transistors M1 and M2 using the body effect. Even if the first transistor M1 and the second transistor M2 are at a fast process angle or at a high temperature, the gate-source voltages Vgs of the first transistor M1 and the second transistor M2 are relatively large, so that the first transistor M1 and the second transistor M2 operate in a saturation region.

As described above, the width-to-length ratio of the fifth transistor M5 is J times the width-to-length ratio of the sixth transistor M6, i.e., the width-to-length ratio of the sixth transistor M6 is smaller than the width-to-length ratio of the fifth transistor M5, so the source gate voltage vsg_m5 of the fifth transistor M5 is smaller than the source gate voltage vsg_m6 of the sixth transistor M6. The drain voltage vd_m4=v1- (vsg_m6-vsg_m5) of the fourth transistor M4 may be made smaller than a predetermined value by controlling the ratio J of the width-to-length ratio of the fifth transistor M5 to the width-to-length ratio of the sixth transistor M6 such that the value of vd_m4 may be controlled such that the fourth transistor M4 operates in the linear region. Here, the predetermined value is a source-drain voltage value vsd_m4 of the fourth transistor M4 such that the fourth transistor M4 operates in the linear region. In this case, by adjusting the width-to-length ratio scaling factor K of the third transistor M3 and the fourth transistor M4, the drain-source currents in the third transistor M3 and the fourth transistor M4 can be equalized, and thus the first constant current I1 is equally distributed among the third transistor M3 and the fourth transistor M4, and thus also equally distributed among the first transistor M1 and the second transistor M2.

As described above, the width-to-length ratio of the first transistor M1 is N times that of the second transistor M2, so vgs_m2> vgs_m1, where vgs_m2 represents the gate-source voltage of the second transistor M2 and vgs_m1 represents the gate-source voltage of the first transistor M1. The output voltage of the error amplifier veaout=vpgate-vgs_m2+vgs_m1=vpgate- (vgs_m2-vgs_m1). Wherein, (vgs_m2-vgs_m1) >0V. The magnitude of (vgs_m2-vgs_m1) is related to the width-to-length ratio of the first transistor M1 and the width-to-length ratio of the second transistor M2, and the magnitude of N may be adjusted such that (vgs_m2-vgs_m1) is greater than a difference that causes Veaout to be controlled to be small enough (as described above, (|vpgate-v1|) is less than the second voltage threshold and the voltage difference between Veaout and Vpgate is greater than the third voltage threshold) such that both transistor Mp2c and transistor Mp2 in the error amplifier operate in the saturation region. This can increase the output impedance of the error amplifier, thereby increasing the dc open loop gain Av of the error amplifier, and ensuring that the output voltage accuracy of the low dropout linear regulator 500 will not deteriorate during no-load or light load. At this time, veaout and Vpgate are closer to V1, and the eighth transistor M8 and the eleventh transistor M11 are turned off, so that no current flows in the eighth transistor M8 and the eleventh transistor M11.

In the case where the load current Iout gradually increases to be larger than the first current threshold value and smaller than the second current threshold value, vpgate gradually decreases, and Veaout also decreases because veaout=vpgate- (vgs_m2-vgs_m1). Since Veaout < Vgate, the eighth transistor M8 is turned on first, and the eleventh transistor M11 remains turned off. Here, the second current threshold is a load current value such that the eighth transistor M8 is turned on and the eleventh transistor M11 is turned off.

As described above, the width-to-length ratio of the output power transistor Mpout is M times the width-to-length ratio of the seventh transistor M7. The current ids_m7=iout/M < =i1×1/x at the time of critical saturation of the seventh transistor M7 can be made by setting the value of M. Here, x is greater than 2, ids_m7 corresponds to the second mirror current Iout' in fig. 4. With the eighth transistor M8 turned on, the current ids_m7 may flow into the ninth transistor M9. Since the ninth transistor M9 and the tenth transistor M10 constitute a current mirror, the current in the tenth transistor M10 is also i1×1/x at maximum, and since the eleventh transistor M11 is turned off, the current of the tenth transistor M10 is supplied only by the fourth transistor M4. The current of the fourth transistor M4 is i1×1/2 and is distributed to the tenth transistor M10 and the second transistor M2, so that the current of the second transistor M2 is at least equal to i1×1/2-i1×1/x. And the current of the first transistor M1 is i1×1/2. Although the current of the first transistor M1 is larger than that of the second transistor M2, the aspect ratio of the first transistor M1 is N times that of the second transistor M2, and (vgs_m2-vgs_m1) >0V can be still made by setting N. Thus, veaout is still smaller than Vpgate, but the difference between Veaout and Vpgate becomes gradually smaller.

In the case where the load current Iout gradually increases to be larger than the second current threshold value, vpgate continues to decrease (as described above, at which time (|vpgate-V1|) is larger than the second voltage threshold value) until the eleventh transistor M11 is turned on. Assuming that the current ids_m7=iout/M > =i1×y of the seventh transistor M7 at this time, where y is equal to or greater than 2, the difference between Veaout and Vpgate approaches 0V (e.g., greater than the fourth voltage threshold and less than the third voltage threshold). Here, the difference between Veaout and Vpgate can be demonstrated by the negative method to be close to 0V.

It is assumed that the voltage difference between the voltage Veaout of the first node eaout and the voltage Vpgate of the second node pgate exceeds the third threshold voltage Veaout < Vpgate at this time, and the current ids_m7 of the seventh transistor M7 flows all into the eighth transistor M8 and the ninth transistor M9. Since the ninth transistor M9 and the tenth transistor M10 form a current mirror, the current in the tenth transistor M10 is also ids_m7 (ids_m7 > =i1×y), and the current in the tenth transistor M10 can only be supplied by the fourth transistor M4, but the current that the fourth transistor M4 can supply at most is i1×1/2. Thus, the tenth transistor M10 will pull Vpgate low to bring the tenth transistor M10 into the linear region, but at this time Vpgate will be much lower than Veaout, the eleventh transistor M11 will be turned on, so that ids_m7 will flow all into the eleventh transistor M11, which contradicts the assumption that ids_m7 will flow all into the eighth transistor M8 and the ninth transistor M9. Therefore, the difference between Veaout and Vpgate approaches 0V at load currents Iout greater than the second current threshold.

In this case, the current in the first transistor M1 is (N/n+1) ×i1, and the current in the second transistor M2 is (1/n+1) ×i1. If N is large, the current in the second transistor M2 is negligible, so that the current in the first transistor M1 is approximately I1, and thus the current I11 in the third transistor M3 is approximately I1. Since the third transistor M3 and the fourth transistor M4 form a current mirror, the current I11' in the fourth transistor M4 is also I1 at maximum. The current I11 '(I11' =i1) in the fourth transistor M4 is supplied to the tenth transistor M10. Since the ninth transistor M9 and the tenth transistor M10 constitute a current mirror, the total current supplied to the ninth transistor M9 and the tenth transistor M10 is halved. In the case where ids_mp7=i1×y, the total current supplied to the ninth transistor M9 and the tenth transistor M10 is the current i1×y from the seventh transistor M7 and the current I1 from the fourth transistor M4, i.e., i1× (1+y). Therefore, the current in both the ninth transistor M9 and the tenth transistor M10 is I1× (1+y)/2. Since the partial current I1 in the tenth transistor M10 is supplied by the fourth transistor M4, the current of the eleventh transistor M11 is I1× (1+y)/2-I1. The current in the eighth transistor M8 is equal to the current in the ninth transistor M9, so the currents of both the eighth transistor M8 and the eleventh transistor M11 differ by I1. By setting the width-to-length ratio of the eighth transistor M8 and the eleventh transistor M11, (Vpgate-Veaout) =i1/gm, where gm is the transconductance of the eighth transistor M8 and the eleventh transistor M11, can be made. Since I1 is small, veaout can be made approximately equal to Vpgate by setting gm. As the load current Iout increases, the current ids_m7 (i.e., iout') of the seventh transistor M7 also increases. Thus, the transconductance gm of the eighth transistor M8 and the eleventh transistor M11 also increases, thereby making Veaout closer to Vpgate. Thus if the load current Iout continues to increase, vpgate continues to decrease, veaout remains approximately equal to Vpgate. Thus, the transistor Mp2 and the transistor Mp2c in the error amplifier do not enter the linear region, and still maintain the high output impedance and the high gain of the error amplifier.

In addition, the impedance of the second node pgate is the parallel connection of the reciprocal 1/gm_m2 of the transconductance of the second transistor M2 and the reciprocal 1/gm_m11 of the transconductance of the eleventh transistor M11, and the transconductance gm_m11 of the eleventh transistor M11 varies with the load current Iout. The larger the load current Iout, the larger the transconductance gm_m11 of the eleventh transistor M11, so that the smaller the impedance of the second node pgate. This can dynamically compensate for the impedance of the second node pgate, thus improving the stability of the LDO.

Further, the minimum operating voltage V1 of the low dropout linear regulator according to the embodiment of the present disclosure only needs to be larger than vsg_mpout (the source gate voltage of the transistor Mpout in fig. 4 and 5) +vdsat_mn2 (the overdrive voltage of the transistor Mn2 in fig. 2) +vdsat_mn2c (the overdrive voltage of the transistor Mn2c in fig. 2). Assuming that the source gate voltage of the transistor Mpout needs to reach 0.8V and the overdrive voltages of the transistors Mn2 and Mn2c need to reach 0.2V, V1 only needs to reach 1.2V, so the structures of fig. 4 and 5 are suitable for LDO circuits with low voltage and ultra low quiescent current.

In summary, the low dropout linear regulator according to the embodiments of the present disclosure is suitable for a low-voltage ultralow quiescent current LDO, and can maintain high output impedance and high gain of an error amplifier, improve the accuracy of the output voltage of the LDO, and improve the stability of the LDO.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A low dropout linear regulator comprising: the device comprises an error amplifier, an output power tube, a voltage division feedback circuit and a voltage buffer;

the non-inverting input end of the error amplifier is coupled with the first end of the voltage division feedback circuit, the inverting input end of the error amplifier is coupled with the reference signal end, and the output end of the error amplifier is coupled with the voltage buffer through a first node;

the voltage buffer is coupled with the control electrode of the output power tube through a second node;

the first pole of the output power tube is coupled with a first voltage end, and the second pole of the output power tube is coupled with the second end of the voltage division feedback circuit and the output end of the low dropout linear voltage regulator;

The voltage buffer is configured to control a voltage difference between the first node and the second node;

wherein the voltage buffer includes: a first current source circuit, a first control circuit, a current mirror circuit, a load current mirror circuit, and a second control circuit;

the first current source circuit is configured to supply a first constant current from an output terminal of the first current source circuit to the first control circuit;

the first control circuit is configured to control a voltage difference between the first node and the second node, and to provide a first distribution current to the current mirror circuit via a third node in accordance with a voltage of the first node, a voltage of the second node, and the first constant current;

the current mirror circuit is configured to generate a first mirror current of the first distributed current and provide the first mirror current to the second control circuit;

the load current mirror circuit is configured to generate a second mirror current according to a load current of the low dropout linear regulator, and to provide the second mirror current to the second control circuit via a fourth node;

the second control circuit is configured to control a voltage difference between the first node and the second node in accordance with the first mirror current and the second mirror current.

2. The low dropout linear regulator according to claim 1, wherein said first control circuit comprises: a first transistor and a second transistor,

the control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the output end of the first current source circuit, and the second electrode of the first transistor is coupled to the third node;

the control electrode of the second transistor is coupled to the second electrode of the second transistor and the second node, and the first electrode of the second transistor is coupled to the output terminal of the first current source circuit.

3. The low dropout linear regulator according to claim 1, wherein the first transistor has a width to length ratio N times greater than that of the second transistor, N being greater than 1.

4. The low dropout linear regulator according to claim 1, wherein the current mirror circuit comprises: a third transistor, a fourth transistor and a voltage control circuit,

wherein a control electrode of the third transistor is coupled to a second electrode of the third transistor and a control electrode of the fourth transistor, a first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the third node;

A first pole of the fourth transistor is coupled to the first voltage terminal, and a second pole of the fourth transistor is coupled to the first terminal of the voltage control circuit;

a second terminal of the voltage control circuit is coupled to the second node, the voltage control circuit being configured to control a voltage of the second pole of the fourth transistor such that the fourth transistor operates in a linear region and to pass a source-drain current of the fourth transistor to the second node.

5. The low dropout linear regulator according to claim 4, wherein the fourth transistor has a width to length ratio K times greater than the width to length ratio of the third transistor, K being greater than 1.

6. The low dropout linear regulator according to claim 4 or 5, wherein the voltage control circuit comprises: a fifth transistor, a sixth transistor and a second current source circuit,

the control electrode of the fifth transistor is coupled to the output end of the second current source circuit, the first electrode of the fifth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is coupled to the second node;

a control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the output end of the second current source circuit, and a first electrode of the sixth transistor is coupled to the first voltage end;

The second current source circuit is configured to supply a second constant current from the output terminal of the second current source circuit to the sixth transistor.

7. The low dropout linear regulator according to claim 6, wherein the fifth transistor has a width to length ratio J times greater than that of the sixth transistor, J being greater than 1.

8. The low dropout linear regulator according to claim 1, wherein the load current mirror circuit comprises: a seventh one of the transistors is provided with a third transistor,

the control electrode of the seventh transistor is coupled to the control electrode of the output power transistor, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the fourth node.

9. The low dropout linear regulator according to claim 1, wherein the second control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,

wherein a control electrode of the eighth transistor is coupled to the first node, a first electrode of the eighth transistor is coupled to the fourth node, and a second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the ninth transistor;

the control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, and the first electrode of the ninth transistor is coupled to the second voltage terminal;

A first pole of the tenth transistor is coupled to the second voltage terminal, and a second pole of the tenth transistor is coupled to the control pole and the second pole of the eleventh transistor;

the control electrode of the eleventh transistor is coupled to the control electrode of the output power transistor, and the first electrode of the eleventh transistor is coupled to the fourth node.

10. A low dropout linear regulator comprising: an error amplifier, an output power transistor, a first resistor, a second resistor, a first current source circuit, a second current source circuit, and first to eleventh transistors;

the non-inverting input end of the error amplifier is coupled with the second end of the first resistor and the first end of the second resistor, the inverting input end of the error amplifier is coupled with the reference signal end, and the output end of the error amplifier is coupled with the control electrode of the first transistor and the control electrode of the eighth transistor;

the control electrode of the output power tube is coupled with the control electrode of the second transistor, the control electrode of the seventh transistor and the control electrode of the eleventh transistor, the first electrode of the output power tube is coupled with a first voltage end, and the second electrode of the output power tube is coupled with the first end of the first resistor and the output end of the low-dropout linear voltage regulator;

A second end of the second resistor is coupled with a second voltage end;

a first pole of the first transistor is coupled with the output end of the first current source circuit, and a second pole of the first transistor is coupled with the control pole and the second pole of the third transistor;

the control electrode and the second electrode of the second transistor are coupled with the second electrode of the fifth transistor, and the first electrode of the second transistor is coupled with the output end of the first current source circuit;

the first current source circuit is configured to supply a first constant current from an output terminal of the first current source circuit to the first transistor and the second transistor;

a first pole of the third transistor is coupled to the first voltage terminal;

a control electrode of a fourth transistor is coupled to the control electrode of the third transistor, a first electrode of the fourth transistor is coupled to the first voltage terminal, and a second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor;

a control electrode of the fifth transistor is coupled with the control electrode of the sixth transistor and the second electrode;

the second pole of the sixth transistor is coupled to the output end of the second current source circuit, and the first pole of the sixth transistor is coupled to the first voltage end;

The second current source circuit is configured to supply a second constant current from the output terminal of the second current source circuit to the sixth transistor;

a first pole of the seventh transistor is coupled to the first voltage terminal, and a second pole of the seventh transistor is coupled to the first pole of the eighth transistor and the first pole of the eleventh transistor;

a second pole of the eighth transistor is coupled to the control pole of the ninth transistor and the second pole;

the control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, and the first electrode of the ninth transistor is coupled to the second voltage terminal;

a first pole of the tenth transistor is coupled to the second voltage terminal, and a second pole of the tenth transistor is coupled to the control pole and the second pole of the eleventh transistor.