WO2021035707A1

WO2021035707A1 - Low-dropout regulator

Info

Publication number: WO2021035707A1
Application number: PCT/CN2019/103781
Authority: WO
Inventors: 熊付荣; 康超健; 马壮; 石玉楠; 宋伟
Original assignee: 华为技术有限公司
Priority date: 2019-08-30
Filing date: 2019-08-30
Publication date: 2021-03-04
Also published as: CN114144741A

Abstract

A low-dropout regulator which is applied to a power supply system, comprising: a voltage source, a ground terminal, an error amplifier circuit (320), a control circuit (350), a power tube circuit (330) and an output node. The power tube circuit (330) comprises a first power tube (331) and a second power tube (332) connected in series between the voltage source and the ground terminal. A common connection point of the first power tube (331) and the second power tube (332) is coupled to the output node. The error amplifier circuit (320) is used to provide a control voltage to gates of the first power tube (331) and the second power tube (332) on the basis of the voltage of the output node. The error amplifier circuit (320) comprises a first output terminal and a second output terminal. The first output terminal is coupled to the gate of the first power tube (331), and the second output terminal is coupled to the gate of the second power tube (332). The control circuit (350) comprises a third power tube (351) and a fourth power tube (352). A source and drain of the third power tube (351) are connected in series between the first output terminal and the second output terminal. A source and drain of the fourth power tube (352) are connected in series between the first output terminal and the second output terminal.

Description

一种低压差稳压器A low-dropout voltage stabilizer

技术领域Technical field

本申请涉及集成电路领域，尤其涉及一种低压差稳压器。This application relates to the field of integrated circuits, and in particular to a low-dropout voltage regulator.

背景技术Background technique

低压差稳压器(low dropout regulator，通常简称为LDO)，用途是提供稳定的直流电压电源。相比于一般线性直流稳压器，LDO能适用于在更小输出输入电压差的情况下工作，可以提供较低的压差，常用于电源稳压。The low dropout regulator (low dropout regulator, usually referred to as LDO) is used to provide a stable DC voltage power supply. Compared with general linear DC voltage regulators, LDOs can be applied to work with a smaller output and input voltage difference, can provide a lower voltage difference, and are often used for power supply voltage stabilization.

典型的LDO包括四个模块：基准电压源、误差放大器(error amplifier，EA)、功率管电路和反馈电路。A typical LDO includes four modules: a reference voltage source, an error amplifier (EA), a power tube circuit, and a feedback circuit.

LDO的工作原理是，反馈电路采样输出电压，与基准电压源产生的基准电压(voltage reference，VREF)作差后经误差放大电路放大来控制功率管电路的栅极电压，提供输出电流驱动负载，根据输出电压来调节负载电流使得输出电压保持稳定。The working principle of the LDO is that the feedback circuit samples the output voltage, makes a difference with the reference voltage (VREF) generated by the reference voltage source, and then is amplified by the error amplifier circuit to control the gate voltage of the power tube circuit and provide the output current to drive the load. Adjust the load current according to the output voltage so that the output voltage remains stable.

在LDO为有源终端供电过程中，当负载电流变化，可能存在向LDO输出的灌(sink)电流，sink电流会导致LDO的输出电压高于标称值，造成输出电压不稳定。When the LDO supplies power to the active terminal, when the load current changes, there may be a sink current output to the LDO. The sink current will cause the output voltage of the LDO to be higher than the nominal value, resulting in unstable output voltage.

发明内容Summary of the invention

本申请实施例提供了一种低压差稳压器，能够在sink电流时保持输出电压稳定。The embodiment of the present application provides a low dropout voltage stabilizer, which can keep the output voltage stable when the sink current occurs.

本申请实施例第一方面提供一种低压差稳压器，包括：电压源、地端、误差放大电路、控制电路、功率管电路和输出节点；其中，该功率管电路包括第一功率管和第二功率管，该第一功率管和该第二功率管串联在该电压源和该地端之间，该第一功率管和第二功率管的公共连接点被耦合至该输出节点；该误差放大电路用于基于该输出节点的电压，向该第一功率管和第二功率管的栅极提供控制电压，该误差放大电路包括第一输出端和第二输出端，该第一输出端被耦合至该第一功率管的栅极，该第二输出端被耦合至该第二功率管的栅极；该控制电路包括第三功率管和第四功率管，该第三功率管的源极和漏极串接于该第一输出端和第二输出端之间，该第四功率管的源极和漏极串接于该第一输出端和第二输出端之间。The first aspect of the embodiments of the present application provides a low dropout voltage regulator, including: a voltage source, a ground terminal, an error amplifying circuit, a control circuit, a power tube circuit, and an output node; wherein the power tube circuit includes a first power tube and A second power tube, the first power tube and the second power tube are connected in series between the voltage source and the ground, and the common connection point of the first power tube and the second power tube is coupled to the output node; the The error amplifying circuit is used to provide a control voltage to the gates of the first power tube and the second power tube based on the voltage of the output node, the error amplifying circuit includes a first output terminal and a second output terminal, the first output terminal Is coupled to the gate of the first power tube, the second output terminal is coupled to the gate of the second power tube; the control circuit includes a third power tube and a fourth power tube, the source of the third power tube The pole and the drain are connected in series between the first output terminal and the second output terminal, and the source and the drain of the fourth power tube are connected in series between the first output terminal and the second output terminal.

本申请实施例提供的低压差稳压器，使用于source电流和sink电流的情况下，通过第一功率管和第二功率管的设置，使得在source电流时，第一功率管开启而第二功率管关闭，当sink电流时，第二功率管开启而第一功率管关闭，控制电路的设置，可以避免第一功率管和第二功率管同时开启带来的功耗损失。The low dropout voltage regulator provided by the embodiment of the present application is used in the case of source current and sink current. Through the settings of the first power tube and the second power tube, the first power tube is turned on and the second power tube is turned on when the source current is selected. The power tube is turned off. When the sink current is turned on, the second power tube is turned on and the first power tube is turned off. The setting of the control circuit can avoid the power loss caused by the simultaneous turning on of the first power tube and the second power tube.

在第一方面的一种可能的实现方式中，该低压差稳压器还包括控制逻辑，用于在该第一功率管被导通时，导通该第四功率管，关闭该第三功率管；以及在该第二功率管被导通时，导通该第三功率管，关闭该第四功率管。In a possible implementation of the first aspect, the low dropout voltage regulator further includes control logic for turning on the fourth power tube and turning off the third power tube when the first power tube is turned on. Tube; and when the second power tube is turned on, the third power tube is turned on, and the fourth power tube is turned off.

该控制逻辑可通过各功率管的参数设置以及电路连接方式实现，具体此处不做限定。The control logic can be realized through the parameter setting of each power tube and the circuit connection mode, which is not specifically limited here.

在第一方面的一种可能的实现方式中，该第三功率管和第四功率管的栅极被耦合至稳定的偏置电压。In a possible implementation of the first aspect, the gates of the third power tube and the fourth power tube are coupled to a stable bias voltage.

本申请实施例提供的低压差稳压器，低压差稳压器还可以包括偏置电压电路，用于为第三功率管和第四功率管提供稳定的偏置电压。In the low dropout voltage regulator provided by the embodiment of the present application, the low dropout voltage regulator may further include a bias voltage circuit for providing a stable bias voltage for the third power tube and the fourth power tube.

在第一方面的一种可能的实现方式中，该第一功率管为PMOS管，该第二功率管为NMOS 管，该第一功率管的源极被耦合至该电压源，该第二功率管的源极被耦合至该地端，该第一功率管和第二功率管的漏极被耦合至该输出节点。In a possible implementation of the first aspect, the first power tube is a PMOS tube, the second power tube is an NMOS tube, the source of the first power tube is coupled to the voltage source, and the second power tube is The source of the tube is coupled to the ground, and the drains of the first power tube and the second power tube are coupled to the output node.

本申请实施例提供的低压差稳压器，提供了一种功率管电路的具体组成和连接方式。The low dropout voltage regulator provided in the embodiment of the present application provides a specific composition and connection mode of a power tube circuit.

在第一方面的一种可能的实现方式中，该第三功率管为PMOS管，该第四功率管为NMOS管；该误差放大电路的第一输出端耦合至该第三功率管的源极，该第四功率管的漏极，以及该第一功率管的栅极；该误差放大电路的第二输出端耦合至该第三功率管的漏极，该第四功率管的源极，以及该第二功率管的栅极。In a possible implementation of the first aspect, the third power tube is a PMOS tube, and the fourth power tube is an NMOS tube; the first output terminal of the error amplifier circuit is coupled to the source of the third power tube , The drain of the fourth power tube, and the gate of the first power tube; the second output terminal of the error amplifier circuit is coupled to the drain of the third power tube, the source of the fourth power tube, and The grid of the second power tube.

本申请实施例提供的低压差稳压器，提供了一种控制电路的具体组成和连接方式，第三功率管源极耦合至第一功率管的栅极，当第三功率管开启时，可以控制第一功率管栅极电压，第四功率管源极耦合至第二功率管的栅极，当第四功率管开启时，可以控制第二功率管栅极电压。The low dropout voltage regulator provided by the embodiment of the application provides a specific composition and connection method of the control circuit. The source of the third power tube is coupled to the gate of the first power tube. When the third power tube is turned on, The gate voltage of the first power tube is controlled, and the source of the fourth power tube is coupled to the gate of the second power tube. When the fourth power tube is turned on, the gate voltage of the second power tube can be controlled.

在第一方面的一种可能的实现方式中，该低压差稳压器还包括：偏置电压电路，用于向该第三功率管的栅极提供稳定的第一偏置电压，向该第四功率管的栅极提供稳定的第二偏置电压。In a possible implementation of the first aspect, the low dropout voltage regulator further includes: a bias voltage circuit for providing a stable first bias voltage to the gate of the third power tube, and The grid of the four power tube provides a stable second bias voltage.

在第一方面的一种可能的实现方式中，该偏置电压电路包括第一电流源、第二电流源、第五功率管和第六功率管；该第五功率管为NMOS管，该第五功率管的源极被耦合至该地端，该第五功率管的漏极被耦合至第一电流源的一端，该第五功率管的漏极和栅极短接，该第一电流源的另一端接该电压源；该第六功率管为PMOS管，该第六功率管的源极接该电压源，该第六功率管的漏极被耦合至第二电流源的一端，该第六功率管的漏极和栅极短接，该第二电流源的另一端被耦合至该地端。In a possible implementation of the first aspect, the bias voltage circuit includes a first current source, a second current source, a fifth power tube, and a sixth power tube; the fifth power tube is an NMOS tube, and the second power tube is The source of the fifth power tube is coupled to the ground, the drain of the fifth power tube is coupled to one end of the first current source, the drain and the gate of the fifth power tube are short-circuited, the first current source The other end of the sixth power tube is connected to the voltage source; the sixth power tube is a PMOS tube, the source of the sixth power tube is connected to the voltage source, and the drain of the sixth power tube is coupled to one end of the second current source. The drain and gate of the six power transistors are short-circuited, and the other end of the second current source is coupled to the ground.

在第一方面的一种可能的实现方式中，该误差放大电路包括：差分对电路，电流信号增强器和电流镜，该差分对电路用于将该误差放大电路的第一输入端与第二输入端的电压差转化为电流信号，该电流信号增强器包括至少一个电流信号增强单元，该电流信号增强单元用于放大该差分对电路输出的电流信号；该电流镜用于放大该电流信号增强器输出的电流信号并驱动该功率管电路。In a possible implementation of the first aspect, the error amplifying circuit includes a differential pair circuit, a current signal enhancer and a current mirror, and the differential pair circuit is used for the first input terminal and the second input terminal of the error amplifying circuit. The voltage difference at the input terminal is converted into a current signal, and the current signal enhancer includes at least one current signal enhancement unit, the current signal enhancement unit is used to amplify the current signal output by the differential pair circuit; the current mirror is used to amplify the current signal enhancer The output current signal drives the power tube circuit.

在第一方面的一种可能的实现方式中，该电流信号增强单元包括三个PMOS管MP1、MP2和MP3，三个NMOS管MN1、MN2和MN3；该MP1漏极耦合至该差分对电路的第一输出端，该MP1的栅极耦合至该MP2的栅极和该MP3的栅极，该MP1的栅极和漏极短接，该MP1的源极、该MP2的源极和该MP3的源极耦合至LDO输入电源，该MP2的漏极耦合至MN3的漏极，该MP3的漏极耦合至该MN2的漏极，该MN1的漏极耦合至该差分对电路的第二输出端，该MN1的栅极耦合至该MN2的栅极和该MN3的栅极，该MN1的源极、该MN2的源极和该MN3的源极被耦合至该地端。该MP3与该MN2的公共节点耦合至该电流信号增强单元的第一输出端、该MP2和该MN3的公共节点耦合至该电流信号增强单元的第二输出端。In a possible implementation of the first aspect, the current signal enhancement unit includes three PMOS transistors MP1, MP2, and MP3, and three NMOS transistors MN1, MN2, and MN3; the drain of the MP1 is coupled to the differential pair circuit The first output terminal, the gate of the MP1 is coupled to the gate of the MP2 and the gate of the MP3, the gate and the drain of the MP1 are short-circuited, the source of the MP1, the source of the MP2 and the gate of the MP3 The source is coupled to the LDO input power, the drain of MP2 is coupled to the drain of MN3, the drain of MP3 is coupled to the drain of MN2, and the drain of MN1 is coupled to the second output terminal of the differential pair circuit, The gate of the MN1 is coupled to the gate of the MN2 and the gate of the MN3, and the source of the MN1, the source of the MN2 and the source of the MN3 are coupled to the ground. The common node of the MP3 and the MN2 is coupled to the first output terminal of the current signal enhancement unit, and the common node of the MP2 and the MN3 is coupled to the second output terminal of the current signal enhancement unit.

在第一方面的一种可能的实现方式中，该电流信号增强器包括：第一电流信号增强单元和第二电流信号增强单元，该第一电流信号增强单元和第二电流信号增强单元级联。In a possible implementation of the first aspect, the current signal enhancer includes: a first current signal enhancement unit and a second current signal enhancement unit, and the first current signal enhancement unit and the second current signal enhancement unit are cascaded .

在第一方面的一种可能的实现方式中，该反馈电路包括：串联的第一电阻和第二电阻，该第一电阻和该第二电阻的公共节点耦合至该误差放大电路的第一输入端，该第二电阻接地，该第一电阻耦合至该功率管电路的输出端；该低压差稳压器还包括：补偿电容CF，该补偿电容CF耦合至该第一电阻两端。In a possible implementation of the first aspect, the feedback circuit includes: a first resistor and a second resistor connected in series, and a common node of the first resistor and the second resistor is coupled to the first input of the error amplifying circuit The second resistor is grounded, and the first resistor is coupled to the output end of the power tube circuit; the low dropout voltage regulator further includes a compensation capacitor CF, which is coupled to both ends of the first resistor.

本申请实施例的第二方面提供一种电源稳压***，其特征在于，包括如上述第一方面及各实现方式提供的该低压差稳压器，及耦合至该低压差稳压器的电压源和负载。A second aspect of the embodiments of the present application provides a power supply voltage stabilizing system, which is characterized in that it includes the low dropout voltage stabilizer as provided in the above first aspect and various implementation manners, and a voltage coupled to the low dropout voltage stabilizer. Source and load.

本申请实施例的第三方面提供一种芯片***，其特征在于，如上述第一方面及各实现方式提供的该低压差稳压器。The third aspect of the embodiments of the present application provides a chip system, which is characterized by the low dropout voltage regulator provided in the above-mentioned first aspect and various implementation manners.

本申请实施例提供的低压差稳压器，用于电源稳压，在source电流或sink电流时均可保持输出电压稳定，该低压差稳压器包括：电压源、地端、误差放大电路、控制电路、功率管电路和输出节点；其中，该功率管电路包括第一功率管和第二功率管，该第一功率管和该第二功率管串联在该电压源和该地端之间，该第一功率管和第二功率管的公共连接点被耦合至该输出节点；该误差放大电路用于基于该输出节点的电压，向该第一功率管和第二功率管的栅极提供控制电压，该误差放大电路包括第一输出端和第二输出端，该第一输出端被耦合至该第一功率管的栅极，该第二输出端被耦合至该第二功率管的栅极；该控制电路包括第三功率管和第四功率管，该第三功率管的源极和漏极串接于该第一输出端和第二输出端之间，该第四功率管的源极和漏极串接于该第一输出端和第二输出端之间。该低压差稳压器在source电流时，第一功率管开启，且第二功率管关闭；在sink电流时，第一功率管关闭，且第二功率管开启，使得输出节点的输出电压维持稳定，其中连接在误差放大器第一输出端和第二输出端之间的控制电路可以调节第一功率管和第二功率管的栅极电压，避免第一功率管和第二功率管同时开启，可以降低功耗。The low dropout voltage regulator provided by the embodiments of the present application is used for power supply stabilization, and can keep the output voltage stable at source current or sink current. The low dropout voltage regulator includes: a voltage source, a ground terminal, an error amplifier circuit, A control circuit, a power tube circuit and an output node; wherein the power tube circuit includes a first power tube and a second power tube, the first power tube and the second power tube are connected in series between the voltage source and the ground, The common connection point of the first power tube and the second power tube is coupled to the output node; the error amplifier circuit is used to provide control to the gates of the first power tube and the second power tube based on the voltage of the output node The error amplifier circuit includes a first output terminal and a second output terminal, the first output terminal is coupled to the gate of the first power tube, and the second output terminal is coupled to the gate of the second power tube The control circuit includes a third power tube and a fourth power tube, the source and drain of the third power tube are connected in series between the first output terminal and the second output terminal, and the source of the fourth power tube The and drain are connected in series between the first output terminal and the second output terminal. When the low dropout voltage regulator is in source current, the first power tube is turned on and the second power tube is turned off; when in sink current, the first power tube is turned off and the second power tube is turned on, so that the output voltage of the output node remains stable , The control circuit connected between the first output terminal and the second output terminal of the error amplifier can adjust the gate voltage of the first power tube and the second power tube to prevent the first power tube and the second power tube from turning on at the same time. Reduce power consumption.

附图说明Description of the drawings

图1为典型LDO的示意图；Figure 1 is a schematic diagram of a typical LDO;

图2为SCSI有源终端供电结构示意图；Figure 2 is a schematic diagram of the SCSI active terminal power supply structure;

图3为本申请实施例中一个LDO结构示意图；FIG. 3 is a schematic diagram of the structure of an LDO in an embodiment of the application;

图4为本申请实施例中另一个LDO结构示意图；FIG. 4 is a schematic diagram of another LDO structure in an embodiment of the application;

图5-a为本申请实施例中LDO在source电流模式下的示意图；Figure 5-a is a schematic diagram of an LDO in source current mode in an embodiment of the application;

图5-b为本申请实施例中LDO在sink电流模式下的示意图；Figure 5-b is a schematic diagram of the LDO in the sink current mode in an embodiment of the application;

图6为本申请实施例中另一个LDO结构示意图；FIG. 6 is a schematic diagram of another LDO structure in an embodiment of the application;

图7为本申请实施例中电流信号增强单元的结构示意图。FIG. 7 is a schematic structural diagram of a current signal enhancement unit in an embodiment of the application.

具体实施方式detailed description

本申请实施例提供的LDO可以提供较低的压差，常用于电源稳压，当该LDO被输入灌电流时，可以保持输出电压稳定性。The LDO provided in the embodiments of the present application can provide a lower voltage drop, and is often used for power supply stabilization. When the LDO is input and sinks current, the output voltage stability can be maintained.

下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

本申请说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", etc. in the description and claims of the application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in a sequence other than the content illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those clearly listed. Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。It should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above-mentioned terms in this application can be understood under specific circumstances.

本申请实施例中出现的专业术语介绍：Introduction of professional terms appearing in the embodiments of this application:

拉(source)电流是指从输出口主动输出电流，本实施例中具体是指LDO向负载输出电流。Source current refers to actively outputting current from the output port. In this embodiment, it specifically refers to the LDO outputting current to the load.

灌(sink)电流是指从输出被动输入电流，本实施例中具体是指负载向LDO灌入电流。Sink current refers to passively inputting current from the output, and in this embodiment specifically refers to the load sinking current into the LDO.

请参阅图1，为典型LDO的示意图。Please refer to Figure 1 for a schematic diagram of a typical LDO.

典型的LDO包括四个模块：基准电压源110、误差放大电路120、功率管电路130和反馈电路140。A typical LDO includes four modules: a reference voltage source 110, an error amplifier circuit 120, a power tube circuit 130, and a feedback circuit 140.

基准电压源110用于提供不随电流和温度变化的基准电压VREF。The reference voltage source 110 is used to provide a reference voltage VREF that does not change with current and temperature.

误差放大电路通常包括误差放大器(error amplifier，EA)。该误差放大电路120的第一输入端耦合至基准电压源110，输出端耦合至该功率管电路130的栅极，该功率管电路130的源极耦合至电压源Vin，漏极耦合至输出节点以及反馈电路140，反馈电路140另一端被耦合至误差放大电路120的第二输入端。The error amplifier circuit usually includes an error amplifier (error amplifier, EA). The first input terminal of the error amplifier circuit 120 is coupled to the reference voltage source 110, the output terminal is coupled to the gate of the power tube circuit 130, the source of the power tube circuit 130 is coupled to the voltage source Vin, and the drain is coupled to the output node And the feedback circuit 140, the other end of the feedback circuit 140 is coupled to the second input end of the error amplifying circuit 120.

该LDO的工作原理是，输出电压Vout由反馈电路140取样反馈电压Vfb，加在误差放大电路120输入端，与加在该误差放大电路另一输入端的VREF相比较，两者的差值经误差放大电路放大后控制功率管电路130的栅极电压，当电路建立平衡时，反馈电压Vfb近似等于VREF，LDO稳定输出电压Vout。The working principle of the LDO is that the output voltage Vout is sampled by the feedback circuit 140 and the feedback voltage Vfb is added to the input end of the error amplifier circuit 120, and compared with the VREF added to the other input end of the error amplifier circuit. The amplifying circuit controls the gate voltage of the power tube circuit 130 after amplification. When the circuit is balanced, the feedback voltage Vfb is approximately equal to VREF, and the LDO stabilizes the output voltage Vout.

通过合理设置各模块参数可构成一个稳定的负反馈***得到一个稳定的电压输出：A stable negative feedback system can be formed to obtain a stable voltage output by setting the parameters of each module reasonably:

输出电压Vout＝β*VREFOutput voltage Vout=β*VREF

其中，β为反馈系数，由反馈电路的电阻确定，取值大于或等于1。Among them, β is the feedback coefficient, which is determined by the resistance of the feedback circuit, and the value is greater than or equal to 1.

请参阅图2，为小型计算机***接口(small computer system interface，SCSI)有源终端供电结构示意图。Please refer to Figure 2, which is a schematic diagram of a small computer system interface (SCSI) active terminal power supply structure.

如图所示，通过LDO为SCSI有源终端提供输入电压VREG，图中总线端点B1至BN均有通过MOS管MP_1至MP_2N-1被耦合至至电压节点VOH，此时，单路就会有I1＝(VOH-VREG)/R的电流流向LDO输出，即负载向LDO灌入电流导致LDO的输出电压VOH高于标称值，无法保持VOH稳定。As shown in the figure, the input voltage VREG is provided for the SCSI active terminal through the LDO. The bus endpoints B1 to BN in the figure are all coupled to the voltage node VOH through the MOS transistors MP_1 to MP_2N-1. At this time, the single channel will have The current of I1=(VOH-VREG)/R flows to the LDO output, that is, the load sinks current into the LDO, which causes the output voltage VOH of the LDO to be higher than the nominal value, and the VOH cannot be kept stable.

由于负载可能向LDO输出端输入电流，导致LDO的输出电压高于标称值。为解决该问题，本申请实施例提供了一种低压差稳压器，下面具体进行介绍。Because the load may input current to the LDO output terminal, the output voltage of the LDO is higher than the nominal value. In order to solve this problem, an embodiment of the present application provides a low-dropout voltage stabilizer, which will be described in detail below.

请参阅图3，为本申请实施例中一个LDO结构示意图。Please refer to FIG. 3, which is a schematic diagram of an LDO structure in an embodiment of this application.

LDO包括：基准电压源310、误差放大电路320、功率管电路330、反馈电路340、电压源、地端和输出节点，该LDO还包括控制电路350和偏置电压电路360。LDO的电压源的电压为Vin，输出节点的输出电压为Vout。The LDO includes: a reference voltage source 310, an error amplifier circuit 320, a power tube circuit 330, a feedback circuit 340, a voltage source, a ground terminal, and an output node. The LDO also includes a control circuit 350 and a bias voltage circuit 360. The voltage of the voltage source of the LDO is Vin, and the output voltage of the output node is Vout.

其中，该基准电压源310用于提供VREF。Wherein, the reference voltage source 310 is used to provide VREF.

该功率管电路330包括第一功率管331和第二功率管332。该第一功率管和该第二功率管串联在该电压源和该地端之间，该第一功率管和第二功率管的公共连接点被耦合至该输出节点。The power tube circuit 330 includes a first power tube 331 and a second power tube 332. The first power tube and the second power tube are connected in series between the voltage source and the ground, and the common connection point of the first power tube and the second power tube is coupled to the output node.

可选的，该第一功率管可以为p沟道金属氧化物半导体(p-channel metal oxide semiconductor，PMOS)，也可以为N沟道金属氧化物半导体(n-channel mental oxide semiconductor，NMOS)，此处不做限定。该第二功率管可以为PMOS也可以为NMOS，此处不做限定。需要说明的是，该第一功率管的类型与第二功率管的类型没有必然联系，第一功率管的类型与第二功率管的类型可以相同，也可以不相同，此处不做限定。Optionally, the first power transistor may be a p-channel metal oxide semiconductor (PMOS) or an N-channel metal oxide semiconductor (NMOS), There is no limitation here. The second power tube may be PMOS or NMOS, which is not limited here. It should be noted that the type of the first power tube is not necessarily related to the type of the second power tube. The type of the first power tube and the type of the second power tube may be the same or different, which is not limited here.

该误差放大电路320的一个输入端耦合至基准电压源310，另一个输入端被耦合至反馈电路340，第一输入端输入VREF，第二输入端基于该输出节点的电压，通过反馈电路输入反馈电压，第一输入端与第二输入端的电压差值经误差放大电路放大后用于驱动功率管电路330。具体地，该误差放大电路320包括第一输出端和第二输出端，第一输出端被耦合至第一功率管331的栅极，第二输出端被耦合至第二功率管332的栅极。误差放大电路320通过控制功率管电路330的栅极电压，当电路建立平衡时，可以稳定LDO经输出节点输出的电压Vout。One input terminal of the error amplifier circuit 320 is coupled to the reference voltage source 310, and the other input terminal is coupled to the feedback circuit 340, the first input terminal is input VREF, the second input terminal is based on the voltage of the output node, and the feedback circuit is input through the feedback circuit. The voltage, the voltage difference between the first input terminal and the second input terminal is amplified by the error amplifier circuit and used to drive the power tube circuit 330. Specifically, the error amplifying circuit 320 includes a first output terminal and a second output terminal. The first output terminal is coupled to the gate of the first power tube 331, and the second output terminal is coupled to the gate of the second power tube 332. . The error amplifier circuit 320 controls the gate voltage of the power tube circuit 330 to stabilize the voltage Vout output by the LDO through the output node when the circuit is balanced.

该控制电路350包括第三功率管351和第四功率管352。该第三功率管351可以为PMOS也可以为NMOS，此处不做限定，该第四功率管352可以为PMOS也可以为NMOS，此处不做限定。该第三功率管的源极和漏极串接于该第一输出端和第二输出端之间，该第四功率管的源极和漏极串接于该第一输出端和第二输出端之间。该控制电路用于控制该第一功率管开启时，第二功率管关闭；第二功率管开启时，第一功率管关闭。The control circuit 350 includes a third power tube 351 and a fourth power tube 352. The third power tube 351 may be PMOS or NMOS, which is not limited here, and the fourth power tube 352 may be PMOS or NMOS, which is not limited here. The source and drain of the third power tube are connected in series between the first output terminal and the second output terminal, and the source and drain of the fourth power tube are connected in series with the first output terminal and the second output terminal. Between ends. The control circuit is used to control when the first power tube is turned on, the second power tube is turned off; when the second power tube is turned on, the first power tube is turned off.

可选的，该偏置电压电路360包括第一电流源IB1和第二电流源IB2，该IB1被耦合至第四功率管的栅极，该IB2被耦合至第三功率管的栅极。偏置电压电路用于提供预设的偏置电压，当误差放大电路320输出端电压变化时，可以控制第四功率管352的开启或关闭，以及控制第三功率管351的开启或关闭。可选的，如图3所示，IB1一端耦合至LDO的电源输入端VIN，另一端接地，IB2的一端耦合至LDO的电源输入端VIN，另一端接地。Optionally, the bias voltage circuit 360 includes a first current source IB1 and a second current source IB2, the IB1 is coupled to the gate of the fourth power tube, and the IB2 is coupled to the gate of the third power tube. The bias voltage circuit is used to provide a preset bias voltage. When the voltage at the output terminal of the error amplifier circuit 320 changes, the fourth power tube 352 can be controlled to turn on or off, and the third power tube 351 can be controlled to turn on or off. Optionally, as shown in FIG. 3, one end of IB1 is coupled to the power input terminal VIN of the LDO, the other end is grounded, one end of IB2 is coupled to the power input terminal VIN of the LDO, and the other end is grounded.

LDO工作状态中包括source电流模式和sink电流模式，其中source电流模式下，LDO source电流；sink电流模式下，LDO sink电流。The LDO working state includes source current mode and sink current mode. In the source current mode, the LDO source current; in the sink current mode, the LDO sink current.

该低压差稳压器还包括控制逻辑，用于在该第一功率管被导通时，导通该第四功率管，关闭该第三功率管；以及在该第二功率管被导通时，导通该第三功率管，关闭该第四功率管。该控制逻辑，具体可以通过第一功率管、第二功率管、第三功率管和第四功率管的具体类型、参数以及电路连接方式的配置来实现。下面具体进行介绍。The low dropout voltage regulator also includes control logic for turning on the fourth power tube and turning off the third power tube when the first power tube is turned on; and when the second power tube is turned on , The third power tube is turned on, and the fourth power tube is turned off. The control logic can be specifically implemented by the configuration of specific types, parameters, and circuit connection modes of the first power tube, the second power tube, the third power tube, and the fourth power tube. The following is a specific introduction.

source电流模式时，误差放大电路320输出电压较低，第一功率管导通，通过预设的IB1和IB2，控制第三功率管关闭，且第四功率管开启，第四功率管在工作电流范围内，随着误差放大电路输出的电压波动而电阻变化，通过IB1的合理设置，可以控制第二功率管的栅极电压，避免第二功率管导通。由此，实现了第一功率管开启，第二功率管关闭。In the source current mode, the output voltage of the error amplifier circuit 320 is low, the first power tube is turned on, and the third power tube is controlled to be turned off through the preset IB1 and IB2, and the fourth power tube is turned on, and the fourth power tube is in working current. Within the range, the resistance changes as the voltage output by the error amplifier circuit fluctuates. Through the reasonable setting of IB1, the gate voltage of the second power tube can be controlled to prevent the second power tube from being turned on. As a result, the first power tube is turned on and the second power tube is turned off.

sink电流模式下，误差放大电路320输出电压较高，第二功率管导通，通过预设的IB1和IB2，控制第三功率管开启，且第四功率管关闭，第三功率管在工作电流范围内，随着误差放大电路输出的电压波动而电阻变化，通过IB2的合理设置，可以控制第一功率管的栅极电压，避免第一功率管导通。由此，实现了第二功率管开启，第一功率管关闭。第二功率管一端接地，由此，sink电流时，可以避免LDO的电源输出端的电压升高，保持输出电压稳定。In sink current mode, the output voltage of the error amplifier circuit 320 is higher, the second power tube is turned on, and the third power tube is controlled to be turned on through the preset IB1 and IB2, and the fourth power tube is turned off, and the third power tube is in working current. Within the range, the resistance changes as the voltage output by the error amplifier circuit fluctuates. Through the reasonable setting of IB2, the gate voltage of the first power tube can be controlled to prevent the first power tube from being turned on. Thus, the second power tube is turned on and the first power tube is turned off. One end of the second power tube is grounded. Therefore, when the sink current is applied, the voltage at the power output terminal of the LDO can be prevented from rising, and the output voltage can be kept stable.

控制电路可以用于避免第一功率管和第二功率管同时导通，降低能耗。The control circuit can be used to prevent the first power tube and the second power tube from being turned on at the same time, thereby reducing energy consumption.

本申请实施例提供的LDO，可以用于电源稳压，为负载提供稳定的电压输出。该LDO功率管电路通过误差放大电路输出电压信号控制第一功率管和第二功率管的栅极，以及控制电路中第三功率管和第四功率管的开启或关闭，进而控制第一功率管和第二功率管的开启或关闭，由此，在source电流模式下，使得该第一功率管打开，第二功率管关闭；sink电流模式下，第二功率管打开，由于第二功率管接地，在sink电流时，可以保持LDO输出电压稳定，使得LDO在存在sink和source电流的情况下保持输出电压稳定。The LDO provided in the embodiment of the application can be used for power supply stabilization to provide a stable voltage output for the load. The LDO power tube circuit controls the gates of the first power tube and the second power tube through the output voltage signal of the error amplifier circuit, and controls the turning on or off of the third power tube and the fourth power tube in the control circuit, thereby controlling the first power tube And the second power tube is turned on or off, thus, in the source current mode, the first power tube is turned on and the second power tube is turned off; in the sink current mode, the second power tube is turned on, because the second power tube is grounded In the sink current, the LDO output voltage can be kept stable, so that the LDO can keep the output voltage stable in the presence of sink and source currents.

请参阅图4，本申请实施例中另一个LDO结构示意图；Please refer to FIG. 4, which is a schematic diagram of another LDO structure in an embodiment of the present application;

本申请实施例提供的LDO包括：基准电压源410、误差放大电路420、功率管电路430和反馈电路440，该LDO还包括控制电路450和偏置电压电路460。功率管电路430包括第一功率管MPP，MPP为PMOS管，和第二功率管MNN，MNN为NMOS管。The LDO provided by the embodiment of the present application includes: a reference voltage source 410, an error amplifier circuit 420, a power tube circuit 430, and a feedback circuit 440. The LDO also includes a control circuit 450 and a bias voltage circuit 460. The power tube circuit 430 includes a first power tube MPP, which is a PMOS tube, and a second power tube MNN, which is an NMOS tube.

其中，误差放大电路420包括一对跨导放大单元，包括第一跨导放大单元Gm(UP)和第二跨导放大单元Gm(DN)，误差放大电路420还包括一对1：m的电流镜，m为镜像比系数，与电流镜内部的晶体管参数的沟道尺寸有关，m大于1，例如可以为5，具体数值此处不做限定。The error amplifying circuit 420 includes a pair of transconductance amplifying units, including a first transconductance amplifying unit Gm (UP) and a second transconductance amplifying unit Gm (DN), and the error amplifying circuit 420 also includes a pair of 1:m currents. Mirror, m is the mirror ratio coefficient, which is related to the channel size of the transistor parameter inside the current mirror, m is greater than 1, for example, it can be 5, and the specific value is not limited here.

该电流镜具体包括两个PMOS管MPO1、MPO2，和两个NMOS管MNO1、MNO2，MPO1的栅极耦合至MPO2的栅极，MPO1的栅极和漏极短接，并耦合至第一跨导放大单元Gm(UP)的输出，MPO1的源极和MPO2的源极耦合至LDO输入电压源Vin，MPO2的漏端为误差放大电路的第一输出端，被耦合至控制电路的第一输入端。MNO1的栅极耦合至MNO2的栅极，MNO1的栅极和漏极短接，并耦合至第二跨导放大单元Gm(DN)的输出，MNO1的源极接地，MNO2的漏极为误差放大器的第二输出端，被耦合至控制电路的第二输入端，源极接地。The current mirror specifically includes two PMOS transistors MPO1 and MPO2, and two NMOS transistors MNO1 and MNO2. The gate of MPO1 is coupled to the gate of MPO2, and the gate and drain of MPO1 are short-circuited and coupled to the first transconductor. The output of the amplifying unit Gm(UP), the source of MPO1 and the source of MPO2 are coupled to the LDO input voltage source Vin, and the drain of MPO2 is the first output terminal of the error amplifier circuit, which is coupled to the first input terminal of the control circuit . The gate of MNO1 is coupled to the gate of MNO2. The gate and drain of MNO1 are short-circuited and coupled to the output of the second transconductance amplifying unit Gm(DN). The source of MNO1 is grounded, and the drain of MNO2 is the error amplifier. The second output terminal is coupled to the second input terminal of the control circuit, and the source is grounded.

控制电路包括第三功率管MPO3和第四功率管MNO3，MPO3为PMOS管，MNO3为NMOS管。该第三功率管的源极和漏极串接于该误差放大器的第一输出端和第二输出端之间，该第四功率管的源极和漏极串接于该误差放大器的第一输出端和第二输出端之间。具体地，误差放大电路420的第一输出端，即MPO2的漏极，耦合至MNO3的漏极、MPO3的源极，以及第一功率管MPP的栅极。误差放大电路420的第二输出端，即MNO2的漏极，耦合至MNO3的源极、MPO3的漏极以及第二功率管MNN的栅极。The control circuit includes a third power tube MPO3 and a fourth power tube MNO3. MPO3 is a PMOS tube, and MNO3 is an NMOS tube. The source and drain of the third power tube are connected in series between the first output terminal and the second output terminal of the error amplifier, and the source and drain of the fourth power tube are connected in series with the first output terminal of the error amplifier. Between the output terminal and the second output terminal. Specifically, the first output terminal of the error amplifier circuit 420, that is, the drain of MPO2, is coupled to the drain of MNO3, the source of MPO3, and the gate of the first power tube MPP. The second output terminal of the error amplifier circuit 420, that is, the drain of MNO2, is coupled to the source of MNO3, the drain of MPO3, and the gate of the second power tube MNN.

第一功率管的源极被耦合至电压源Vin，第一功率管MPP的漏极耦合至第二功率管MNN的漏极，第二功率管的源极被耦合至地端。第一功率管MPP和第二功率管MNN的公共节点为该LDO的输出节点，输出节点的输出电压Vout可用于为负载提供稳定的电压。The source of the first power tube is coupled to the voltage source Vin, the drain of the first power tube MPP is coupled to the drain of the second power tube MNN, and the source of the second power tube is coupled to the ground. The common node of the first power tube MPP and the second power tube MNN is the output node of the LDO, and the output voltage Vout of the output node can be used to provide a stable voltage for the load.

偏置电压电路包括PMOS管MPO4，NMOS管MNO4和第一偏置电流IB1和第二偏置电流IB2。其中MNO4的源极接地，栅极与漏极短接，漏极以及MNO3的栅极耦合至第一偏置电流的一端，第一偏置电流的另一端耦合至LDO的输入电压源Vin，由此，可以确定向MNO3栅极提供的第一偏置电压VBN即为MNO4的栅源电压VGS。第二偏置电流IB2的一端耦合至MPO3的栅极和耦合至MPO4的漏极，IB2的另一端接地，MPO4的源极耦合至LDO的输入电压源Vin，MPO4的栅极与漏极短接，由此，可以确定向MPO3栅极提供的第二偏置电压为VIN减MPO4的源栅电压VSG。可选的，第一偏置电流可以与多个功率管串联在VIN和地端之间，例如IB1与NMOS 管MNO4-1和NMOS管MNO4-2串联；类似地，第二偏置电流可以与多个功率管串联在VIN和地端之间，例如IB2与PMOS管MPO4-1和PMOS管MPO4-2串联，具体此处不做限定。The bias voltage circuit includes a PMOS tube MPO4, an NMOS tube MNO4, and a first bias current IB1 and a second bias current IB2. The source of MNO4 is grounded, the gate is shorted to the drain, the drain and the gate of MNO3 are coupled to one end of the first bias current, and the other end of the first bias current is coupled to the input voltage source Vin of the LDO. Therefore, it can be determined that the first bias voltage VBN provided to the gate of MNO3 is the gate source voltage VGS of MNO4. One end of the second bias current IB2 is coupled to the gate of MPO3 and the drain of MPO4, the other end of IB2 is grounded, the source of MPO4 is coupled to the input voltage source Vin of LDO, and the gate of MPO4 is shorted to the drain Therefore, it can be determined that the second bias voltage provided to the gate of MPO3 is VIN minus the source gate voltage VSG of MPO4. Optionally, the first bias current can be connected in series with multiple power transistors between VIN and ground, for example, IB1 can be connected in series with the NMOS transistor MNO4-1 and the NMOS transistor MNO4-2; similarly, the second bias current can be connected in series with the NMOS transistor MNO4-1 and the NMOS transistor MNO4-2. Multiple power tubes are connected in series between VIN and ground, for example, IB2 is connected in series with PMOS tube MPO4-1 and PMOS tube MPO4-2, which is not specifically limited here.

可选的，该LDO的反馈电路包括串联的第一电阻R1和第二电阻R2，R1和R2的公共节点耦合至该误差放大电路的同相输入端，R2的另一端接地，R1的另一端耦合至功率管的输出端及电压输出端。Optionally, the feedback circuit of the LDO includes a first resistor R1 and a second resistor R2 connected in series, the common node of R1 and R2 is coupled to the non-inverting input end of the error amplifier circuit, the other end of R2 is grounded, and the other end of R1 is coupled To the output terminal and voltage output terminal of the power tube.

可选的，该LDO还包括补偿电容CF，CF被耦合至R1两端形成前馈补偿，可以用于增强LDO环路的稳定性。Optionally, the LDO further includes a compensation capacitor CF, which is coupled to both ends of R1 to form feedforward compensation, which can be used to enhance the stability of the LDO loop.

下面分别介绍在source电流模式下和sink电流模式下，该控制电路控制功率管电路的工作机理。请参阅图5-a，为本申请实施例中LDO在source电流模式下的示意图；以及图5-b，为本申请实施例中LDO在sink电流模式下的示意图。The following respectively introduces the working mechanism of the control circuit controlling the power tube circuit in the source current mode and the sink current mode. Please refer to FIG. 5-a, which is a schematic diagram of the LDO in the source current mode in an embodiment of the application; and FIG. 5-b, which is a schematic diagram of the LDO in the sink current mode in an embodiment of the application.

控制电路以及偏置电压电路需要合理设置直流工作点避免MPP和MNN同时流过电流造成功耗损失。The control circuit and the bias voltage circuit need to set the DC operating point reasonably to avoid the power loss caused by the current flowing through the MPP and MNN at the same time.

source电流模式下，请参考图5-a，此时本申请实施例的LDO向负载输送电流，当负载电流变大时，LDO响应有一定时延，导致Vout电压降低。基于Vout电压的降低，误差放大电路420通过MPO2的漏极向MPO3的源极和MPP的栅极输出的电压降低；以及，误差放大电路420通过MNO2的漏极向MNO3的源极、MNN的栅极输出的电压降低。MPP作为PMOS管，其源极接稳定的电压源Vin，由于栅极电压的降低，而保持导通，MPP的源漏电流变大，使得Vout抬升，由此，电路达到平衡时得以保持Vout稳定。MNN作为NMOS管，其源极接稳定的电压地，由于栅极电压的降低，MNN保持关闭。In the source current mode, please refer to Fig. 5-a. At this time, the LDO in the embodiment of the present application delivers current to the load. When the load current increases, the LDO response has a time delay, which causes the Vout voltage to decrease. Based on the decrease in Vout voltage, the voltage output from the error amplifier circuit 420 to the source of MPO3 and the gate of MPP through the drain of MPO2 decreases; and, the error amplifier circuit 420 passes the drain of MNO2 to the source of MNO3 and the gate of MNN. The voltage of the pole output drops. As a PMOS tube, the source of MPP is connected to a stable voltage source Vin. Due to the decrease of the gate voltage, it remains on. The source leakage current of MPP becomes larger, which makes Vout rise. As a result, Vout can be kept stable when the circuit reaches equilibrium. . MNN acts as an NMOS tube, and its source is connected to a stable voltage ground. Due to the decrease of the gate voltage, the MNN remains off.

对于控制电路来说，MPO3和MNO3的栅极接收偏置电压电路提供的稳定的偏置电压。从而，MPO3作为PMOS管，由于源极电压和栅极电压的电压差降低至小于导通阈值，而关闭；MNO3作为NMOS管，由于栅极电压和源极电压的电压差增大至大于导通阈值，而导通。For the control circuit, the gates of MPO3 and MNO3 receive the stable bias voltage provided by the bias voltage circuit. Therefore, as a PMOS tube, MPO3 is turned off because the voltage difference between the source voltage and the gate voltage is reduced to less than the turn-on threshold; MNO3 is used as an NMOS tube, because the voltage difference between the gate voltage and the source voltage increases to be greater than the turn-on Threshold, while conducting.

根据大信号模型分析，通过直流工作点设置MNO3工作在饱和区，MNO3的源漏电压改变时，漏源电流不变，栅源电压VGS不变，由于MNO3的栅极电压为VBN，因此MNO3源极电压为VBN-VGS。通过合理设置VBN和MNO3的宽长比，确保VBN-VGS小于MNN的导通电压，从而保证source电流时，MNN处于截止关闭状态，避免MPP和MNN同时流过电流造成功耗损失。According to the analysis of the large signal model, the MNO3 is set to work in the saturation region through the DC operating point. When the source-drain voltage of MNO3 changes, the drain-source current does not change, and the gate-source voltage VGS does not change. Since the gate voltage of MNO3 is VBN, the MNO3 source The pole voltage is VBN-VGS. By reasonably setting the aspect ratio of VBN and MNO3, ensure that VBN-VGS is less than the on-voltage of MNN, so as to ensure that when the source current, the MNN is in the off-off state, and avoid the loss of power consumption caused by the current flowing through the MPP and MNN at the same time.

在source电流模式下的稳压工作过程如下：当Vout电压因负载电流变化等原因发生变化时候，通过反馈电路到误差放大电路反相输入端，与误差放大电路的同相端电压VREF的差值，定为ΔV。此电压信号通过误差放大电路中的跨导放大，将误差电压ΔV转化为小信号电流is，可得is＝0.5Gm×ΔV；通过MPO1/MPO2及MNO1/MNO2以及此时工作的MPO3，将电流信号转化为电压Vout_ea＝m*Gm×ΔV×rds，这里rds为MPO2和MNO2的小信号并联阻抗，EA输出的电压信号Vout_ea通过功率管MPP的栅极电压控制源漏电流来使得Vout电压稳定。The voltage stabilization process in the source current mode is as follows: When the Vout voltage changes due to changes in load current and other reasons, the difference between the inverting input terminal of the error amplifier circuit and the non-inverting terminal voltage VREF of the error amplifier circuit through the feedback circuit, Set as ΔV. This voltage signal is amplified by the transconductance in the error amplifier circuit, and the error voltage ΔV is converted into a small signal current is, which can be obtained is=0.5Gm×ΔV; through MPO1/MPO2 and MNO1/MNO2 and the working MPO3 at this time, the current The signal is transformed into a voltage Vout_ea=m*Gm×ΔV×rds, where rds is the small signal parallel impedance of MPO2 and MNO2, and the voltage signal Vout_ea output by EA controls the source leakage current through the gate voltage of the power tube MPP to stabilize the Vout voltage.

sink电流模式下，请参阅图5-b，此时负载向本申请实施例的LDO灌入电流，当灌入电流变大时，LDO响应有一定时延，导致Vout电压升高。基于Vout电压的升高，误差放大电路420通过MPO2的漏极向MPO3的源极和MPP的栅极输出的电压升高；以及，误差放大电路420通过MNO2的漏极向MNO3的源极、MNN的栅极输出的电压升高。MPP作为PMOS管，其源极接稳定的电压源Vin，由于栅极电压的升高，而保持关闭。MNN作为NMOS管，其源极接稳定的电压地，由于栅极电压的升高，而保持导通，电路达到平衡时得以保持Vout稳定。In the sink current mode, please refer to Figure 5-b. At this time, the load sinks current into the LDO of the embodiment of the present application. When the sink current becomes larger, the LDO response has a time delay, which causes the Vout voltage to rise. Based on the increase in the Vout voltage, the error amplifier circuit 420 increases the voltage output from the drain of MPO2 to the source of MPO3 and the gate of MPP; and, the error amplifier circuit 420 passes the drain of MNO2 to the source of MNO3, MNN The voltage of the gate output rises. MPP is used as a PMOS tube, and its source is connected to a stable voltage source Vin. Due to the increase in the gate voltage, it remains closed. As an NMOS tube, the source of MNN is connected to a stable voltage ground. Due to the increase of the gate voltage, it remains on, and the Vout can be kept stable when the circuit reaches equilibrium.

对于控制电路来说，MPO3和MNO3的栅极接收偏置电压电路提供的稳定的偏置电压。从而，MPO3作为PMOS管，由于源极电压和栅极电压的电压差升高至大于导通阈值，而导通；MNO3作为NMOS管，由于栅极电压和源极电压的电压差降低至小于导通阈值，而关闭。For the control circuit, the gates of MPO3 and MNO3 receive the stable bias voltage provided by the bias voltage circuit. Therefore, as a PMOS tube, MPO3 is turned on because the voltage difference between the source voltage and the gate voltage rises to greater than the turn-on threshold; as an NMOS tube, the voltage difference between the gate voltage and the source voltage is reduced to less than the turn-on threshold. Threshold is passed, and closed.

根据大信号模型分析，通过直流工作点设置MPO3工作在饱和区，MPO3的源漏电压改变时，漏源电流不变，栅源电压VGS不变，由于MPO3的栅极电压为VBP，因此MPO3源极电压为VBP+VSG。通过合理设置VBN和MPO3的宽长比，确保Vin-(VBP+VSG)小于MPP的导通电压Vth，从而保证sink电流时，MPP处于截止关闭状态，避免MPP和MNN同时流过电流造成功耗损失。According to the analysis of the large signal model, MPO3 is set to work in the saturation region through the DC operating point. When the source-drain voltage of MPO3 changes, the drain-source current does not change, and the gate-source voltage VGS does not change. Since the gate voltage of MPO3 is VBP, the MPO3 source The pole voltage is VBP+VSG. By reasonably setting the aspect ratio of VBN and MPO3, ensure that Vin-(VBP+VSG) is less than the on-voltage Vth of MPP, so as to ensure that when sink current, MPP is in an off-off state to avoid current flowing through MPP and MNN at the same time causing power consumption loss.

在sink电流模式下的稳压工作过程如下：当Vout电压因负载电流变化等原因发生变化时候，通过反馈电路到误差放大电路反相输入端，与误差放大电路的同相端电压VREF的差值，定为ΔV。此电压信号通过误差放大电路中的跨导放大，将误差电压ΔV转化为小信号电流is，可得is＝0.5Gm×ΔV；通过MPO1/MPO2及MNO1/MNO2以及此时工作的MNO3，将电流信号转化为电压Vout_ea＝m*Gm×ΔV×rds，这里rds为MPO2和MNO2的小信号并联阻抗，EA输出的电压信号Vout_ea通过功率管MPP的栅极转化为电流来使得Vout电压稳定。The working process of voltage stabilization in sink current mode is as follows: When the Vout voltage changes due to changes in load current and other reasons, the difference between the inverting input terminal of the error amplifier circuit through the feedback circuit and the non-inverting terminal voltage VREF of the error amplifier circuit, Set as ΔV. This voltage signal is amplified by the transconductance in the error amplifier circuit, and the error voltage ΔV is converted into a small signal current is, which can be obtained is=0.5Gm×ΔV; through MPO1/MPO2, MNO1/MNO2 and the working MNO3 at this time, the current The signal is converted into a voltage Vout_ea=m*Gm×ΔV×rds, where rds is the small signal parallel impedance of MPO2 and MNO2, and the voltage signal Vout_ea output by EA is converted into a current through the grid of the power tube MPP to stabilize the Vout voltage.

请参阅图6，本申请实施例中另一个LDO结构示意图。Please refer to FIG. 6, which is a schematic diagram of another LDO structure in an embodiment of the present application.

本申请实施例提供的LDO包括：基准电压源、误差放大电路、控制电路、偏置电压电路、功率管电路、反馈电路、电压源、地端和输出节点。The LDO provided by the embodiments of the present application includes: a reference voltage source, an error amplifier circuit, a control circuit, a bias voltage circuit, a power tube circuit, a feedback circuit, a voltage source, a ground terminal, and an output node.

其中，反馈电路包括串联的第一电阻R1和第二电阻R2，R1和R2的公共节点耦合至该误差放大电路的同相输入端，R2的另一端接地，R1的另一端耦合至功率管电路的输出端及电压输出端。The feedback circuit includes a first resistor R1 and a second resistor R2 connected in series. The common node of R1 and R2 is coupled to the non-inverting input end of the error amplifier circuit, the other end of R2 is grounded, and the other end of R1 is coupled to the power tube circuit. Output terminal and voltage output terminal.

功率管电路430包括第一功率管MPP，MPP为PMOS管，和第二功率管MNN，MNN为NMOS管。The power tube circuit 430 includes a first power tube MPP, which is a PMOS tube, and a second power tube MNN, which is an NMOS tube.

误差放大电路包括差分对电路、电流信号增强器和电流镜。The error amplifier circuit includes a differential pair circuit, a current signal booster and a current mirror.

差分对电路用于将该误差放大电路的第一输入端与第二输入端的电压差转化为电流信号，该电流信号增强器包括至少一个电流信号增强单元，该电流信号增强单元用于放大该差分对电路输出的电流信号；该电流镜用于放大该电流信号增强器输出的电流信号并驱动该功率管电路。The differential pair circuit is used to convert the voltage difference between the first input terminal and the second input terminal of the error amplifier circuit into a current signal. The current signal enhancer includes at least one current signal enhancement unit, and the current signal enhancement unit is used to amplify the difference. The current signal output by the circuit; the current mirror is used to amplify the current signal output by the current signal enhancer and drive the power tube circuit.

其中，差分对电路包括四个NMOS管MIN1、MIN2、MIN3和MIN4，MIN1和MIN2构成差分对，MIN3和MIN4为1:1电流镜。MIN1的栅极耦合至VREF，MIN1的源极耦合至MIN2的源极，MIN1与MIN2的公共节点耦合至偏置电流源，偏置电流源另一端接地。MIN1的漏极耦合至电流信号增强器第一输入端，MIN2的漏极耦合至MIN3的漏极，MON3的栅极耦合至MIN4的栅极，MIN3的栅极和漏极短接，MIN3和MIN4的源极耦合至LDO内部的工作电压VDD，MIN4的漏极耦合至电流信号增强器的第二输入端。Among them, the differential pair circuit includes four NMOS transistors MIN1, MIN2, MIN3, and MIN4. MIN1 and MIN2 form a differential pair, and MIN3 and MIN4 are 1:1 current mirrors. The gate of MIN1 is coupled to VREF, the source of MIN1 is coupled to the source of MIN2, the common node of MIN1 and MIN2 is coupled to the bias current source, and the other end of the bias current source is grounded. The drain of MIN1 is coupled to the first input terminal of the current signal booster, the drain of MIN2 is coupled to the drain of MIN3, the gate of MON3 is coupled to the gate of MIN4, the gate and drain of MIN3 are short-circuited, MIN3 and MIN4 The source of is coupled to the operating voltage VDD inside the LDO, and the drain of MIN4 is coupled to the second input of the current signal booster.

该电流信号增强器包括至少一个电流信号增强单元，需要说明的是，在实际应用中，可以根据需要设置一个电流信号增强单元，或多个电流信号增强单元进行级联，此处不对电流信号增强器中包含的电流信号增强单元的数量进行限定。The current signal enhancer includes at least one current signal enhancement unit. It should be noted that in practical applications, one current signal enhancement unit or multiple current signal enhancement units can be cascaded as needed. The current signal enhancement unit is not enhanced here. The number of current signal enhancement units included in the device is limited.

请参阅图7，为本申请实施例中电流信号增强单元的结构示意图。Please refer to FIG. 7, which is a schematic diagram of the structure of the current signal enhancement unit in the embodiment of the application.

该电流信号增强单元包括3个PMOS管MP1、MP2和MP3，3个NMOS管MN1、MN2和MN3；MP1漏极耦合至差分对电路的第一输出端，MP1的栅极耦合至MP2的栅极和MP3的栅极，MP1的栅极和漏极短接，MP1、MP2和MP3的源极耦合至LDO的工作电压VDD，MP2的漏极耦合至MN3的漏极，MP3的漏极耦合至MN2的漏极，MN1的漏极耦合至差分对电路的第二输出端，MN1的栅极耦合至MN2的栅极和MN3的栅极，MN1、MN2和MN3的源极接地。MP3与MN2的公共节点为该电流信号增强单元的第一输出端、MP2和MN3的公共节点为该电流信号增强单元的第二输出端。The current signal enhancement unit includes three PMOS transistors MP1, MP2 and MP3, and three NMOS transistors MN1, MN2 and MN3; the drain of MP1 is coupled to the first output terminal of the differential pair circuit, and the gate of MP1 is coupled to the gate of MP2 Connect with the gate of MP3, the gate and drain of MP1 are short-circuited, the sources of MP1, MP2 and MP3 are coupled to the operating voltage VDD of the LDO, the drain of MP2 is coupled to the drain of MN3, and the drain of MP3 is coupled to MN2 The drain of MN1 is coupled to the second output terminal of the differential pair circuit, the gate of MN1 is coupled to the gate of MN2 and the gate of MN3, and the sources of MN1, MN2, and MN3 are grounded. The common node of MP3 and MN2 is the first output terminal of the current signal enhancement unit, and the common node of MP2 and MN3 is the second output terminal of the current signal enhancement unit.

其中MP1、MP2、MP3的尺寸关系如下：Among them, the size relationship of MP1, MP2, and MP3 is as follows:

其中，k为常数，例如可以是2或3，具体此处不做限定。Among them, k is a constant, for example, it can be 2 or 3, which is not specifically limited here.

类似的，MN1、MN2和MN3也满足上述尺寸关系。Similarly, MN1, MN2, and MN3 also satisfy the above-mentioned size relationship.

误差放大电路中将误差电压ΔV转化为小信号电流is，IB为直流电流。电流信号增强单元电路耗电流为2(k+1)IB，电流信号放大倍数为(2k+1)；电流信号增强器的优点是电流信号增强单元级联时增益能耗比较优。In the error amplifier circuit, the error voltage ΔV is converted into a small signal current is, and IB is a direct current. The current consumption of the current signal enhancement unit circuit is 2(k+1)IB, and the current signal amplification factor is (2k+1); the advantage of the current signal enhancer is that the current signal enhancement unit has better gain and energy consumption when cascaded.

可选的，电流信号增强器包括两个级联的电流信号增强单元，其放大倍数为：(2k+1) ²，而消耗的电流为4(k+1)IB。 Optionally, the current signal enhancer includes two cascaded current signal enhancement units, the amplification factor of which is (2k+1) ² , and the current consumed is 4(k+1)IB.

若N级级联，其电流信号放大倍数为(2k+1) ⁿ，其消耗的电流：2n(k+1)IB。 If N stages are cascaded, the current signal amplification factor is (2k+1) ⁿ , and the current consumed: 2n(k+1)IB.

图6所示的电流信号增强器包括两个级联的电流信号增强单元，第一电流信号增强单元包括3个PMOS管MP1、MP2和MP3，3个NMOS管MN1、MN2和MN3；第二电流信号增强单元也包括3个PMOS管和3个NMOS管，分别是MP4、MP5、MP6，和MN4、MN5、MN6。The current signal enhancer shown in Figure 6 includes two cascaded current signal enhancement units. The first current signal enhancement unit includes three PMOS transistors MP1, MP2 and MP3, and three NMOS transistors MN1, MN2 and MN3; the second current The signal enhancement unit also includes 3 PMOS tubes and 3 NMOS tubes, namely MP4, MP5, MP6, and MN4, MN5, MN6.

第一电流信号增强单元中，MP1漏极耦合至差分对电路中MIN1的漏极，MP1的栅极耦合至MP2的栅极和MP3的栅极，MP1的栅极和漏极短接，MP1、MP2和MP3的源极耦合至LDO内部的工作电压VDD，MP2的漏极耦合至MN3的漏极，MP3的漏极耦合至MN2的漏极，MN1的漏极耦合至差分对电路中MIN4的漏极，MN1的栅极耦合至MN2的栅极和MN3的栅极，MN1、MN2和MN3的源极接地。MP3与MN2的公共节点耦合至该第二电流信号增强单元的第一输入端、MP2和MN3的公共节点耦合至第二电流信号增强单元的第二输入端。第二信号增强单元中，MP4、MP5、MP6、MN4、MN5和MN6的接法与第一电流信号增强单元中的MP1、MP2、MP3、MN1、MN2和MN3接法类似。MP4的漏极耦合至MP3与MN2的公共节点，MP4的漏极和栅极短接，MP4的栅极耦合至MP5的栅极和MP6的栅极，MP4的源极、MP5的源极和MP6的源极都耦合至LDO内部的工作电压VDD，MP5的漏极耦合至MN6的漏极，MP6的漏极耦合至MN5的漏极。MN4的漏极耦合至MP2和MN3的公共节点，MN4的漏极和栅极短接，MN4的栅极耦合至MN5、MN6的栅极，MN4的源极、MN5的源极和MN6的源极接地，MN6和MP5的公共节点耦合至电流镜第一输入端，MN5和MP6的公共节点耦合至电流镜的第二输入端。In the first current signal enhancement unit, the drain of MP1 is coupled to the drain of MIN1 in the differential pair circuit, the gate of MP1 is coupled to the gate of MP2 and the gate of MP3, the gate of MP1 and the drain are short-circuited, MP1 The source of MP2 and MP3 is coupled to the internal operating voltage VDD of the LDO, the drain of MP2 is coupled to the drain of MN3, the drain of MP3 is coupled to the drain of MN2, and the drain of MN1 is coupled to the drain of MIN4 in the differential pair circuit. The gate of MN1 is coupled to the gate of MN2 and the gate of MN3, and the sources of MN1, MN2, and MN3 are grounded. The common node of MP3 and MN2 is coupled to the first input terminal of the second current signal enhancement unit, and the common node of MP2 and MN3 is coupled to the second input terminal of the second current signal enhancement unit. In the second signal enhancement unit, the connections of MP4, MP5, MP6, MN4, MN5, and MN6 are similar to the connections of MP1, MP2, MP3, MN1, MN2, and MN3 in the first current signal enhancement unit. The drain of MP4 is coupled to the common node of MP3 and MN2, the drain and gate of MP4 are short-circuited, the gate of MP4 is coupled to the gate of MP5 and the gate of MP6, the source of MP4, the source of MP5 and MP6 The sources of are all coupled to the internal operating voltage VDD of the LDO, the drain of MP5 is coupled to the drain of MN6, and the drain of MP6 is coupled to the drain of MN5. The drain of MN4 is coupled to the common node of MP2 and MN3, the drain and gate of MN4 are short-circuited, the gate of MN4 is coupled to the gates of MN5, MN6, the source of MN4, the source of MN5, and the source of MN6 Ground, the common node of MN6 and MP5 is coupled to the first input terminal of the current mirror, and the common node of MN5 and MP6 is coupled to the second input terminal of the current mirror.

电流镜包括两个PMOS管MPO1、MPO2，和两个NMOS管MNO1、MNO2，MN5和MP6的公共节点耦合至MPO1的漏极，MPO1的栅极和漏极短接，MPO1的栅极耦合至MPO2的栅极，MPO1的源极和MPO2的源极耦合至LDO工作电压VDD，MPO2的漏极耦合至控制电路的第一输入端。MN6和MP5的公共节点耦合至MNO1的漏极，MNO1的栅极耦合至MNO2的栅极，MNO1的栅极和漏极短接，MNO1的源极接地，MNO2的源极接地，漏极耦合至该控制电路的第二输入端。The current mirror includes two PMOS transistors MPO1, MPO2, and two NMOS transistors MNO1, MNO2, MN5 and MP6. The common node is coupled to the drain of MPO1, the gate and drain of MPO1 are short-circuited, and the gate of MPO1 is coupled to MPO2. The gate of MPO1 and the source of MPO2 are coupled to the LDO operating voltage VDD, and the drain of MPO2 is coupled to the first input terminal of the control circuit. The common node of MN6 and MP5 is coupled to the drain of MNO1, the gate of MNO1 is coupled to the gate of MNO2, the gate and drain of MNO1 are short-circuited, the source of MNO1 is grounded, the source of MNO2 is grounded, and the drain is coupled to The second input of the control circuit.

控制电路包括第三功率管MPO3和第四功率管MNO3，MPO3为PMOS管，MNO3为NMOS管。误差放大电路420的第一输出端，即MPO2的漏极，耦合至MNO3的漏极、MPO3的源极，以及第一功率管MPP的栅极。误差放大电路420的第二输出端，即MNO2的漏极，耦合至MNO3的源极、MPO3的漏极以及第二功率管MNN的栅极。The control circuit includes a third power tube MPO3 and a fourth power tube MNO3. MPO3 is a PMOS tube, and MNO3 is an NMOS tube. The first output terminal of the error amplifier circuit 420, that is, the drain of MPO2, is coupled to the drain of MNO3, the source of MPO3, and the gate of the first power tube MPP. The second output terminal of the error amplifier circuit 420, that is, the drain of MNO2, is coupled to the source of MNO3, the drain of MPO3, and the gate of the second power tube MNN.

偏置电压电路包括PMOS管MPO4，NMOS管MNO4和第一偏置电流IB1和第二偏置电流IB2。其中MNO4的源极接地，栅极与漏极短接，漏极以及MNO3的栅极耦合至第一偏置电流的一端，第一偏置电流的另一端耦合至LDO的输入电压源Vin。第二偏置电流IB2的一端耦合至MPO3的栅极和耦合至MPO4的漏极，IB2的另一端接地，MPO4的源极耦合至LDO的输入电压源Vin，MPO4的栅极与漏极短接。The bias voltage circuit includes a PMOS tube MPO4, an NMOS tube MNO4, and a first bias current IB1 and a second bias current IB2. The source of MNO4 is grounded, the gate is shorted to the drain, the drain and the gate of MNO3 are coupled to one end of the first bias current, and the other end of the first bias current is coupled to the input voltage source Vin of the LDO. One end of the second bias current IB2 is coupled to the gate of MPO3 and the drain of MPO4, the other end of IB2 is grounded, the source of MPO4 is coupled to the input voltage source Vin of the LDO, and the gate of MPO4 is shorted to the drain .

第一功率管MPP的漏极耦合至第二功率管MNN的漏极。第一功率管MPP和第二功率管MNN的公共节点为该LDO的输出节点，输出节点的输出电压Vout可用于为负载提供稳定的电压。The drain of the first power tube MPP is coupled to the drain of the second power tube MNN. The common node of the first power tube MPP and the second power tube MNN is the output node of the LDO, and the output voltage Vout of the output node can be used to provide a stable voltage for the load.

可选的，该LDO的反馈电路包括串联的第一电阻R1和第二电阻R2，R1和R2的公共节点耦合至该误差放大电路的同相输入端，R2的另一端接地，R1的另一端耦合至功率管电路的输出端及电压输出端。Optionally, the feedback circuit of the LDO includes a first resistor R1 and a second resistor R2 connected in series, the common node of R1 and R2 is coupled to the non-inverting input end of the error amplifier circuit, the other end of R2 is grounded, and the other end of R1 is coupled To the output terminal and voltage output terminal of the power tube circuit.

可选的，该LDO还包括补偿电容CF，CF被耦合至R1两端形成前馈补偿。Optionally, the LDO further includes a compensation capacitor CF, which is coupled to both ends of R1 to form feedforward compensation.

可选的，该LDO还可以包括电容C，电容C一端耦合至Vout，另一端接地，可用于稳定输出、提升电源抑制比(PSR)和负载瞬态响应等，可以设置在片内或片外，此处不做限定。Optionally, the LDO can also include a capacitor C. One end of the capacitor C is coupled to Vout and the other end is grounded. It can be used to stabilize output, improve power supply rejection ratio (PSR) and load transient response, etc., and can be set on-chip or off-chip. , There is no limitation here.

本申请提供一种电源稳压***，包括上述实施例中提供的低压差稳压器以及耦合至该低压差稳压器的电压源和负载。The present application provides a power supply voltage stabilizing system, including the low dropout voltage regulator provided in the above-mentioned embodiment, and a voltage source and load coupled to the low dropout voltage regulator.

本申请实施例提供的LDO，可以应用于模拟芯片供电领域，具体此处不做限定。The LDO provided in the embodiments of the present application may be applied to the field of power supply for analog chips, and the specifics are not limited here.

Claims

一种低压差稳压器，其特征在于，包括：电压源、地端、误差放大电路、控制电路、功率管电路和输出节点；其中，A low-dropout voltage regulator, which is characterized by comprising: a voltage source, a ground terminal, an error amplifying circuit, a control circuit, a power tube circuit, and an output node; wherein,

所述功率管电路包括第一功率管和第二功率管，所述第一功率管和所述第二功率管串联在所述电压源和所述地端之间，所述第一功率管和第二功率管的公共连接点被耦合至所述输出节点；The power tube circuit includes a first power tube and a second power tube. The first power tube and the second power tube are connected in series between the voltage source and the ground. The common connection point of the second power tube is coupled to the output node;

所述误差放大电路用于基于所述输出节点的电压，向所述第一功率管和第二功率管的栅极提供控制电压，所述误差放大电路包括第一输出端和第二输出端，所述第一输出端被耦合至所述第一功率管的栅极，所述第二输出端被耦合至所述第二功率管的栅极；The error amplifying circuit is used to provide a control voltage to the gates of the first power tube and the second power tube based on the voltage of the output node, and the error amplifying circuit includes a first output terminal and a second output terminal, The first output terminal is coupled to the gate of the first power tube, and the second output terminal is coupled to the gate of the second power tube;

所述控制电路包括第三功率管和第四功率管，所述第三功率管的源极和漏极串接于所述第一输出端和第二输出端之间，所述第四功率管的源极和漏极串接于所述第一输出端和第二输出端之间。The control circuit includes a third power tube and a fourth power tube, the source and drain of the third power tube are connected in series between the first output terminal and the second output terminal, and the fourth power tube The source and drain of are connected in series between the first output terminal and the second output terminal.
根据权利要求1所述的低压差稳压器，其特征在于，所述低压差稳压器还包括控制逻辑，用于在所述第一功率管被导通时，导通所述第四功率管，关闭所述第三功率管；以及在所述第二功率管被导通时，导通所述第三功率管，关闭所述第四功率管。The low dropout voltage regulator according to claim 1, wherein the low dropout voltage regulator further comprises control logic for turning on the fourth power when the first power tube is turned on When the second power tube is turned on, the third power tube is turned on, and the fourth power tube is turned off.
根据权利要求1所述的低压差稳压器，其特征在于，所述第三功率管和第四功率管的栅极被耦合至稳定的偏置电压。The low dropout voltage regulator according to claim 1, wherein the gates of the third power tube and the fourth power tube are coupled to a stable bias voltage.
根据权利要求1至3中任一项所述的低压差稳压器，其特征在于，所述第一功率管为PMOS管，所述第二功率管为NMOS管，所述第一功率管的源极被耦合至所述电压源，所述第二功率管的源极被耦合至所述地端，所述第一功率管和第二功率管的漏极被耦合至所述输出节点。The low dropout voltage regulator according to any one of claims 1 to 3, wherein the first power tube is a PMOS tube, the second power tube is an NMOS tube, and the first power tube The source is coupled to the voltage source, the source of the second power tube is coupled to the ground, and the drains of the first power tube and the second power tube are coupled to the output node.
根据权利要求4所述的低压差稳压器，其特征在于，所述第三功率管为PMOS管，所述第四功率管为NMOS管；The low dropout voltage regulator according to claim 4, wherein the third power tube is a PMOS tube, and the fourth power tube is an NMOS tube;

所述误差放大电路的第一输出端耦合至所述第三功率管的源极，所述第四功率管的漏极，以及所述第一功率管的栅极；The first output terminal of the error amplifying circuit is coupled to the source of the third power tube, the drain of the fourth power tube, and the gate of the first power tube;

所述误差放大电路的第二输出端耦合至所述第三功率管的漏极，所述第四功率管的源极，以及所述第二功率管的栅极。The second output terminal of the error amplifier circuit is coupled to the drain of the third power tube, the source of the fourth power tube, and the gate of the second power tube.
根据权利要求1至5中任一项所述的低压差稳压器，其特征在于，所述低压差稳压器还包括：The low dropout voltage stabilizer according to any one of claims 1 to 5, wherein the low dropout voltage stabilizer further comprises:

偏置电压电路，用于向所述第三功率管的栅极提供稳定的第一偏置电压，向所述第四功率管的栅极提供稳定的第二偏置电压。The bias voltage circuit is used to provide a stable first bias voltage to the grid of the third power tube, and to provide a stable second bias voltage to the grid of the fourth power tube.
根据权利要求6中所述的低压差稳压器，其特征在于，所述偏置电压电路包括第一电流源、第二电流源、第五功率管和第六功率管；The low dropout voltage regulator according to claim 6, wherein the bias voltage circuit comprises a first current source, a second current source, a fifth power tube, and a sixth power tube;

所述第五功率管为NMOS管，所述第五功率管的源极被耦合至所述地端，所述第五功率管的漏极被耦合至第一电流源的一端，所述第五功率管的漏极和栅极短接，所述第一电流源的另一端接所述电压源；The fifth power tube is an NMOS tube, the source of the fifth power tube is coupled to the ground, and the drain of the fifth power tube is coupled to one end of the first current source. The drain and the gate of the power tube are short-circuited, and the other end of the first current source is connected to the voltage source;

所述第六功率管为PMOS管，所述第六功率管的源极接所述电压源，所述第六功率管的漏极被耦合至第二电流源的一端，所述第六功率管的漏极和栅极短接，所述第二电流源的另一端被耦合至所述地端。The sixth power tube is a PMOS tube, the source of the sixth power tube is connected to the voltage source, the drain of the sixth power tube is coupled to one end of the second current source, and the sixth power tube is The drain and gate of the second current source are short-circuited, and the other end of the second current source is coupled to the ground.
根据权利要求1至7中任一项所述的低压差稳压器，其特征在于，所述误差放大电路包括：The low dropout voltage regulator according to any one of claims 1 to 7, wherein the error amplifying circuit comprises:

差分对电路，电流信号增强器和电流镜，所述差分对电路用于将所述误差放大电路的第一输入端与第二输入端的电压差转化为电流信号，所述电流信号增强器包括至少一个电流信号增强单元，所述电流信号增强单元用于放大所述差分对电路输出的电流信号；所述电流镜用于放大所述电流信号增强器输出的电流信号并驱动所述功率管电路。A differential pair circuit, a current signal enhancer and a current mirror, the differential pair circuit is used to convert the voltage difference between the first input terminal and the second input terminal of the error amplifier circuit into a current signal, and the current signal enhancer includes at least A current signal enhancement unit, the current signal enhancement unit is used to amplify the current signal output by the differential pair circuit; the current mirror is used to amplify the current signal output by the current signal enhancer and drive the power tube circuit.
根据权利要求8所述的低压差稳压器，其特征在于，所述电流信号增强单元包括三个PMOS管MP1、MP2和MP3，三个NMOS管MN1、MN2和MN3；The low dropout voltage regulator according to claim 8, wherein the current signal enhancement unit comprises three PMOS tubes MP1, MP2 and MP3, and three NMOS tubes MN1, MN2 and MN3;

所述MP1漏极耦合至所述差分对电路的第一输出端，所述MP1的栅极耦合至所述MP2的栅极和所述MP3的栅极，所述MP1的栅极和漏极短接，所述MP1的源极、所述MP2的源极和所述MP3的源极耦合至LDO输入电源，所述MP2的漏极耦合至MN3的漏极，所述MP3的漏极耦合至所述MN2的漏极，所述MN1的漏极耦合至所述差分对电路的第二输出端，所述MN1的栅极耦合至所述MN2的栅极和所述MN3的栅极，所述MN1的源极、所述MN2的源极和所述MN3的源极被耦合至所述地端。所述MP3与所述MN2的公共节点耦合至所述电流信号增强单元的第一输出端、所述MP2和所述MN3的公共节点耦合至所述电流信号增强单元的第二输出端。The drain of the MP1 is coupled to the first output terminal of the differential pair circuit, the gate of the MP1 is coupled to the gate of the MP2 and the gate of the MP3, and the gate and the drain of the MP1 are short. Then, the source of MP1, the source of MP2, and the source of MP3 are coupled to the LDO input power, the drain of MP2 is coupled to the drain of MN3, and the drain of MP3 is coupled to all The drain of the MN2, the drain of the MN1 is coupled to the second output terminal of the differential pair circuit, the gate of the MN1 is coupled to the gate of the MN2 and the gate of the MN3, the MN1 The source of, the source of MN2 and the source of MN3 are coupled to the ground. The common node of the MP3 and the MN2 is coupled to the first output terminal of the current signal enhancement unit, and the common node of the MP2 and the MN3 is coupled to the second output terminal of the current signal enhancement unit.
根据权利要求8或9所述的低压差稳压器，其特征在于，所述电流信号增强器包括：The low dropout voltage regulator according to claim 8 or 9, wherein the current signal booster comprises:

第一电流信号增强单元和第二电流信号增强单元，所述第一电流信号增强单元和第二电流信号增强单元级联。A first current signal enhancement unit and a second current signal enhancement unit, and the first current signal enhancement unit and the second current signal enhancement unit are cascaded.
根据权利要求1至10中任一项所述的低压差稳压器，其特征在于，所述反馈电路包括：The low dropout voltage regulator according to any one of claims 1 to 10, wherein the feedback circuit comprises:

串联的第一电阻和第二电阻，所述第一电阻和所述第二电阻的公共节点耦合至所述误差放大电路的第一输入端，所述第二电阻接地，所述第一电阻耦合至所述功率管电路的输出端；A first resistor and a second resistor are connected in series, the common node of the first resistor and the second resistor is coupled to the first input terminal of the error amplifying circuit, the second resistor is grounded, and the first resistor is coupled To the output end of the power tube circuit;

所述低压差稳压器还包括：The low dropout voltage regulator further includes:

补偿电容CF，所述补偿电容CF耦合至所述第一电阻两端。The compensation capacitor CF is coupled to both ends of the first resistor.
一种电源稳压***，其特征在于，包括如权利要求1至11中任一项所述的低压差稳压器以及耦合至所述输出节点的负载。A power supply voltage stabilization system, characterized by comprising the low dropout voltage regulator according to any one of claims 1 to 11 and a load coupled to the output node.
一种芯片***，其特征在于，包括如权利要求1至11中任一项所述的低压差稳压器。A chip system, characterized by comprising the low dropout voltage regulator according to any one of claims 1 to 11.