CN117093515A - Memory, terminal equipment and memory system - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The application discloses a memory, terminal equipment and a memory system, wherein the memory comprises a circuit board, a memory unit, a hybrid controller, a first memory interface and a second memory interface, wherein the memory unit, the hybrid controller, the first memory interface and the second memory interface are arranged on the circuit board; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the first memory interface and/or the second memory interface. The memory provided by the application is provided with the first memory interface and the second memory interface with different interface types, so that the memory can be accessed by external hosts corresponding to different host interface types through the first memory interface and/or the second memory interface, and the application scene of the memory is enlarged.
Description
Technical Field
The present application relates to the field of data transmission technologies, and in particular, to a memory, a terminal device, and a storage system.
Background
The memory is widely applied to terminal electronic equipment and mainly comprises a core medium (Flash) and a corresponding memory interface.
At present, the types of memories are many, flash is matched with memory interfaces of different interface types, and different types of memories are respectively formed.
However, the evolution of the present-day platform is towards diversification of host interface types, each host interface type corresponds to one memory interface type, and the memory of each memory interface type can only perform data transmission with the platform of the corresponding host interface type, and each memory cannot be accessed by the platform corresponding to the different host interface type, so that the application scenario of the memory is limited.
Disclosure of Invention
In view of the above, embodiments of the present application provide a memory, a terminal device and a storage system, which overcome or at least partially solve the above problems of the prior art.
In a first aspect, an embodiment of the present application provides a memory, including a circuit board, and a memory unit, a hybrid controller, a first memory interface and a second memory interface that are disposed on the circuit board, where the hybrid controller is electrically connected to the memory unit, the first memory interface and the second memory interface, and interface types of the first memory interface and the second memory interface are different; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the first memory interface and/or the second memory interface.
The memory provided by the embodiment is configured with the first memory interface and the second memory interface with different interface types, so that the memory can be accessed by external hosts corresponding to different host interface types through the first memory interface and/or the second memory interface, and the application scene of the memory is enlarged. Further, when the external host accesses the memory through the first memory interface and the second memory interface concurrently, the access rate of the external host to the memory can be increased.
In some optional embodiments, the first memory interface is an M-PHY memory interface, the second memory interface is a PCIE memory interface, and the hybrid controller is configured with a general flash memory control function and a solid state disk control function; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the M-PHY memory interface and/or the PCIE memory interface.
The memory provided by the embodiment is configured with the M-PHY memory interface and the PCIE memory interface, so that the memory can be accessed by external hosts corresponding to different host interface types through the M-PHY memory interface and/or the PCIE memory interface, and the application scene of the memory is enlarged.
In some optional embodiments, the M-PHY memory interface is multiple, and the hybrid controller is configured to control the storage unit to perform data transmission with the external host through at least any one of the PCIE memory interface and the multiple M-PHY memory interfaces.
The memory provided by the embodiment is configured with the PCIE memory interface and the plurality of M-PHY memory interfaces, so that the memory can be accessed by external hosts corresponding to different host interface types through the PCIE memory interface and the plurality of M-PHY memory interfaces, and the application scene of the memory is enlarged. When the external host accesses the memory through the PCIE memory interface and the plurality of M-PHY memory interfaces, the access rate of the external host to the memory can be increased.
In some optional embodiments, the PCIE memory interfaces are plural, and the hybrid controller is configured to control the storage unit to perform data transmission with the external host through at least any one of the PCIE memory interfaces and the M-PHY memory interfaces.
The memory provided by the embodiment is configured with a plurality of M-PHY memory interfaces and a plurality of PCIE memory interfaces, so that the memory can be accessed by external hosts corresponding to different host interface types through the plurality of M-PHY memory interfaces and the plurality of PCIE memory interfaces, and the application scene of the memory is enlarged. When the external host accesses the memory through the multiple M-PHY memory interfaces and the multiple PCIE memory interfaces concurrently, the access rate of the external host to the memory can be further improved.
Wherein, in some alternative embodiments, the M-PHY memory interface includes a UniPro data link layer and the PCIE memory interface includes an NVME protocol layer; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the UniPro data link layer and/or the NVME protocol layer.
The M-PHY memory interface provided by the embodiment is provided with a UniPro data link layer and the PCIE memory interface is provided with an NVME protocol layer, so that the memory can be accessed by external hosts corresponding to different host interface types through the UniPro data link layer and/or the NVME protocol layer, and the application scene of the memory is enlarged.
In some alternative embodiments, the target memory size of the memory is the same as the size of the conventional solid state hard disk, and the target general-purpose flash memory size of the target general-purpose flash memory in the memory is the same as the size of the conventional general-purpose flash memory.
The memory provided by the embodiment has the same appearance size as the conventional solid state disk, and the size of the target general flash memory of the memory is the same as the size of the conventional general flash memory, so that the memory can be ensured to be suitable for application scenes of the conventional solid state disk and the conventional general flash memory, and the application scenes of the memory are enlarged.
In some optional embodiments, the target universal flash memory pins of the target universal flash memory are arranged at the target solid state disk non-reactive pin positions corresponding to the target solid state disk in the memory.
According to the memory provided by the embodiment, the target UFS pin of the target general flash memory in the memory is integrated at the position of the target solid state disk non-functional pin of the target solid state disk, so that the increase of the size of the memory due to the fact that the corresponding position is additionally arranged for the pin of the target general flash memory in the memory is avoided, and the design size of the memory is reduced.
In some optional embodiments, the hybrid controller includes a flash layer conversion layer and a hybrid control unit, where the flash layer conversion layer is configured to construct a mapping relationship table between the storage unit and the external host; the hybrid control unit is used for controlling the storage unit to carry out data transmission with an external host through the first memory interface and/or the second memory interface according to the mapping relation table.
According to the memory provided by the embodiment, the memory unit is controlled to perform data transmission with the external host through the first memory interface and/or the second memory interface according to the mapping relation table constructed by the flash memory conversion layer, so that the access success rate of the external host to the memory is improved.
In a second aspect, an embodiment of the present application provides a terminal device, including a housing and a memory provided in the first aspect, where the memory is mounted on the housing.
In a third aspect, an embodiment of the present application provides a storage system, including the terminal device and the external host provided in the second aspect, where the terminal device performs data transmission with the external host through the first memory interface and/or the second memory interface.
It will be appreciated that the advantages of the second and third aspects may be found in the relevant description of the first aspect and are not described in detail herein.
Wherein in some alternative embodiments, the external host includes a first host interface corresponding to the first memory interface and a second host interface corresponding to the second memory, the first host interface being of a different interface type than the second host interface; the hybrid controller is used for controlling the storage unit and the external host to perform data transmission through the first memory interface and the first host interface and/or performing data transmission through the second memory interface and the second host interface.
The external host and the memory provided by the embodiment are respectively configured with corresponding interfaces of different interface types, the external host can access the memory through various interface connection modes, the memory can be ensured to be accessed by other interface connection modes when the connection of one interface connection mode fails, and the access success rate of the external host for accessing the memory is improved.
In some alternative embodiments, the first memory interfaces are multiple, the second memory interfaces are multiple, the first host interfaces are multiple, the second host interfaces are multiple, each first memory interface corresponds to one first host interface, and each second memory interface corresponds to one second host interface; the hybrid controller is used for controlling the storage unit and the external host to perform data transmission through at least one first memory interface and at least one corresponding first host interface, and/or performing data transmission through at least one second memory interface and at least one corresponding second host interface.
The external host and the memory provided by the embodiment are respectively configured with a plurality of corresponding interfaces with different interface types, so that the access success rate of the external host for accessing the memory is further improved. Further, when the external host accesses the memory through the plurality of first host interfaces and the plurality of second host interfaces, the access rate of the external host to the memory can be greatly improved.
Wherein in some alternative embodiments, the first memory interfaces are plural, the second memory interfaces are plural, the external host includes plural first external hosts and plural second external hosts, each first external host includes a first host interface, each first memory interface corresponds to a first host interface, each second external host includes a second host interface, and each second memory interface corresponds to a second host interface; the hybrid controller is used for controlling the storage unit and each first external host to carry out data transmission through a first memory interface and a first host interface, and/or controlling the storage unit and each second external host to carry out data transmission through a second memory interface and a second host interface.
The memory provided by the embodiment ensures that the memory can be accessed by one or more external hosts by configuring a plurality of memory interfaces with different interface types, and further expands the application scene of the memory.
In a fourth aspect, an embodiment of the present application provides a memory, including a circuit board, and a memory unit, a transmission controller and a third memory interface that are disposed on the circuit board, where the transmission controller is electrically connected to the memory unit and the third memory interface, the transmission controller includes an auxiliary controller and a hybrid controller, the third memory interface is a first memory interface or a second memory interface that can be mutually converted, and interface types of the first memory interface and the second memory interface are different; the auxiliary controller is used for converting the third memory interface into the first memory interface when the host interface of the external host is identified as the first host interface corresponding to the first memory interface; the auxiliary controller is further used for converting the third memory interface into the second memory interface when the host interface is identified as a second host interface corresponding to the second memory interface, and the interface types of the first host interface and the second host interface are different; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the first memory interface or the second memory interface.
The third memory interface of the memory provided in this embodiment converts between the first memory interface and the second memory interface according to the identified host interface type, so that the memory can be accessed by corresponding external hosts of different host interface types through the first memory interface or the second memory interface, and the application scenario of the memory is enlarged.
In some alternative embodiments, the first memory interface is an M-PHY memory interface, the second memory interface is a PCIE memory interface, the first host interface is an M-PHY host interface, and the second host interface is a PCIE host interface; the auxiliary controller is used for converting the third memory interface into the M-PHY memory interface when the host interface is identified as the M-PHY host interface; the auxiliary controller is further configured to convert the third memory interface into a PCIE memory interface when the host interface is identified as a PCIE host interface; the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the M-PHY memory interface and the M-PHY host interface or carrying out data transmission with the external host through the PCIE memory interface and the PCIE host interface.
The memory provided by the embodiment is configured with the M-PHY memory interface and the PCIE memory interface, so that the memory can be accessed by external hosts corresponding to different host interface types through the M-PHY memory interface or the PCIE memory interface, and the application scene of the memory is enlarged.
In a fifth aspect, an embodiment of the present application provides a terminal device, including a housing and a memory provided in the fourth aspect, where the memory is mounted on the housing.
In a sixth aspect, an embodiment of the present application provides a storage system, including the terminal device and the external host provided in the fifth aspect, where the terminal device performs data transmission with the external host through the first memory interface or the second memory interface.
It will be appreciated that the advantages of the fifth and sixth aspects may be found in the fourth aspect and are not described here.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic diagram of a data transmission scenario of an existing UFS.
Fig. 2 shows a schematic diagram of a data transmission scenario of an existing SSD.
Fig. 3 illustrates a schematic view of a scenario of a storage system according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a memory in a memory system according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a package structure of a memory in a memory system according to an embodiment of the present application.
Fig. 6 shows a schematic diagram of a layout scenario of conventional SSD pins of a conventional SSD.
Figure 7 shows a layout scenario diagram of a conventional UFS pin of a conventional UFS.
Fig. 8 is a schematic diagram illustrating pin layout of a memory in a memory system according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a hardware structure of an external host in a storage system according to an embodiment of the present application.
Fig. 10 is a schematic structural diagram of an external host in a storage system according to an embodiment of the present application.
Fig. 11 is a schematic diagram of another scenario of a storage system according to an embodiment of the present application.
Fig. 12 is a schematic diagram of a memory in another memory system according to an embodiment of the present application.
Fig. 13 is a schematic diagram of an application scenario of a memory in another storage system according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.
The memory is widely applied to terminal electronic equipment and mainly comprises a core medium (Flash) and a corresponding memory interface.
At present, the types of memories are many, flash is matched with memory interfaces of different interface types, and different types of memories are respectively formed. For example, universal Flash memory (Universal Flash Storage, UFS) is composed of Flash and corresponding M-PHY memory interfaces, and Solid State Disk (Solid State Disk or Solid State Drive, SSD) is composed of Flash and corresponding PCIE memory interfaces.
However, the evolution of today's platforms is moving toward a diversification of host interface types, each host interface type corresponding to one memory interface type, the memory of each memory interface type being capable of data transfer only with the platform of the corresponding host interface type. For example, host interfaces of a Host (Host) include an M-PHY Host interface and a PCIE Host interface, UFS can only perform data transmission through the Host corresponding to the M-PHY Host interface and the M-PHY memory interface, as shown in fig. 1, and SSD can only perform data transmission through the Host corresponding to the PCIE Host interface and the PCIE memory interface, as shown in fig. 2. Each memory cannot be accessed by a platform corresponding to a different host interface type, resulting in limited application scenarios for the memory.
In view of the above problems, an embodiment of the present application provides a memory, a terminal device, and a memory system, where the memory includes a circuit board, and a memory unit, a hybrid controller, a first memory interface, and a second memory interface that are disposed on the circuit board. The hybrid controller is electrically connected to the storage unit, the first memory interface and the second memory interface are different in interface type, and the hybrid controller is used for controlling the storage unit to perform data transmission with an external host through the first memory interface and/or the second memory interface. The memory is configured with the first memory interface and the second memory interface with different interface types, so that the memory can be accessed by external hosts corresponding to different host interface types through the first memory interface and/or the second memory interface, and the application scene of the memory is enlarged. Further, when the external host accesses the memory through the first memory interface and the second memory interface concurrently, the access rate of the external host to the memory can be increased.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
Referring to fig. 3, an embodiment of the present application provides a storage system 10, where the storage system 10 includes a terminal device 100 and an external host 200, and the terminal device 100 can be connected to the external host 200 and perform data transmission with the external host 200.
In some embodiments, the terminal device 100 may be any one of a server terminal device, an in-vehicle terminal device, or an on-board terminal device, etc., and the type of the terminal device 100 is not limited herein, and may be specifically set according to actual requirements.
In this embodiment, the terminal device 100 may include a housing 110 and a memory 120, where the memory 120 is mounted on the housing 110, and the housing 110 may provide mounting support and physical protection for the memory 120.
In this embodiment, referring to fig. 4, the memory 120 includes a circuit board 121, a memory unit 122 disposed on the circuit board 121, a hybrid controller 123, a first memory interface 124 and a second memory interface 125. The hybrid controller 123 is electrically connected to the memory unit 122, the first memory interface 124 and the second memory interface 125, wherein the first memory interface 124 and the second memory interface 125 are different in interface type, and the hybrid controller 123 is used for controlling the memory unit 122 to perform data transmission with the external host 200 through the first memory interface 124 and/or the second memory interface 125. Compared with the existing memory 120 configured with only one memory interface, the memory 120 is configured with the first memory interface 124 and the second memory interface 125 of different types, so that the memory 120 can be accessed by the external hosts 200 corresponding to different host interface types through the first memory interface 124 and/or the second memory interface 125, thereby expanding the application scenario of the memory 120. Further, when the external host 200 accesses the memory 120 concurrently through the first memory interface 124 and the second memory interface 125, the access rate of the external host 200 to the memory 120 can be increased.
In some embodiments, the circuit board 121 may be any one of a printed circuit board (Printed Circuit Boards, PCB), a flexible circuit board (Flexible Printed Circuit, FPC), a ceramic circuit board, an aluminum-based circuit board, a copper-based circuit board, or the like, and the type of the circuit board 121 is not limited herein, and may be specifically set according to actual requirements.
In some embodiments, the hybrid controller 123 may include a flash layer transition layer (Flash Translation Layer, FTL) 1231 and a hybrid control unit 1232, wherein the FTL 1231 is electrically connected to the hybrid control unit 1232 and is in data interaction with the hybrid control unit 1232. The FTL 1231 may be used to construct a mapping relationship table between the storage unit 122 and the external host 200, and the hybrid control unit 1232 may be used to control, according to the mapping relationship table, the storage unit 122 to perform data transmission with the external host 200 through the first memory interface 124 and/or the second memory interface 125, so that the mapping relationship table constructed according to the FTL 1231 is implemented, and control, by controlling, the storage unit 122 to perform data transmission with the external host 200 through the first memory interface 124 and/or the second memory interface 125, the access success rate of the external host 200 for accessing the memory 120 is improved.
It can be understood that the memory 120 takes Flash as a storage medium (the storage unit 122), the memory 120 cannot be directly read and written by the external Host 200, in order to solve the problem, the FTL 1231 is configured in the hybrid controller 123, several logical mapping tables are managed by the FTL 1231 to perform an intermediate conversion, when a Host gives a logical address, the FTL 1231 establishes a corresponding mapping relationship on the logical mapping table according to the logical address, the mapping relationship includes a Block (Block) number and a Page (Page) number of Flash, and the like, and the mapping relationship is connected to a physical address on Flash, and finds data at a location corresponding to Flash according to the Block number and Page number included in the mapping relationship, and transmits the data to the Host.
In some embodiments, the first memory interface 124 may be plural, the second memory interface 125 may be plural, and the hybrid controller 123 may be configured to control the data transmission of the storage unit 122 with the external host 200 through at least one of the plural first memory interfaces 124 and the plural second memory interfaces 125.
In some embodiments, the first memory interface 124 may be an M-PHY memory interface, the second memory interface 125 may be a PCIE memory interface, the hybrid controller 123 may be configured with a general flash memory (Universal Flash Storage, UFS) control function and a Solid State Disk (Solid State Drive, SSD) control function, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data transmission with the external host 200 through the M-PHY memory interface and/or the PCIE memory interface. The memory 120 is configured with an M-PHY memory interface and a PCIE memory interface, so that the memory 120 can be accessed by external hosts 200 corresponding to different host interface types through the M-PHY memory interface and/or the PCIE memory interface, thereby expanding an application scenario of the memory 120.
As an example, the first memory interface 124 is an M-PHY memory interface, the second memory interface 125 is a PCIE memory interface, the external host 200 includes an M-PHY host interface, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data transmission with the external host 200 corresponding to the M-PHY host interface through the M-PHY memory interface.
As an example, the first memory interface 124 is an M-PHY memory interface, the second memory interface 125 is a PCIE memory interface, the external host 200 includes a PCIE host interface, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data transmission with the external host 200 corresponding to the PCIE host interface through the PCIE memory interface.
As an example, the first memory interface 124 is an M-PHY memory interface, the second memory interface 125 is a PCIE memory interface, the external host 200 includes an M-PHY host interface and a PCIE host interface, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data transmission with the external host 200 corresponding to the M-PHY host interface through the M-PHY memory interface, and perform data transmission with the external host 200 corresponding to the PCIE host interface through the PCIE memory interface.
In some embodiments, the M-PHY memory interface may be plural, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data transmission with the external host 200 through at least any one of the PCIE memory interface and the plural M-PHY memory interfaces. The memory 120 is configured with a PCIE memory interface and a plurality of M-PHY memory interfaces, so that the memory 120 can be accessed by external hosts 200 corresponding to different host interface types through the PCIE memory interface and the plurality of M-PHY memory interfaces, thereby expanding an application scenario of the memory 120. When the external host 200 concurrently accesses the memory 120 through the PCIE memory interface and the plurality of M-PHY memory interfaces, an access rate of the external host 200 to the memory 120 may be increased.
In some embodiments, the M-PHY memory interface may be plural, the PCIE memory interface may be plural, and the hybrid controller 123 may be configured to control the storage unit 122 to perform data interaction with the external host 200 through at least any one of the plural PCIE memory interfaces and the plural M-PHY memory interfaces. The memory 120 is configured with a plurality of M-PHY memory interfaces and a plurality of PCIE memory interfaces, so that the memory 120 can be accessed by external hosts 200 corresponding to different host interface types through the plurality of M-PHY memory interfaces and the plurality of PCIE memory interfaces, thereby expanding an application scenario of the memory 120. When the external host 200 concurrently accesses the memory 120 through the plurality of M-PHY memory interfaces and the plurality of PCIE memory interfaces, the access rate of the external host 200 to the memory 120 may be further increased.
In some embodiments, the M-PHY memory interface may include a UniPro data link layer, the PCIE memory interface may include an NVME protocol layer, and the hybrid controller 123 may be configured to control data transfer of the storage unit 122 with the external host 200 via the UniPro data link layer and/or the NVME protocol layer. The M-PHY memory interface is provided with a UniPro data link layer and the PCIE memory interface is provided with an NVME protocol layer, so that the memory 120 can be accessed by external hosts 200 corresponding to different host interface types through the UniPro data link layer and/or the NVME protocol layer, and an application scenario of the memory 120 is enlarged.
In some implementations, memory 120 may include a destination SSD and a destination UFS, i.e., memory 120 is comprised of a destination SSD and a destination UFS. The target memory size of the memory 120 may be the same as the conventional SSD size of the conventional SSD, and the target UFS size of the target UFS in the memory 120 may be the same as the conventional UFS size of the conventional UFS, so that the memory 120 may be ensured to be applicable to an application scenario of the conventional SSD and an application scenario of the conventional UFS, and the application scenario of the memory 120 is expanded.
The target memory size of the memory 120 may be a size set by the user according to the actual demand, or the target UFS size may be a size set by the user according to the actual demand, which is not limited herein.
In an application scenario, the memory 120 is in a BGA package (Ball Grid Array Package) structure, as shown in fig. 5, the target memory size of the memory 120 may include a target memory length (a), a target memory width (B), a target memory pin layout length (C), a target memory pin layout width (D), a target memory minimum pin pitch (E), a minimum pitch (E1) of the target memory pins with respect to a longitudinal symmetry axis, a minimum pitch (E2) of the target memory pins with respect to a width direction symmetry axis, and the target UFS size may include a target UFS pin layout length (E) and a target UFS pin layout width (F).
Wherein A is 11.50 millimeters (mm), B is 13.00mm, C is 9.50mm, D is 10.50mm, e is 0.50mm, e1 is 0.25mm, e2 is 0.25mm, E is 6.50mm, F is 6.5mm.
It should be noted that the target memory size and the target UFS size are not limited herein, and may be specifically set according to actual requirements.
In some embodiments, the target UFS pins of the target UFS may be disposed at the non-functional pin positions of the target SSD corresponding to the target SSD in the memory 120, and the target UFS pins of the target UFS are integrated at the non-functional pin positions of the target SSD, so that an increase in the size of the memory due to an additional disposition of the corresponding positions for the target UFS pins in the memory 120 is avoided, and the design size of the memory 120 is reduced.
In an application scenario, a conventional SSD pin layout diagram of a conventional SSD is shown in fig. 6, where the conventional SSD pins include conventional SSD functional pins and conventional SSD non-functional pins, where the conventional SSD non-functional pins include reserved pins (Host Specific Balls, HSB) and Ground (GND) pins, and the other pins are conventional SSD functional pins, such as pins laid in an internal pin layout area corresponding to an internal 14 row x14 column area in fig. 6.
The normal UFS pins of the normal UFS are shown in fig. 7, and the layout modes of the normal UFS pins and the normal SSD non-functional pins completely coincide, so that the target SSD non-functional pins of the target UFS in the memory 120 can be replaced by the target UFS pins of the target UFS, as shown in fig. 8, the memory 120 is guaranteed to have the characteristics of both the normal SSD and the normal UFS, and the design size of the memory 120 is reduced.
In some embodiments, the external host 200 may be any one of a mobile phone, a wearable device (such as a smart watch, a smart bracelet, a smart glasses, a smart jewelry, etc.), a tablet (Tablet Personal Computer, tablet pc), an augmented Reality (Augmented Reality, AR)/Virtual Reality (VR) device, a notebook, an Ultra-mobile Personal Computer, UMPC, a netbook, a personal digital assistant (Personal Digital Assistant, PDA), a smart panel, etc., which is not limited to the type of the external host 200, and may be specifically set according to actual needs.
In some embodiments, as shown in fig. 9, a hardware architecture diagram of the external host 200 is shown. As shown in fig. 9, the external host 200 may include a processor 210, a host interface 220, an internal memory 221, a universal serial bus (Universal Serial Bus, USB) interface 230, a charge management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, a sensor module 280, keys 290, a motor 291, an indicator 292, a camera 293, a display 294, a user identification module (Subscriber Identification Module, SIM) card interface 295, and the like. Among other things, the sensor module 280 may include a pressure sensor 280A, a gyroscope sensor 280B, a barometric pressure sensor 280C, a magnetic sensor 280D, an acceleration sensor 280E, a distance sensor 280F, a proximity light sensor 280G, a fingerprint sensor 280H, a temperature sensor 280J, a touch sensor 280K, an ambient light sensor 280L, a bone conduction sensor 280M, and the like.
It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the external host 200. In other embodiments of the present application, external host 200 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
Illustratively, the processor 210 shown in fig. 9 may include one or more processing units, such as: the processor 210 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (Digital Signal Processor, DSP), a baseband processor, and/or a Neural network processor (Neural-Network Processing Unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.
Wherein the controller may be a neural hub and command center of the external host 200. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.
A memory may also be provided in the processor 210 for storing instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. The memory may hold instructions or data that the processor 210 has just used or recycled. If the processor 210 needs to reuse the instruction or data, it may be called directly from memory. Repeated accesses are avoided and the latency of the processor 210 is reduced, thereby improving the efficiency of the system.
In some embodiments, processor 210 may include one or more interfaces. The interfaces may include an integrated circuit (Inter-Integrated Circuit, I2C) interface, an integrated circuit built-in audio (Inter-Integrated Circuit Sound, I2S) interface, a pulse code modulation (Pulse Code Modulation, PCM) interface, a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, a mobile industry processor interface (Mobile Industry Processor Interface, MIPI), a high speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface, a general purpose input/Output (GPIO) interface, a subscriber identity module (Subscriber Identity Module, SIM) interface, and/or a universal serial bus (Universal Serial Bbus, USB) interface, among others.
In some embodiments, the I2C interface is a bi-directional synchronous Serial bus including a Serial Data Line (SDA) and a Serial clock Line (Derail Clock Line, SCL). The processor 210 may contain multiple sets of I2C buses. The processor 210 may be coupled to the touch sensor 280K, charger, flash, camera 293, etc., respectively, through different I2C bus interfaces. For example, the processor 210 may couple the touch sensor 280K through an I2C interface, such that the processor 210 communicates with the touch sensor 280K through an I2C bus interface, implementing the touch function of the external host 200.
In some embodiments, the I2S interface may be used for audio communication. Processor 210 may contain multiple sets of I2S buses. The processor 210 may be coupled to the audio module 270 via an I2S bus to enable communication between the processor 210 and the audio module 270.
In some embodiments, the audio module 270 may communicate audio signals to the wireless communication module 260 through the I2S interface to implement a function of answering a call through a bluetooth headset.
In some embodiments, the PCM interface may also be used for audio communication, sampling, quantizing, and encoding analog signals. The audio module 270 and the wireless communication module 260 may be coupled by a PCM bus interface.
In some embodiments, the audio module 270 may also transmit audio signals to the wireless communication module 260 through the PCM interface to implement a function of answering a call through the bluetooth headset. It should be appreciated that both the I2S interface and the PCM interface may be used for audio communication.
In some embodiments, the UART interface is a universal serial data bus for asynchronous communications. The bus may be a bi-directional communication bus. It converts the data to be transmitted between serial communication and parallel communication. UART interfaces are typically used to connect the processor 210 with the wireless communication module 260. For example, the processor 210 communicates with a bluetooth module in the wireless communication module 260 through a UART interface to implement bluetooth functions. In some embodiments, the audio module 270 may transmit an audio signal to the wireless communication module 260 through a UART interface, implementing a function of playing music through a bluetooth headset.
In some embodiments, a MIPI interface may be used to connect processor 210 with peripheral devices such as display 294, camera 293, and the like. The MIPI interfaces include camera serial interfaces (Camera Serial Interface, CSI), display serial interfaces (Display Serial Interface, DSI), and the like. The processor 210 and the camera 293 communicate through the CSI interface to realize the photographing function of the external host 200. The processor 210 and the display 294 communicate through the DSI interface to implement the display function of the external host 200.
In some embodiments, the GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or as a data signal. The GPIO interface may be used to connect the processor 210 with the camera 293, the display 294, the wireless communication module 260, the audio module 270, the sensor module 280, and the like. The GPIO interface may also be configured as an I2C interface, an I2S interface, a UART interface, an MIPI interface, etc.
Illustratively, the USB interface 230 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 230 may be used to connect a charger to charge the external host 200, or may be used to transfer data between the external host 200 and a peripheral device. And can also be used for connecting with a headset, and playing audio through the headset. The interface may also be used to connect other electronic devices, such as AR devices, etc.
It should be understood that the connection relationship between the modules illustrated in the embodiment of the present application is only illustrative, and is not limited to the structure of the external host 200. In other embodiments of the present application, the external host 200 may also use different interfacing manners, or a combination of multiple interfacing manners, as in the above embodiments.
The charge management module 240 is configured to receive a charge input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 240 may receive a charging input of a wired charger through the USB interface 230. In some wireless charging embodiments, the charge management module 240 may receive wireless charging input through a wireless charging coil of the external host 200. The charging management module 240 may also provide power to the electronic device through the power management module 241 while charging the battery 242.
The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the external host 200 selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.
Video codecs are used to compress or decompress digital video. The external host 200 may support one or more video codecs. In this way, the external host 200 may play or record video in a variety of encoding formats, such as: moving picture experts group (Moving Picture Experts Group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.
The NPU is a Neural Network (NN) computing processor, and can rapidly process input information by referencing a biological Neural Network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent awareness of the external host 200 may be implemented by the NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.
The host interface 220 may be used to connect external memory, such as external UFS or SSD, to enable expansion of the storage capabilities of the external host 200. The external memory communicates with the processor 210 through the host interface 220 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory.
The internal memory 221 may be used to store computer executable program code that includes instructions. The processor 210 executes various functional applications of the external host 200 and data processing by executing instructions stored in the internal memory 221. The internal memory 221 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data (e.g., audio data, phonebook, etc.) created during use of the external host 200, and the like. In addition, the internal memory 221 may include a high-speed random access memory, and may further include a nonvolatile memory, such as at least one disk storage device, a flash memory device, UFS, SSD, and the like.
The software system of the external host 200 may employ a layered architecture, an event driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture.
In some embodiments, as shown in fig. 10, the external host 200 may include a first host interface 222 corresponding to the first memory interface 124 and a second host interface 223 corresponding to the second memory interface 125, the first host interface 222 being different from the second host interface 223 in interface type, and the hybrid controller 123 may be configured to control the data transmission between the memory unit 122 and the external host 200 through the first memory interface 124 and the first host interface 222, and/or through the second memory interface 125 and the second host interface 223. The external host 200 and the memory 120 are respectively configured with corresponding interfaces of different interface types, the external host 200 can access the memory 120 through a plurality of interface connection modes, so that the memory 120 can be ensured to be accessed by other interface connection modes when the connection of one interface connection mode fails, and the access success rate of the external host 200 for accessing the memory 120 is improved.
In some embodiments, the first memory interface 124 may be plural, the second memory interface 125 may be plural, the first host interface 222 may be plural, the second host interface 223 may be plural, each first memory interface 124 corresponds to one first host interface 222, and each second memory interface 125 corresponds to one second host interface 223. The hybrid controller 123 may be configured to control the data transmission between the storage unit 122 and the external host 200 via the at least one first memory interface 124 and the corresponding at least one first host interface 222, and/or via the at least one second memory interface 125 and the corresponding at least one second host interface 223. The external host 200 and the memory 120 are respectively configured with a plurality of corresponding interfaces with different interface types, so that the access success rate of the external host 200 for accessing the memory 120 is further improved. Further, when the external host 200 accesses the memory 120 through the plurality of first host interfaces 222 and the plurality of second host interfaces 223 concurrently, the access rate of the external host 200 to the memory 120 can be greatly improved.
In some embodiments, the first memory interface 124 may be plural, the second memory interface 125 may be plural, the external host 200 may include plural first external hosts each including one first host interface 222, each first memory interface 124 corresponding to one first host interface 222, and plural second external hosts each including one second host interface 223, each second memory interface 125 corresponding to one second host interface 223.
The hybrid controller 123 may be configured to control the data transfer between the storage unit 122 and each of the first external hosts through a first memory interface 124 and a first host interface 222, and/or to control the data transfer between the storage unit 122 and each of the second external hosts through a second memory interface 125 and a second host interface 223. The memory 120 further expands the application scenario of the memory 120 by configuring a plurality of memory interfaces of different interface types to ensure that the memory 120 is accessible by one or more external hosts 200.
In the memory 120, the terminal device 100 and the memory system 10 provided in this embodiment, the memory 120 includes a circuit board 121, and a memory unit 122, a hybrid controller 123, a first memory interface 124 and a second memory interface 125 that are disposed on the circuit board 121. The hybrid controller 123 is electrically connected to the memory unit 122, the first memory interface 124 and the second memory interface 125, wherein the first memory interface 124 and the second memory interface 125 are different in interface type, and the hybrid controller 123 is used for controlling the memory unit 122 to perform data transmission with the external host 200 through the first memory interface 124 and/or the second memory interface 125. The memory 120 is configured with the first memory interface 124 and the second memory interface 125 with different interface types, so that the memory 120 can be accessed by the external host 200 corresponding to different host interface types through the first memory interface 124 and/or the second memory interface 125, thereby expanding the application scenario of the memory 120. Further, when the external host 200 accesses the memory 120 concurrently through the first memory interface 124 and the second memory interface 125, the access rate of the external host 200 to the memory 120 can be increased.
Referring to fig. 11, another storage system 20 is provided in an embodiment of the present application, where the storage system 20 includes a terminal device 300 and an external host 200, and the terminal device 300 can be connected to the external host 200 and perform data transmission with the external host 200.
In some embodiments, the terminal device 300 may be any one of a server terminal device, an on-board terminal device, or an on-board terminal device, etc., and the type of the terminal device 300 is not limited herein, and may be specifically set according to actual requirements.
In this embodiment, the terminal device 300 may include a housing 310 and a memory 320, the memory 320 is mounted on the housing 310, and the housing 310 may provide mounting support and physical protection for the memory 320.
In this embodiment, referring to fig. 12, the memory 320 includes a circuit board 321, a memory unit 322 disposed on the circuit board 321, a transmission controller 323 and a third memory interface 324, the transmission controller 323 is electrically connected to the memory unit 322 and the third memory interface 324, the transmission controller 323 includes an auxiliary controller 3231 and a hybrid controller 3232, the third memory interface 324 is a first memory interface 124 or a second memory interface 125 that can be mutually converted, and interface types of the first memory interface 124 and the second memory interface 125 are different.
The auxiliary controller 3231 is for converting the third memory interface 324 into the first memory interface 124 upon recognizing that the host interface 220 of the external host 200 is the first host interface 222 corresponding to the first memory interface 124; the auxiliary controller 3231 is further configured to convert the third memory interface 324 into the second memory interface 125 when recognizing that the host interface 220 is the second host interface 223 corresponding to the second memory interface 125, and the first host interface 222 is different from the second host interface 223 in interface type. The hybrid controller 3232 is used for controlling the storage unit 322 to perform data transmission with the external host 200 through the first memory interface 124 or the second memory interface 125. The third memory interface 324 of the memory 320 converts between the first memory interface 124 and the second memory interface 125 according to the identified host interface type, so that the memory 320 can be accessed by the corresponding external hosts 200 of different host interface types through the first memory interface 124 or the second memory interface 125, thereby expanding the application scenario of the memory 320.
In an application scenario, as shown in fig. 13, the storage unit 322 includes a plurality of first storage units 3221 and a plurality of second storage units 3222, the hybrid controller 3232 is composed of an SSD controller 3233 and a UFS controller 3234, the plurality of first storage units 3221 are electrically connected in parallel to the SSD controller 3233, and the plurality of second storage units 3222 are electrically connected in parallel to the UFS controller 3234. The SSD controller 3233 and the UFS controller 3234 are electrically connected to the auxiliary controller 3231, and the SSD controller 3233 and the UFS controller 3234 are electrically connected to the third memory interface 324 through the auxiliary controller 3231, respectively.
In some implementations, memory 320 may include a destination SSD and a destination UFS, i.e., memory 320 is comprised of a destination SSD and a destination UFS. The target memory size of the memory 320 may be the same as the conventional SSD size of the conventional SSD, and the target UFS size of the target UFS in the memory 320 may be the same as the conventional UFS size of the conventional UFS, so that the memory 320 may be ensured to be suitable for an application scenario of the conventional SSD and an application scenario of the conventional UFS, and the application scenario of the memory 320 is enlarged.
The target memory size of the memory 320 may be a size set by the user according to the actual requirement, or the target UFS size may be a size set by the user according to the actual requirement, which is not limited herein.
In some embodiments, the destination UFS pins of the destination UFS of the memory 320 may be disposed at destination SSD non-functional pin positions corresponding to the destination SSD in the memory 320, and the destination UFS pins of the destination UFS are integrated at destination SSD non-functional pin positions of the destination SSD, so that an increase in the size of the memory due to an additional disposition of corresponding positions for the destination UFS pins in the memory 320 is avoided, and the design size of the memory 320 is reduced.
In the memory 320, the terminal device 300 and the storage system 20 provided in this embodiment, the memory 320 includes a circuit board 321, and a storage unit 322, a transmission controller 323 and a third memory interface 324 that are disposed on the circuit board 321. The transmission controller 323 is electrically connected to the storage unit 322 and the third memory interface 324, the transmission controller 323 includes an auxiliary controller 3231 and a hybrid controller 3232, the third memory interface 324 is a first memory interface 124 or a second memory interface 125 that can be mutually converted, and the interface types of the first memory interface 124 and the second memory interface 125 are different. The auxiliary controller 3231 is configured to convert the third memory interface 324 into the first memory interface 124 when recognizing that the host interface 220 of the external host 200 is the first host interface 222 corresponding to the first memory interface 124, and the auxiliary controller 3231 is further configured to convert the third memory interface 324 into the second memory interface 125 when recognizing that the host interface 220 is the second host interface 223 corresponding to the second memory interface 125, wherein the first host interface 222 is different from the second host interface 223 in interface type, and the hybrid controller 3232 is configured to control the storage unit 322 to perform data transmission with the external host 200 through the first memory interface 124 or the second memory interface 125. The third memory interface 324 of the memory 320 converts between the first memory interface 124 and the second memory interface 125 according to the identified host interface type, so that the memory 320 can be accessed by the corresponding external hosts 200 of different host interface types through the first memory interface 124 or the second memory interface 125, thereby expanding the application scenario of the memory 320.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be appreciated by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (17)
1. The memory is characterized by comprising a circuit board, a memory unit, a hybrid controller, a first memory interface and a second memory interface, wherein the memory unit, the hybrid controller, the first memory interface and the second memory interface are arranged on the circuit board, the hybrid controller is electrically connected with the memory unit, the first memory interface and the second memory interface, and the interface types of the first memory interface and the second memory interface are different;
the hybrid controller is used for controlling the storage unit to carry out data transmission with an external host through the first memory interface and/or the second memory interface.
2. The memory of claim 1, wherein the first memory interface is an M-PHY memory interface and the second memory interface is a PCIE memory interface, the hybrid controller configured with a general purpose flash memory control function and a solid state disk control function;
The hybrid controller is configured to control the storage unit to perform data transmission with the external host through the M-PHY memory interface and/or the PCIE memory interface.
3. The memory of claim 2 wherein the M-PHY memory interface is a plurality, and the hybrid controller is configured to control the memory unit to perform data transfer with the external host via at least any one of the PCIE memory interface and the plurality of M-PHY memory interfaces.
4. The memory of claim 3 wherein the PCIE memory interfaces are plural, and the hybrid controller is configured to control the storage unit to perform data transmission with the external host through at least any one of the plural PCIE memory interfaces and the plural M-PHY memory interfaces.
5. The memory of claim 2 wherein the M-PHY memory interface comprises a UniPro data link layer and the PCIE memory interface comprises an NVME protocol layer;
the hybrid controller is used for controlling the storage unit to carry out data transmission with the external host through the UniPro data link layer and/or the NVME protocol layer.
6. The memory of claim 2, wherein the target memory size of the memory is the same as a conventional solid state hard drive size, and the target general purpose flash memory size of the target general purpose flash memory in the memory is the same as a conventional general purpose flash memory size.
7. The memory of claim 6, wherein the target universal flash memory pins of the target universal flash memory are arranged at target solid state drive non-functional pin locations corresponding to target solid state drives in the memory.
8. The memory according to any one of claims 1 to 7, wherein the hybrid controller includes a flash layer conversion layer for constructing a mapping relationship table of the storage unit and the external host, and a hybrid control unit;
the hybrid control unit is used for controlling the storage unit to carry out data transmission with the external host through the first memory interface and/or the second memory interface according to the mapping relation table.
9. A terminal device comprising a housing and a memory as claimed in any one of claims 1 to 8, the memory being mounted to the housing.
10. A storage system comprising a terminal device according to claim 9 and an external host, the terminal device being in data transfer with the external host via the first memory interface and/or the second memory interface.
11. The storage system of claim 10, wherein the external host includes a first host interface corresponding to the first memory interface and a second host interface corresponding to the second memory, the first host interface being of a different interface type than the second host interface;
the hybrid controller is configured to control the storage unit and the external host to perform data transmission through the first memory interface and the first host interface, and/or perform data transmission through the second memory interface and the second host interface.
12. The storage system of claim 11, wherein the first memory interfaces are plural, the second memory interfaces are plural, the first host interfaces are plural, the second host interfaces are plural, each first memory interface corresponds to one first host interface, and each second memory interface corresponds to one second host interface;
The hybrid controller is configured to control the storage unit and the external host to perform data transmission through at least one first memory interface and at least one corresponding first host interface, and/or perform data transmission through at least one second memory interface and at least one corresponding second host interface.
13. The storage system of claim 10, wherein the first memory interfaces are plural, the second memory interfaces are plural, the external hosts include first external hosts and second external hosts, each first external host includes a first host interface, each first memory interface corresponds to a first host interface, each second external host includes a second host interface, each second memory interface corresponds to a second host interface;
the hybrid controller is used for controlling the storage unit and each first external host to carry out data transmission through a first memory interface and a first host interface, and/or controlling the storage unit and each second external host to carry out data transmission through a second memory interface and a second host interface.
14. The memory is characterized by comprising a circuit board, a storage unit, a transmission controller and a third memory interface, wherein the storage unit, the transmission controller and the third memory interface are arranged on the circuit board, the transmission controller is electrically connected with the storage unit and the third memory interface, the transmission controller comprises an auxiliary controller and a hybrid controller, the third memory interface is a first memory interface or a second memory interface which can be mutually converted, and the interface types of the first memory interface and the second memory interface are different;
the auxiliary controller is used for converting the third memory interface into the first memory interface when the host interface of the external host is identified as the first host interface corresponding to the first memory interface; the auxiliary controller is further configured to convert the third memory interface into the second memory interface when the host interface is identified as a second host interface corresponding to the second memory interface, where the first host interface is different from the second host interface in interface type;
the hybrid controller is used for controlling the storage unit to carry out data transmission with the external host through the first memory interface or the second memory interface.
15. The memory of claim 14, wherein the first memory interface is an M-PHY memory interface, the second memory interface type is a PCIE memory interface, the first host interface is an M-PHY host interface, and the second host interface is a PCIE host interface;
the auxiliary controller is used for converting the third memory interface into the M-PHY memory interface when the host interface is identified as the M-PHY host interface; the auxiliary controller is further configured to convert the third memory interface into the PCIE memory interface when the host interface is identified as the PCIE host interface;
the hybrid controller is configured to control the storage unit to perform data transmission with the external host through the M-PHY memory interface and the M-PHY host interface, or perform data transmission with the external host through the PCIE memory interface and the PCIE host interface.
16. A terminal device comprising a housing and a memory as claimed in any one of claims 14 to 15, the memory being mounted to the housing.
17. A storage system comprising a terminal device according to claim 16 and an external host, the terminal device being in data transfer with the external host via the first memory interface or the second memory interface.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854377A (en) * | 2010-01-25 | 2010-10-06 | 杭州东信北邮信息技术有限公司 | Information platform system supporting wireless terminal and implementation method thereof |
| CN104885067A (en) * | 2012-10-29 | 2015-09-02 | 高通股份有限公司 | Operating m-phy based communications over pci-based interfaces, and related cables, connectors, systems and methods |
| US20160077994A1 (en) * | 2014-09-11 | 2016-03-17 | Kabushiki Kaisha Toshiba | Interface circuit |
| CN106295374A (en) * | 2016-08-23 | 2017-01-04 | 记忆科技(深圳)有限公司 | A kind of encryption Hub device supporting multiple UFS equipment |
| CN106776391A (en) * | 2016-12-13 | 2017-05-31 | 成都信息工程大学 | The control method and device of a kind of NAND Flash controllers |
| US20200097397A1 (en) * | 2018-09-20 | 2020-03-26 | SK Hynix Inc. | Apparatus and method for checking valid data in memory system |
| CN114691535A (en) * | 2020-12-28 | 2022-07-01 | 三星电子株式会社 | Memory device, method of operating the same, and method of operating memory controller |
| CN114828098A (en) * | 2020-09-10 | 2022-07-29 | 华为技术有限公司 | Data transmission method and electronic equipment |
| CN115858426A (en) * | 2022-12-23 | 2023-03-28 | 浪潮(山东)计算机科技有限公司 | Hard disk interface, hard disk and electronic equipment |
| CN116231815A (en) * | 2023-05-10 | 2023-06-06 | 荣耀终端有限公司 | Method for controlling charging and electronic equipment |
-
2023
- 2023-10-09 CN CN202311296791.2A patent/CN117093515A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854377A (en) * | 2010-01-25 | 2010-10-06 | 杭州东信北邮信息技术有限公司 | Information platform system supporting wireless terminal and implementation method thereof |
| CN104885067A (en) * | 2012-10-29 | 2015-09-02 | 高通股份有限公司 | Operating m-phy based communications over pci-based interfaces, and related cables, connectors, systems and methods |
| US20160077994A1 (en) * | 2014-09-11 | 2016-03-17 | Kabushiki Kaisha Toshiba | Interface circuit |
| CN106295374A (en) * | 2016-08-23 | 2017-01-04 | 记忆科技(深圳)有限公司 | A kind of encryption Hub device supporting multiple UFS equipment |
| CN106776391A (en) * | 2016-12-13 | 2017-05-31 | 成都信息工程大学 | The control method and device of a kind of NAND Flash controllers |
| US20200097397A1 (en) * | 2018-09-20 | 2020-03-26 | SK Hynix Inc. | Apparatus and method for checking valid data in memory system |
| CN114828098A (en) * | 2020-09-10 | 2022-07-29 | 华为技术有限公司 | Data transmission method and electronic equipment |
| CN114691535A (en) * | 2020-12-28 | 2022-07-01 | 三星电子株式会社 | Memory device, method of operating the same, and method of operating memory controller |
| CN115858426A (en) * | 2022-12-23 | 2023-03-28 | 浪潮(山东)计算机科技有限公司 | Hard disk interface, hard disk and electronic equipment |
| CN116231815A (en) * | 2023-05-10 | 2023-06-06 | 荣耀终端有限公司 | Method for controlling charging and electronic equipment |
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