CN117076374A

CN117076374A - PCIe stream bus conversion method, device, equipment and medium

Info

Publication number: CN117076374A
Application number: CN202311340940.0A
Authority: CN
Inventors: 张静东; 王江为; 王彦伟; 郝锐
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-17
Filing date: 2023-10-17
Publication date: 2023-11-17
Anticipated expiration: 2043-10-17
Also published as: CN117076374B

Abstract

The invention relates to a conversion method, a device, equipment and a medium of a PCIe stream bus, wherein the conversion method comprises a type conversion lookup table setting step, which comprises the following steps: acquiring a first request type value corresponding to the PCIe AXIS stream bus and a second request type value corresponding to the PCIe stream bus; the first request type value and the second request type value are the same in request type; setting the bit number of the first request type value as a first preset value, and setting the bit number of the second request type value as a second preset value; wherein the first preset value is smaller than the second preset value. By the technical scheme, the problem that the conventional PCIe AXIS streaming bus cannot be connected with a PCIe streaming bus in a standard format can be solved.

Description

PCIe stream bus conversion method, device, equipment and medium

Technical Field

The invention relates to the technical field of PCIe streaming buses, in particular to a conversion method, a device, equipment and a medium of a PCIe streaming bus.

Background

With the continuous development of high-speed serial communication technology, more and more devices support PCIe buses to communicate with each other, and how to quickly multiplex existing technology modules to match different computing platforms is more and more important.

FPGA (Field Programmable Gate Array, field programmable and gate array), which is a multi-component heterogeneous chip with high programmability, has abundant hardware resources inside, such as look-up tables, registers, DSP cores, AI cores, PCIe HIP, high-speed Serdes and bus interconnect resources, etc., which can be used by users to implement various data processing engines, complex bus protocols and network protocols, etc.

PCIe is a point-to-point and high bandwidth communication connection standard for interconnection of peripheral components, and the physical layer is based on a high-speed serial-parallel converter channel, adopts a differential circuit design, and has a higher signal transmission frequency; compared with a pure parallel bus, the signal transmission distance is large.

AXI is an advanced extensible interface defined by ARM, widely used in the field of chip design such as SoC, and is part of AMBA (Advanced Microcontroller Bus Architecture ) standard. AXI-Stream (AXIs) is an AXI-based data streaming bus standard, has no address feature, allows a data burst transmission mode, and has the characteristics of data transmission and small processing delay.

Different bus interfaces are respectively used by the existing FPGA manufacturers, the Xilinx PCIe new version IP adopts a self-defined four-type bus interface form, the standard PCIe bus format cannot be docked, the cross-platform transplanting multiplexing is difficult to design, and the design scheme needs to be changed; for example, when the FPGA design scheme using Xilinx PCIe HIP is migrated to the Intel FPGA platform, since the Intel PCIe HIP bus interface adopts the PCIe standard transaction layer TLP format, a large number of PCIe TLP packet logics need to be changed to adapt to the new platform.

Therefore, the prior art scheme does not solve the matching problem of the PCIe HIP bus interface in the form of a non-Xilinx AXIS bus and the standard PCIe ST bus interface, and also cannot match the design of the AXIS bus interface using the new hard core IP with the standard PCIe ST bus interface, so that the universality is low and the module transplanting multiplexing rate is low.

Disclosure of Invention

In order to solve the technical problems, the invention provides a conversion method, a device, equipment and a medium of a PCIe streaming bus, which are used for solving the problem that the current PCIe AXIS streaming bus cannot be connected with a PCIe streaming bus in a standard format.

To achieve the above object, the present invention provides a conversion method of a PCIe streaming bus, the conversion method including a type conversion look-up table setting step including:

acquiring a first request type value corresponding to the PCIe AXIS stream bus and a second request type value corresponding to the PCIe stream bus; the first request type value and the second request type value are the same in request type;

setting the bit number of the first request type value as a first preset value, and setting the bit number of the second request type value as a second preset value; wherein the first preset value is smaller than the second preset value.

Further, setting the number of bits of the first request type value as a first preset value and setting the number of bits of the second request type value as a second preset value, specifically includes:

the number of bits of the first request type value is set to 4 and the number of bits of the second request type value is set to 7.

Further, the request types of the first request type value and the second request type value are the same, which specifically includes:

the request type of both the first request type value and the second request type value includes at least one of: memory read requests, memory write requests, type 0 configuration read requests, type 1 configuration read requests, type 0 configuration write requests, type 1 configuration write requests, and memory read responses.

Further, the conversion method further includes a first-in first-out buffer setting step, which includes:

and respectively setting first-in first-out buffer memory before the PCIe AXIS streaming bus and/or the transmitting interface of the PCIe streaming bus for storing request or response frames.

Further, the conversion method further includes a step of reading and transmitting the data packet with the integrated polling and priority, which includes:

setting a sending priority value for each type of first-in first-out buffer memory respectively; the size of the sending priority value is matched with the priority sending sequence of the data frames.

Further, the step of reading and sending the data packet by combining the polling and the priority further comprises the following steps:

setting data packet sending values for each type of first-in first-out buffer memory respectively; wherein, the data packet sending value is matched with the sending priority value corresponding to each type of first-in first-out buffer.

when all the first-in first-out caches have to be sent data packets, the data packets in the first-in first-out caches with the lowest sending priority value are sent preferentially until the sending ending condition is met.

Further, the method for preferentially sending the data packet in the first-in first-out buffer memory with the lowest sending priority value until the sending ending condition is met specifically includes:

and ending the data packet sending operation when the number of the data packets sent by the first-in first-out buffer with the lowest sending priority value reaches the corresponding data packet sending value or the first-in first-out buffer with the lowest sending priority value is empty.

and when the transmission priority values corresponding to the plurality of first-in first-out caches are the same, carrying out polling and data packet transmission operation according to the serial numbers of the plurality of first-in first-out caches.

Further, the conversion method further includes a step of converting the PCIe AXIS streaming bus interface to a PCIe streaming bus interface, including:

detecting whether a first AXIS streaming transaction layer data packet exists on an AXIS_RC interface of the PCIe AXIS streaming bus;

if so, caching corresponding frame header information, and reorganizing the first AXIS streaming transaction layer data packet according to a frame header format of the streaming transaction layer data packet corresponding to the PCIe streaming bus.

Further, the step of converting the PCIe AXIS streaming bus interface to a PCIe streaming bus interface further includes:

and caching the first streaming transaction layer data packet generated by recombining the first AXIS streaming transaction layer data packet to a first-in first-out cache corresponding to the PCIe streaming bus interface.

detecting whether a second AXIS stream transaction layer data packet exists on an AXIS_CQ interface of the PCIe AXIS stream bus;

if so, searching a request type corresponding to the second AXIS streaming transaction layer data packet from a request type lookup table;

and if the request type corresponding to the second AXIS streaming transaction layer data packet is a memory write request, caching corresponding frame header information and load data, and reorganizing the second AXIS streaming transaction layer data packet according to the frame header format of the streaming transaction layer data packet corresponding to the PCIe streaming bus.

and caching the second streaming transaction layer data packet generated by recombining the second AXIS streaming transaction layer data packet to a first-in first-out cache corresponding to the PCIe streaming bus interface.

and reading the transaction layer data packet from all first-in first-out caches corresponding to the PCIe streaming bus interface according to the step of reading and sending the data packet fused with the priority, and sending the transaction layer data packet to the PCIe streaming bus interface.

Further, the conversion method further includes a step of converting the PCIe streaming bus interface to the PCIe AXIS streaming bus interface, including:

detecting whether a third stream transaction layer data packet exists on an interface of the PCIe stream bus;

if so, searching a request type corresponding to the third stream transaction layer data packet through the type conversion lookup table;

and acquiring the descriptor type of the corresponding AXIS streaming bus according to the request type corresponding to the third streaming transaction layer data packet, and recombining the third streaming transaction layer data packet according to the descriptor type.

Further, the step of converting the PCIe streaming bus interface to the PCIe AXIS streaming bus interface further includes:

and carrying out data frame buffering on the third AXIS streaming transaction layer data packet generated in a re-establishing mode.

judging whether the PCIe AXIS stream bus meets the condition of sending data packets or not; if yes, sending the third AXIS streaming transaction layer data packet; wherein the conditions for transmitting the data packet include at least one of: whether the preparation signal of the PCIe AXIS stream bus meets the preset sending condition or not, and whether the spare tag and the window value of the PCIe AXIS stream bus meet the preset sending condition or not.

The invention also provides a conversion device of the PCIe stream bus, which is used for realizing the conversion method of the PCIe stream bus, and comprises a type conversion lookup table setting unit, which comprises the following steps:

a request type value acquisition unit for: acquiring a first request type value corresponding to the PCIe AXIS stream bus and a second request type value corresponding to the PCIe stream bus; the first request type value and the second request type value are the same in request type;

A request type value bit setting unit for: setting the bit number of the first request type value as a first preset value, and setting the bit number of the second request type value as a second preset value; wherein the first preset value is smaller than the second preset value.

The present invention further provides a computer device, including a memory, a processor, and a computer program, where the computer program is stored in the memory and can be executed on the processor, and the processor executes the computer program to implement the steps of the PCIe streaming bus translation method.

The present invention further provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the PCIe streaming bus translation method described above.

Compared with the prior art, the technical scheme provided by the invention has the following technical effects:

in the invention, in order to reliably and conveniently perform mutual conversion on interfaces of a PCIe AXIS streaming bus and a PCIe streaming bus, a type conversion lookup table is firstly set;

that is, since the request types of the two bus interfaces are defined differently, the request type value of the bus before conversion is used as the input of the lookup table, and the request type value corresponding to the bus after conversion is searched;

In addition, through analyzing the descriptor format or frame header format of different buses in detail and combining with the data processing flow, the mutual conversion between the AXIS and PCIe ST buses is realized, so that the problem of matching and transplanting of PCIe hard core summarization interfaces of different FPGA platforms and the bus interfaces of the existing applications is solved; by using the method, different platforms and applications can rapidly realize bidirectional conversion between bus interfaces, and the transplantation of the existing platforms and schemes is accelerated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an Intel PCIe hard core ST bus interface of the prior art;

FIG. 2 is a schematic diagram of a prior art Xilinx PCIe new version HIP bus interface;

FIG. 3 is a flowchart illustrating a method for converting a PCIe streaming bus according to a first embodiment of the present invention;

FIG. 4 is a schematic diagram of an AXIS bus interface for converting an ST bus interface of a PCIe hard core to an application in accordance with an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of an ST bus interface for transferring an AXIS bus interface of a PCIe hard core in accordance with an embodiment of the present invention;

FIG. 6 is a diagram showing the structure of a translation look-up table of AXIS bus and ST bus frame request types according to an embodiment of the present invention;

FIG. 7 is an exemplary diagram of a request frame descriptor (a) and PCIe ST_TX header format (b) for a request in an embodiment of the present invention;

FIG. 8 is an exemplary diagram of a request-side response frame description (a) and PCIe ST_RX header format (b) in an actual embodiment of the present invention;

FIG. 9 is a schematic diagram of a data frame processing flow when an application module or PCIe hard core ST_TX bus interface is converted into an AXIS_CC interface and an AXIS_RQ interface according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a data frame processing flow when the AXIS_CC interface and the AXIS_RQ interface of the PCIe hard core or the application module are transferred to the ST_TX bus interface according to an embodiment of the present invention;

FIG. 11 is a block diagram illustrating a PCIe streaming bus translation device in accordance with a second embodiment of the present invention;

fig. 12 is an internal structure diagram of a computer device in the second embodiment of the present invention.

Detailed Description

In the prior art, the meanings of each English abbreviation are as follows:

FPGA, field Programmable Gate Array, field programmable gate array;

HIP, hard Intellectual Property, hard core IP;

PCIe, peripheral Component Interconnect Express, peripheral component interconnect express;

AXI, advanced eXtensible Interface, advanced extensible interface;

AXIS, namely AXI-Streaming, streaming AXIS bus interface;

ST, streaming;

the BIOS, basic Input Output System, basic input output system;

LUT, look Up Table;

TLP, transaction Layer Packet, transaction layer packet;

FIFO, first-In-First-Out, first-In First-Out buffer.

As shown in fig. 1 to fig. 2, in the prior art solution, xilinx FPGA PCIe HIP adopts a custom AXIS bus interface, defines 4 types of input/output interfaces, further defines a plurality of descriptor expressions PCIe TLP frame header, and a user analyzes specific PCIe TLP request or response frame data from a HIP interface according to a timing instruction of an IP manual bus interface.

Intel FPGA PCIe HIP adopts bus interface time sequence and frame head format defined by PCIe standard, and has the advantages of low user learning cost, convenient design and transplantation, and high multiplexing rate.

According to the method and the device, conversion of the ST bus interface and the three bus interface of the PCIe hard core is realized by analyzing TLP packets of different types according to the standard format of the PCIe header.

The technical scheme has the following defects:

the PCIe transaction layer interface based on the FPGA is converted into a three-bus interface and a method, the PCIe standard defines an interface bus to be converted into a three-bus interface format, because the new version Xilinx HIP adopts an IP interface with a custom 4-class bus format instead of an ST bus interface, the scheme is not applicable,

hardware resources such as FIFO resources used in the scheme are more, TLP packets of different types need to be analyzed and classified in detail, and the scheme is complex; meanwhile, the universality of the three bus interfaces is not high, and the module transplanting multiplexing rate is low.

Therefore, the present invention provides a PCIe streaming bus conversion method, device, equipment and medium, so as to solve the above problems.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Embodiment one:

as shown in fig. 3, an embodiment of the present invention provides a conversion method of a PCIe streaming bus, where the conversion method includes a type conversion lookup table setting step, including:

In a specific embodiment, in order to reliably and conveniently perform mutual conversion on interfaces of the PCIe AXIS streaming bus and the PCIe streaming bus, a type conversion lookup table is firstly set;

that is, since the request type definitions of the two bus interfaces are different, the request type value corresponding to the bus after conversion needs to be retrieved by taking the request type value of the bus before conversion as the input of the lookup table.

In an actual embodiment, a bus interface and frame format adaptation conversion method is provided for the situation that the frame format of each interface transaction layer of a PCIe hard core bus of an Xilinx FPGA platform is not a standard format, so as to solve the problems that in the prior art, when the FPGA design is transplanted across platforms, a large amount of bus interface logic needs to be modified, the occupied hardware resources are more, the scheme is complex, the multiplexing cannot be realized, and the like.

In an AXIS bus interface adopted by a Xilinx new-edition PCIe hard core, each interface uses specific descriptor to describe PCIe TLP frame header information, but the descriptor format and word sequence are completely different from the TLP frame header format definition in a standard PCIe ST bus, and each type of descriptor needs to be converted when an FPGA design scheme is transplanted; the definition of each signal of the interface in the AXIS bus and the PCIe ST bus adopted and the time sequence between them are different, and the TLP frame header format and the time sequence of each signal in the conversion interface need to be converted and assigned.

In a preferred embodiment, the method for setting the number of bits of the first request type value to a first preset value and setting the number of bits of the second request type value to a second preset value specifically includes:

In a preferred embodiment, the request types of the first request type value and the second request type value are the same, and specifically include:

In a practical embodiment, the conversion lookup tables of two Xilinx PCIe hard core request types and PCIe standard frame types are used for searching and matching different types of request and response frames and transceiving channels;

the conversion from the request type of the AXIS bus to the request type of the ST bus is realized by using a 4-input 7-output lookup table, and the conversion can be realized by using a 7-input 4-output lookup table reversely.

In a preferred embodiment, the conversion method further includes a first-in first-out buffer setting step including:

first-in first-out buffers are respectively arranged in front of the PCIe AXIS streaming bus and/or the transmitting interface of the PCIe streaming bus and are used for storing request or response frames.

In a practical embodiment, a buffer FIFO is provided in front of the transmission interfaces such as axis_rq, axis_cc or st_tx, and is used to store the request or response frames output by the PCIe hard core or the application, and then it is determined whether to trigger a frame of data according to the downstream status (such as valid tag and remaining window value).

In a preferred embodiment, the conversion method further includes a step of sending a poll and priority combined packet read, which includes:

setting a sending priority value for each type of first-in first-out buffer memory respectively; wherein, the size of the sending priority value is matched with the sending priority sequence of the data frames.

In a preferred embodiment, the step of sending the poll and priority combined packet read further comprises:

setting data packet sending values for each type of first-in first-out buffer memory respectively; wherein, the data packet sending value is matched with the sending priority value corresponding to each type of first-in first-out buffer memory.

In a preferred embodiment, the method for preferentially sending the data packet in the first-in first-out buffer with the lowest sending priority value until the sending ending condition is met specifically includes:

And when the transmission priority values corresponding to the first-in first-out caches are the same, carrying out polling and data packet transmission operation according to the serial numbers of the first-in first-out caches.

In an actual embodiment, when cache frames are fetched from a plurality of FIFOs and sent to a hard core IP or an application interface, a data frame is sent by adopting an algorithm of combining polling and priority, each type of FIFO is provided with a priority value, and FIFOs with high priority are sent preferentially; if the FIFO of the high priority is empty, the same-level FIFO polls to send a frame TLP packet.

The improved polling priority sending algorithm judging process flow is as follows:

1) Defining priorities for the 4 FIFOs respectively, for example, sequentially 1, 2, 3 and 3, wherein the priorities are gradually reduced from 1 to 3;

2) Setting parameters of N1 packets, N2 packets and N3 packets of priority transmission (for example, N1, N2 and N3 are all 3) for the FIFO of each priority level;

3) Assuming that all the 4 FIFOs have data packets to be transmitted, firstly transmitting the data packets in the FIFO 1 (with priority of 1) until the number of transmitted packets reaches N1 packets or the FIFO 1 is empty; then send out the data packet in FIFO 2 (priority 2) according to the same logic;

4) The priority of the FIFO 3 is the same as that of the FIFO 4, and the polling sequentially transmits the data in the two FIFOs, namely the N3 packet and the N4 packet;

5) After four FIFOs poll one round, the transmission is repeated and circulated according to the logic when the data is still in the FIFO 1.

In a preferred embodiment, the translation method further includes the step of converting the PCIe AXIS streaming bus interface to a PCIe streaming bus interface, including:

if so, caching the corresponding frame header information, and reorganizing the first AXIS streaming transaction layer data packet according to the frame header format of the streaming transaction layer data packet corresponding to the PCIe streaming bus.

In a preferred embodiment, the step of converting the PCIe AXIS streaming bus interface to a PCIe streaming bus interface further includes:

if the request exists, searching a request type corresponding to the second AXIS streaming transaction layer data packet from a request type lookup table;

If the request type corresponding to the second AXIS streaming transaction layer data packet is a memory write request, caching corresponding frame header information and load data, and reorganizing the second AXIS streaming transaction layer data packet according to the frame header format of the streaming transaction layer data packet corresponding to the PCIe streaming bus.

and reading the transaction layer data packet from all the first-in first-out caches corresponding to the PCIe streaming bus interface according to the step of reading and sending the data packet fused with the priority, and sending the transaction layer data packet to the PCIe streaming bus interface.

In an actual embodiment, the data frame processing flow when the AXIS_CC interface and the AXIS_RQ interface of the PCIe hard core or the application module are converted to the ST_TX bus interface is specifically implemented as follows:

1) Sequentially detecting whether the AXIS_RC and AXIS_CQ interfaces have TLP packets or not;

2) If the AXIS_RC interface has a data packet, caching frame header information, reorganizing a TLP packet header and data according to an ST bus TLP frame header format, and caching the TLP packet header and the data to the FIFO to be sent;

3) If the AXIS_CQ interface has a data packet, searching an FMT_TYPE lookup table and judging whether the data packet is a read request, a write request or other data packets;

4) If the request is a memory write request, the frame header information and the load data are cached, and are recombined according to a PCIe TLP packet frame standard format and cached to the FIFO to be sent;

5) The polling priority judging module reads TLP packets in each buffer memory FIFO according to each FIFO priority and a polling algorithm and sends the TLP packets to the ST bus interface.

In a preferred embodiment, the translation method further includes a PCIe streaming bus interface to PCIe AXIS streaming bus interface step, which includes:

detecting whether a third stream transaction layer data packet exists at an interface of the PCIe stream bus;

if so, searching a request type corresponding to the third stream transaction layer data packet through a type conversion lookup table;

and obtaining the descriptor type of the corresponding AXIS streaming bus according to the request type corresponding to the third streaming transaction layer data packet, and reorganizing the third streaming transaction layer data packet according to the descriptor type.

In a preferred embodiment, the step of converting the PCIe streaming bus interface to the PCIe AXIS streaming bus interface further includes:

judging whether the PCIe AXIS stream bus meets the condition of sending the data packet; if yes, a third AXIS stream transaction layer data packet is sent; wherein the conditions for transmitting the data packet include at least one of: whether the preparation signal of the PCIe AXIS stream bus meets the preset sending condition, and whether the spare tag and the window value of the PCIe AXIS stream bus meet the preset sending condition.

In an actual embodiment, the processing flow of the data frame when the application module or PCIe hard core st_tx bus interface transfers the axis_cc interface and the axis_rq interface is specifically as follows:

1) Detecting whether a frame TLP packet exists;

2) Searching the request type through a type conversion lookup table;

3) Judging the type and reorganizing TLP header information according to different types of descriptors of the AXIS bus;

4) Caching the frame after the recombination is completed;

5) Judging the ready signal or the spare tag and the window value, and sending a frame of TLP data packet.

In summary, the method and the device for converting the AXIS bus and the PCIe transaction layer bus provided by the embodiment of the invention can convert an AXIS bus interface adopted by an Xilinx FPGA PCIe hard core into a standard PCIe hard core ST bus interface adopted by an application module, as shown in fig. 5;

At the same time, the standard PCIe hard core ST bus interface may also be converted to an AXIS bus interface of the application module, as shown in fig. 4.

The following will explain in detail these two cases:

since the request types of the two bus interfaces are different in definition, the request type value of the bus before conversion is used as the input of the lookup table to search the request type value corresponding to the bus after conversion, and the conversion relationship between the request type value and the request type value is shown in the following table 1, wherein the ST bus TLP frame FmtType of the response packet is 0x4a, and corresponds to the RC and CC interfaces of the AXIS.

Table 1 request response type field conversion table

As shown in fig. 6, the conversion of the request type of the AXIS bus to the request type of the ST bus is implemented using a 4-in 7-out lookup table, and the conversion may be implemented using a 7-in 4-out lookup table in the opposite direction.

As shown in fig. 7 to 8, for TLP reading and writing the memory request frame descriptor/frame header information, the key fields include address, request ID, request type, double word number, completion ID, tag (tag number), last BE, first BE (Byte Enable head and tail Byte Enable), etc., and it can BE found by comparison that the Byte distribution formats of these information on the two buses are different. Wherein Last BE, first BE and a start of packet (Sop) are in the user signal line of the AXIS bus.

Referring to fig. 9, a flow chart of processing a data frame when an application module or PCIe hard core st_tx bus interface transfers an axis_cc interface and an axis_rq interface according to an embodiment of the present invention is shown:

1) Detecting whether a frame TLP packet exists;

2) Searching the request type through a type conversion lookup table;

4) Caching the frame after the recombination is completed;

Referring to fig. 10, a flow chart of data frame processing when the axis_cc interface and the axis_rq interface of the PCIe hard core or the application module are converted to the st_tx bus interface in the practical embodiment of the present invention is specifically implemented as follows:

In addition, the improved polling priority transmission algorithm in the practical embodiment of the invention judges the processing flow as follows:

In summary, the embodiment of the invention provides a conversion method and a processing device for an AXIS bus and a PCIe ST bus in an FPGA, which realizes the mutual conversion between the AXIS bus and the PCIe ST bus by analyzing the descriptor formats or the frame header formats of different buses in detail and combining the data processing flow, thereby solving the problem of matching and transplanting of PCIe hard core summarization interfaces of different FPGA platforms and bus interfaces of the prior application; by using the method, different platforms and applications can rapidly realize bidirectional conversion between bus interfaces, and the transplantation of the existing platforms and schemes is accelerated.

The problems and advantages to be solved are as follows:

1) Conversion of Requester Request bus interface and PCIe sending interface bus of Xilinx PCIe hard core;

2) Conversion of Requester Completion bus interface and PCIe receiving interface bus of Xilinx PCIe hard core;

3) Conversion of Completer Completion bus interface and PCIe sending interface bus of Xilinx PCIe hard core;

4) Conversion of Completer Request bus interface and PCIe receiving interface bus of Xilinx PCIe hard core;

5) Conversion of a transmitting interface of an application and a Requester Request bus interface of the Xilinx PCIe hard core;

6) Conversion of a receiving interface of the application and a Requester Completion bus interface of the Xilinx PCIe hard core;

7) Conversion of a transmitting interface bus of an application and a Completer Completion bus interface of the Xilinx PCIe hard core;

8) Conversion of a receiving interface of the application and a Completer Request bus interface of the Xilinx PCIe hard core;

9) A buffer FIFO is arranged in front of the transmitting interfaces such as AXIS_RQ, AXIS_CC or ST_tx and the like and is used for storing request or response frames output by a PCIe hard core or an application, and then whether to trigger a frame of data is determined according to the downstream states (such as effective tag and residual window value);

10 Two conversion lookup tables of Xilinx PCIe hard core request types and PCIe standard frame types are arranged and used for searching and matching different types of request and response frames and receiving and transmitting channels;

11 Application designs using xix AXIS bus PCIe hard cores can be quickly migrated to platforms (e.g., intel FPGAs) using standard PCIe transaction layer frame format PCIe hard cores;

12 At the same time, the method is convenient for quickly transplanting the application design of a PCIe hard core platform (such as Intel FPGA) using a standard PCIe transaction layer frame format to an AXIS bus PCIe hard core platform of Xilinx.

13 When the buffer frames are fetched from a plurality of FIFOs and sent to the hard core IP or the application interface, a data frame is sent by adopting an algorithm of combining polling and priority, each type of FIFO is provided with a priority value, and the FIFOs with high priority are sent preferentially; if the FIFO of the high priority is empty, the same-level FIFO polls to send a frame TLP packet.

It should be noted that, although the steps in the flowchart are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

Embodiment two:

as shown in fig. 11, an embodiment of the present invention further provides a PCIe streaming bus conversion device, configured to implement the PCIe streaming bus conversion method, where the conversion device includes a type conversion lookup table setting unit, where the type conversion lookup table setting unit includes:

a request type value acquisition unit for: acquiring a first request type value corresponding to the PCIe AXIS stream bus and a second request type value corresponding to the PCIe stream bus; the first request type value and the second request type value are matched with each other;

In a preferred embodiment, the request type value bit setting unit is further configured to:

In a preferred embodiment, the request type value acquisition unit is further configured to:

In a preferred embodiment, the conversion apparatus further comprises a first-in first-out buffer setting unit for:

In a preferred embodiment, the conversion device further comprises a poll and priority fusion packet read transmission unit for:

In a preferred embodiment, the poll and priority combined packet read and send unit is further configured to:

In a preferred embodiment, the translation device further comprises a PCIe AXIS streaming bus interface to PCIe streaming bus interface unit for:

In a preferred embodiment, the PCIe AXIS streaming bus interface to PCIe streaming bus interface unit is further configured to:

In a preferred embodiment, the translation device further comprises a PCIe streaming bus interface to PCIe AXIS streaming bus interface unit for:

In a preferred embodiment, the PCIe streaming bus interface to PCIe AXIS streaming bus interface unit is further configured to:

For specific limitations of the above apparatus, reference may be made to the limitations of the method described above, which are not repeated here.

Each of the modules in the above apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware, or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

The computer device may be a terminal, as shown in fig. 12, which includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It is to be understood that the structures shown in the above figures are merely block diagrams of some of the structures associated with the present invention and are not limiting of the computer devices to which the present invention may be applied, and that a particular computer device may include more or less components than those shown, or may combine some of the components, or have a different arrangement of components.

Implementation of all or part of the flow in the above-described embodiment methods may be accomplished by a computer program that instructs related hardware, and the computer program may be stored in a non-volatile computer readable storage medium, and the computer program may include the flow in the above-described embodiment methods when executed.

Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

It should be noted that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A method for converting a PCIe streaming bus, the method comprising a type conversion look-up table setting step comprising:

2. The PCIe streaming bus translation method according to claim 1, wherein setting the number of bits of the first request type value to a first preset value and setting the number of bits of the second request type value to a second preset value specifically comprises:

3. The PCIe streaming bus translation method according to claim 1 or 2, wherein the request types of the first request type value and the second request type value are the same, specifically comprising:

4. The method for converting a PCIe streaming bus according to claim 3, further comprising a first-in first-out buffer setting step comprising:

5. The method of claim 4, further comprising the step of sending a poll and priority fused packet read, comprising:

6. The PCIe streaming bus translation method according to claim 5, wherein said poll and priority combined packet read and send step further comprises:

7. The PCIe streaming bus translation method according to claim 6, wherein said poll and priority combined packet read and send step further comprises:

8. The PCIe streaming bus translation method according to claim 7, wherein the step of preferentially sending the data packet in the fifo buffer with the lowest sending priority value until the sending end condition is satisfied, specifically comprises:

9. The PCIe streaming bus translation method according to claim 8, wherein said poll and priority combined packet read and send step further comprises:

10. The PCIe streaming bus translation method according to claim 9, further comprising a PCIe AXIS streaming bus interface to PCIe streaming bus interface step comprising:

11. The PCIe streaming bus translation method according to claim 10, wherein the PCIe AXIS streaming bus interface to PCIe streaming bus interface step further comprises:

12. The PCIe streaming bus translation method according to claim 11, wherein the PCIe AXIS streaming bus interface to PCIe streaming bus interface step further comprises:

13. The PCIe streaming bus translation method according to claim 12, wherein the PCIe AXIS streaming bus interface to PCIe streaming bus interface step further comprises:

14. The PCIe streaming bus translation method according to claim 13, wherein the PCIe AXIS streaming bus interface to PCIe streaming bus interface step further comprises:

15. The PCIe streaming bus translation method according to claim 14, further comprising a PCIe streaming bus interface to PCIe AXIS streaming bus interface step comprising:

16. The PCIe streaming bus translation method according to claim 15, wherein the PCIe streaming bus interface to PCIe AXIS streaming bus interface step further comprises:

17. The PCIe streaming bus translation method according to claim 16, wherein the PCIe streaming bus interface to PCIe AXIS streaming bus interface step further comprises:

18. A translation device for PCIe streaming bus according to any of claims 1-17, wherein said translation device comprises a type translation look-up table setting unit comprising:

19. Computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method for translating a PCIe streaming bus according to any of claims 1-17 when the computer program is executed.

20. A computer readable storage medium storing a computer program, which when executed by a processor performs the steps of the PCIe streaming bus translation method according to any one of claims 1-17.