CN117060921A - Differential voltage-controlled loop oscillator, frequency adjusting method and electronic circuit - Google Patents
Differential voltage-controlled loop oscillator, frequency adjusting method and electronic circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention provides a differential voltage-controlled loop oscillator, a frequency adjusting method and an electronic circuit, wherein the differential voltage-controlled loop oscillator comprises M single-order substructures, the single-order substructures are connected end to form an oscillation loop, and M is an odd number greater than or equal to 3; the single-order substructure comprises an inverter unit and a transmission gate unit, wherein the transmission gate unit is connected with the output end of the inverter unit; the transmission gate unit comprises a voltage-controlled transmission gate and a resistance-fixing module which are connected in parallel, wherein the voltage-controlled transmission gate is used for adjusting the upper limit frequency of the differential voltage-controlled loop oscillator, and the resistance-fixing module is used for adjusting the lower limit frequency of the differential voltage-controlled loop oscillator. The differential voltage-controlled loop oscillator, the frequency adjusting method and the electronic circuit solve the problem that the actual oscillation frequency range is not symmetrically distributed on two sides of the target center frequency due to the fact that the lower limit frequency of the existing oscillator cannot be independently adjusted.
Description
Technical Field
The present invention relates to the field of oscillators, and in particular, to a differential voltage-controlled loop oscillator, a frequency adjustment method, and an electronic circuit.
Background
The voltage-controlled loop oscillator is widely applied in the fields of computers, electronics, communication and the like at present; wherein the differential voltage controlled loop oscillator is subject to the above-mentioned applications due to its excellent anti-interference capability.
One of the important indexes for designing the differential voltage-controlled loop oscillator is the frequency oscillation range and the target center frequency; in design, the upper limit frequency of the oscillator, i.e. the oscillation frequency at which the impedance corresponding to the voltage controlled transmission gate being turned on is minimal, is of priority, since it directly determines the upper limit of the division coefficient of the feedback divider in the phase locked loop application.
The problems encountered with practical designs are: once the size of the voltage-controlled transmission gate corresponding to the upper limit frequency is established, the lower limit frequency when the impedance corresponding to the closing of the voltage-controlled transmission gate is maximum is also established; the lower limit frequency has no individually adjustable path or variable, so that there is a problem in that the upper and lower limit frequencies of the oscillator cannot be finely controlled according to a specific application range, resulting in that the actual oscillation frequency range is not symmetrically distributed on both sides of the target center frequency.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a differential voltage-controlled loop oscillator, a frequency adjusting method and an electronic circuit for solving the problem that the lower limit frequency of the existing oscillator cannot be adjusted individually, so that the actual oscillation frequency range is not symmetrically distributed on both sides of the target center frequency.
To achieve the above and other related objects, the present invention provides a differential voltage-controlled loop oscillator, including M single-stage substructures, where each single-stage substructures is connected end to form an oscillation loop, and M is an odd number greater than or equal to 3;
the single-order substructure comprises an inverter unit and a transmission gate unit, wherein the transmission gate unit is connected with the output end of the inverter unit; wherein,
the transmission gate unit comprises a voltage-controlled transmission gate and a resistance-fixing module which are connected in parallel, wherein the voltage-controlled transmission gate is used for adjusting the upper limit frequency of the differential voltage-controlled loop oscillator, and the resistance-fixing module is used for adjusting the lower limit frequency of the differential voltage-controlled loop oscillator.
Optionally, the voltage-controlled transmission gate includes a first NMOS tube and a first PMOS tube, where the first NMOS tube and the first PMOS tube are connected in parallel, and gates of the first NMOS tube and the first PMOS tube are connected with a set of differential control signals; wherein the voltage controlled transmission gate has a minimum impedance and a maximum impedance, and the value of the upper limit frequency is adjusted by the value of the minimum impedance.
Optionally, the number of the voltage-controlled transmission gates is greater than or equal to 1; when the number of the voltage-controlled transmission gates is greater than 1, the voltage-controlled transmission gates are connected in parallel, and the parallel structure has the minimum impedance and the maximum impedance.
Optionally, the resistance-fixing module is implemented by adopting a normally open transmission gate, a resistor series-parallel structure or a resistor-capacitor series-parallel structure, the value of the fixed impedance of the resistance-fixing module is larger than the value of the minimum impedance of the voltage-controlled transmission gate and smaller than the value of the maximum impedance of the voltage-controlled transmission gate, and the value of the lower limit frequency is adjusted by the value of the fixed impedance.
Optionally, the normally open transmission gate includes a second NMOS tube and a second PMOS tube, the second NMOS tube is connected in parallel with the second PMOS tube, a gate of the second NMOS tube is connected with an opening voltage, and a gate of the second PMOS tube is connected with a reference ground.
Optionally, the number of the normally open transmission gates is greater than or equal to 1; when the number of the normally open transmission gates is greater than 1, the normally open transmission gates are connected in parallel, and the parallel structure has the fixed impedance.
Optionally, the voltage-controlled transmission gate is controlled to be turned on or turned off by a set of differential control signals, where the set of differential control signals includes an NMOS gate control voltage and a PMOS gate control voltage, and the PMOS gate control voltage is a difference voltage between the turn-on voltage and the NMOS gate control voltage.
The invention also provides an electronic circuit comprising a differential voltage controlled loop oscillator as claimed in any one of the preceding claims.
The invention also provides a frequency adjusting method of the differential voltage-controlled loop oscillator, which comprises the following steps:
the two ends of the voltage-controlled transmission gate of each single-order substructure in the differential voltage-controlled loop oscillator are connected with a resistance-fixing module in parallel;
and adjusting the upper limit frequency of the differential voltage-controlled loop oscillator through the voltage-controlled transmission gate, and adjusting the lower limit frequency of the differential voltage-controlled loop oscillator through the resistance-fixing module.
Optionally, the voltage-controlled transmission gate has a minimum impedance and a maximum impedance, and the fixed impedance module has a fixed impedance, wherein the value of the fixed impedance module is greater than the value of the minimum impedance of the voltage-controlled transmission gate and less than the value of the maximum impedance of the voltage-controlled transmission gate; the value of the upper limit frequency is adjusted by the value of the minimum impedance, and the value of the lower limit frequency is adjusted by the value of the fixed impedance.
As described above, the differential voltage-controlled loop oscillator, the frequency adjusting method and the electronic circuit of the invention adjust the center frequency by connecting the fixed impedance modules in parallel at the two ends of the voltage-controlled transmission gate in each single-order substructure and adjusting the lower limit frequency of the oscillator by using the fixed impedance value thereof, so that the actual oscillation frequency range of the oscillator is distributed on the two sides of the target center frequency more symmetrically, and the problem that the lower limit frequency cannot be considered when the traditional oscillator structure adjusts the upper limit frequency is avoided.
Drawings
Fig. 1 is a schematic diagram of a differential voltage-controlled loop oscillator according to a first embodiment.
Fig. 2 is a schematic structural diagram of a single-level substructure according to a first embodiment.
Fig. 3 shows a schematic diagram of a completely new oscillator configuration, for example of 3 stages.
Fig. 4 shows a schematic diagram of a conventional oscillator structure taking 3 stages as an example.
Fig. 5 is a diagram showing an upper limit frequency simulation waveform of the conventional oscillator structure shown in fig. 4.
Fig. 6 shows an upper limit frequency simulation waveform for the completely new oscillator structure shown in fig. 3.
Fig. 7 is a diagram showing a lower limit frequency simulation waveform of the conventional oscillator structure shown in fig. 4.
Fig. 8 shows a lower limit frequency simulation waveform for the completely new oscillator configuration shown in fig. 3.
Fig. 9 is a schematic diagram of a pll circuit in the second embodiment.
Description of element reference numerals
100. Differential voltage controlled loop oscillator
110. Single level substructure
111. Inverter unit
112. Transmission gate unit
112a voltage-controlled transmission gate
112b resistance-fixing module
120. Output buffer structure
200. Phase discriminator
300. Filter device
400. Frequency divider
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, the present embodiment provides a differential voltage-controlled loop oscillator 100, which includes M single-order substructures 110, where each single-order substructures 110 is connected end to form an oscillation loop, and M is an odd number greater than or equal to 3; further, an output buffer structure 120 is further included and is connected to the output terminal of the mth single-level substructure 110. Wherein:
as shown in fig. 2, the single-stage substructure 110 includes an inverter unit 111 and a transmission gate unit 112, and the transmission gate unit 112 is connected to an output terminal of the inverter unit 111.
Specifically, as shown in fig. 3, the inverter unit 111 is implemented with an inverter INV; the input end of the inverter INV is connected to the output end of the transmission gate unit 112 in the previous stage of single-stage substructure 110, the output end is connected to the input end of the transmission gate unit 112 in the present stage of single-stage substructure 110, the first power supply end is connected to the inverter operating voltage vd1, and the second power supply end is connected to the reference ground gnd.
It should be noted that, for the first single-level sub-structure 110, the previous single-level sub-structure 110 refers to the mth single-level sub-structure 110; for the second to mth single-level sub-structures 110, the previous single-level sub-structure 110 refers to the previous single-level sub-structure 110, e.g., for the second single-level sub-structure 110, the previous single-level sub-structure 110 refers to the first single-level sub-structure 110.
Specifically, as shown in fig. 2 and 3, the transmission gate unit 112 includes a voltage-controlled transmission gate 112a and a resistance-determining module 112b, which are connected in parallel; the voltage-controlled transmission gate 112a is used for adjusting the upper limit frequency of the differential voltage-controlled loop oscillator 100, and the resistance determining module 112b is used for adjusting the lower limit frequency of the differential voltage-controlled loop oscillator 100.
As an example, as shown in fig. 3, the voltage-controlled transmission gate 112a includes a first NMOS tube NM1 and a first PMOS tube PM1, the first NMOS tube NM1 and the first PMOS tube PM1 are connected in parallel, and gates of the first NMOS tube NM1 and the first PMOS tube PM1 are connected to a set of differential control signals. As an example of the presence of a metal such as,
the source electrode of the first NMOS tube NM1 is connected with the source electrode of the first PMOS tube PM1 and is used as the input end of the voltage-controlled transmission gate 112a, the drain electrode of the first NMOS tube NM1 is connected with the drain electrode of the first PMOS tube PM1 and is used as the output end of the voltage-controlled transmission gate 112a, the grid electrode of the first NMOS tube NM1 is connected with the grid control voltage vc of the NMOS tube, the grid electrode of the first PMOS tube PM1 is connected with the grid control voltage vcn of the PMOS tube, and the grid control voltage vc of the NMOS tube and the grid control voltage vcn of the PMOS tube are a group of differential control signals.
As an alternative, the PMOS gate control voltage vcn is a difference voltage between the on voltage vd2 and the NMOS gate control voltage cn, i.e., vcn=vd2-vc; the on voltage vd2 is a gate control voltage corresponding to the NMOS transistor when the constant resistance module 112b is implemented by using a normally-on transmission gate.
Wherein, the voltage-controlled transmission gate 112a is controlled by the NMOS gate control voltage vc and the PMOS gate control voltage vcn to be opened or closed; when the NMOS gate control voltage vc controls the first NMOS transistor NM1 to be fully turned on and the PMOS gate control voltage vcn controls the first PMOS transistor PM1 to be fully turned on, the voltage-controlled transmission gate 112a is fully turned on, and at this time, the voltage-controlled transmission gate 112a has the minimum impedance r1_min; when the NMOS gate control voltage vc controls the first NMOS NM1 to be completely turned off and the PMOS gate control voltage vcn controls the first PMOS PM1 to be completely turned off, the voltage-controlled transmission gate 112a is fully turned off, and at this time, the voltage-controlled transmission gate 112a has the maximum impedance r1_max; the present embodiment adjusts the value of the upper limit frequency of the differential voltage controlled loop oscillator 100 by the value of the minimum impedance r1_min.
In practical applications, the number of the voltage-controlled transmission gates 112a in the embodiment is not limited, that is, the number of the voltage-controlled transmission gates 112a is 1 or more; when the number of the voltage-controlled transmission gates 112a is greater than 1, the voltage-controlled transmission gates 112a are connected in parallel, and the parallel structure has a minimum impedance r1_min and a maximum impedance r1_max.
When designing, for the case that the number of the voltage-controlled transmission gates 112a is greater than 1, the minimum impedance and the maximum impedance of each voltage-controlled transmission gate 112a can be the same through the design of the width-to-length ratio of the MOS device, and of course, different voltage-controlled transmission gates are also feasible, which has no substantial influence on the embodiment; the impedance of the parallel structure is guaranteed to be the minimum impedance r1_min after all the voltage-controlled transmission gates 112a are fully opened, and the impedance of the parallel structure is guaranteed to be the maximum impedance r1_max after all the voltage-controlled transmission gates are fully closed. In order to simplify the control, the minimum impedance and the maximum impedance of each voltage-controlled transmission gate 112a are generally the same through the design of the width-to-length ratio of the MOS device, and each voltage-controlled transmission gate 112a corresponds to the same set of differential control signals.
As an example, as shown in fig. 3, the fixed resistance module 112b is implemented with a normally open transmission gate, a resistor series-parallel structure, or a resistor-capacitor series-parallel structure, and the value of the fixed resistance R2 of the fixed resistance module 112b is greater than the value of the minimum resistance r1_min of the voltage-controlled transmission gate and less than the value of the maximum resistance r1_max of the voltage-controlled transmission gate, that is, r1_min < r2< r1_max; the present embodiment adjusts the value of the lower limit frequency by fixing the value of the impedance R2.
It should be noted that, the resistance determination module 112b is implemented by adopting a resistor series-parallel structure, which means that the resistance determination module 112b includes a resistor series structure and/or a resistor parallel structure, that is, the resistance determination module 112b may be implemented by adopting a resistor series structure only, a resistor parallel structure only, or a series-parallel structure including both a resistor series structure and a resistor parallel structure.
Similarly, the implementation of the resistance determination module 112b in a series-parallel structure refers to that the resistance determination module 112b includes a series-parallel structure and/or a parallel structure, that is, the resistance determination module 112b may be implemented only in a series-parallel structure, or may be implemented only in a parallel-parallel structure, or may be implemented in a series-parallel structure including both a series-parallel structure and a parallel-parallel structure.
As an alternative, the blocking module 112b is implemented using a normally open transmission gate. The normally-open transmission gate comprises a second NMOS tube NM2 and a second PMOS tube PM2, the second NMOS tube NM2 and the second PMOS tube PM2 are connected in parallel, the grid electrode of the second NMOS tube NM2 is connected with an opening voltage vd2, and the grid electrode of the second PMOS tube PM2 is connected with a reference ground gnd. As an example of the presence of a metal such as,
the source electrode of the second NMOS tube NM2 is connected with the source electrode of the second PMOS tube PM2 and is used as the input end of the normally-on transmission gate, the drain electrode of the second NMOS tube NM2 is connected with the drain electrode of the second PMOS tube PM2 and is used as the output end of the normally-on transmission gate, the grid electrode of the second NMOS tube NM2 is connected with the starting voltage vd2, and the grid electrode of the second PMOS tube PM2 is connected with the reference ground gnd. The second NMOS transistor NM2 and the second PMOS transistor PM2 are fully turned on under the control of the turn-on voltage vd2 and the reference ground gnd, so that the transmission gate is in a normally open state and has a fixed impedance R2.
In practical application, the number of the normally open transmission gates in the embodiment is not limited, that is, the number of the normally open transmission gates is greater than or equal to 1; when the number of the normally open transmission gates is greater than 1, the normally open transmission gates are connected in parallel, and the parallel structure has fixed impedance R2.
When designing, for the case that the number of normally open transmission gates is greater than 1, the fixed impedance of each normally open transmission gate is the same through the design of the width-to-length ratio of the MOS device, and of course, different normally open transmission gates are also feasible, so that no substantial influence is caused on the embodiment, and the impedance of the parallel structure is only required to be the fixed impedance R2 after all normally open transmission gates are fully opened. In order to simplify the control, the fixed impedance of each normally-open transmission gate is generally the same through the design of the width-to-length ratio of the MOS device, and each normally-open transmission gate corresponds to the same set of control voltages (e.g., the turn-on voltage vd2 and the reference ground gnd).
The output buffer structure 120 is configured to perform waveform shaping on the primary oscillation signal generated by the oscillation loop, and then buffer and output a final oscillation signal.
Specifically, as shown in fig. 3, the output buffer structure 120 is implemented by using a buffer BUF; the input terminal of the buffer BUF is connected to the output terminal of the transmission gate unit 112 in the mth single-stage substructure 110, the output terminal generates a final oscillation signal, the first power supply terminal is connected to the buffer operating voltage vd3, and the second power supply terminal is connected to the reference ground gnd. In practical applications, to simplify the control, the inverter operating voltage vd1, the normally open transmission gate turn-on voltage vd2, and the buffer operating voltage vd3 may be the same voltage.
The embodiment also provides a frequency adjusting method of the differential voltage-controlled loop oscillator, which comprises a step S1 and a step S2. Wherein:
step S1: the resistor blocks 112b are connected in parallel to the two ends of the voltage-controlled transmission gate 112a of each single-stage substructure 110 in the differential voltage-controlled loop oscillator 100, so as to obtain the oscillator structure shown in fig. 3.
Step S2: the upper limit frequency of the differential voltage controlled loop oscillator 100 is adjusted by the voltage controlled transmission gate 112a, and the lower limit frequency of the differential voltage controlled loop oscillator 100 is adjusted by the resistance block 112 b.
Wherein the voltage-controlled transmission gate 112a has a minimum impedance r1_min and a maximum impedance r1_max, the fixed impedance block 112b has a fixed impedance R2, and the value of the fixed impedance R2 of the fixed impedance block 112b is greater than the value of the minimum impedance r1_min of the voltage-controlled transmission gate 112a and less than the value of the maximum impedance r1_max of the voltage-controlled transmission gate 112a, i.e., r1_min < r2< r1_max; the value of the upper limit frequency is adjusted by the value of the minimum impedance r1_min, and the value of the lower limit frequency is adjusted by the value of the fixed impedance R2.
The principle of precisely controlling the upper limit frequency and the lower limit frequency of the oscillator is analyzed from the resistance or impedance angle; the resistance determination module 112b is implemented by a normally open transmission gate.
Assuming that the impedance value of the voltage-controlled transmission gate 112a is R1 and the fixed impedance value of the normally-open transmission gate is R2, the total impedance
When the voltage-controlled transmission gate 112a is fully opened, its impedance value is the minimum impedance R1_min, the total impedanceR1_min<R2, the total impedance Rtotal is mainly determined by the minimum impedance R1_min, and the total impedance Rtotal obtains the minimum value, so as to determine the upper limit frequency of the oscillator;
the voltage-controlled transmission gate 112a has a maximum impedance R1_max and a total impedance when it is fully closedR2<R1_max, the total impedance Rtotal is mainly determined by the fixed impedance R2, and the total impedance Rtotal takes a maximum value, thereby determining the lower limit frequency of the oscillator;
it can be seen that as long as appropriate values of the minimum impedance r1_min and the fixed impedance R2 are designed, the upper limit frequency and the lower limit frequency, particularly the lower limit frequency, of the oscillator can be finely designed, respectively, so that the actual frequency oscillation range can be more symmetrically distributed on both sides of the target center frequency.
Designing a differential voltage-controlled loop oscillator based on design indexes (the target center frequency is 10.9GHz, and the target upper limit frequency is 12 GHz), so as to obtain a traditional oscillator structure comprising a 3-level single-order substructure 110 and a brand new oscillator structure recorded in the embodiment, as shown in fig. 4 and 3 respectively; in the brand new oscillator structure, the resistance determining module 112b is implemented by adopting a normally-open transmission gate, and the width-to-length ratio of the MOS device in the voltage-controlled transmission gate is 4.5 times that of the MOS device in the normally-open transmission gate, namely R2/R1_min is approximately equal to 4.5. Simulation verification is carried out on the traditional oscillator structure and the brand new oscillator structure, and the simulation verification is concretely as follows:
simulation verification of the upper limit frequency is performed on the conventional oscillator structure shown in fig. 4 and the completely new oscillator structure shown in fig. 3, wherein the simulation conditions are normal temperature typical process angles, vd1=vd2=vd3=vd=0.6v, vc=0.6v, vcn=vd-vc=0v; fig. 5 shows an upper limit frequency simulation waveform corresponding to the conventional oscillator structure, where the upper limit frequency freq_vout 1_high=11.95 GHz of the conventional oscillator structure; as shown in fig. 6, the upper limit frequency simulation waveform corresponding to the completely new oscillator structure shows that the upper limit frequency freq_vout 2_high=12.25 GHz of the completely new oscillator structure.
Simulation verification of the lower limit frequency is performed on the conventional oscillator structure shown in fig. 4 and the completely new oscillator structure shown in fig. 3, wherein the simulation conditions are normal temperature typical process angles, vd1=vd2=vd3=vd=0.6v, vc=0.45V, vcn=vd-vc=0.15V; the lower limit frequency simulation waveform corresponding to the conventional oscillator structure is shown in fig. 7, and it can be seen that the lower limit frequency freq_vout 1_low=6.30 GHz of the conventional oscillator structure; as shown in fig. 8, the lower limit frequency simulation waveform corresponding to the completely new oscillator structure shows that the lower limit frequency freq_vout 2_low=9.62 GHz of the completely new oscillator structure.
Correspondingly, the actual center frequency of the traditional oscillator structure is 9.125GHz, and the actual center frequency of the completely new oscillator structure is 10.935GHz.
It can be seen that, in the brand new oscillator structure of this embodiment, the upper limit frequency is basically kept at about 12GHz, and the center frequency is adjusted by adjusting the lower limit frequency, so that the center frequency is basically kept at about 10.9GHz, and the actual oscillation frequency range is more symmetrically distributed on both sides of the target center frequency; compared with the traditional oscillator structure, the novel oscillator structure of the embodiment meets design indexes better.
Example two
As shown in fig. 9, the present embodiment provides an electronic circuit including the differential voltage-controlled loop oscillator 100 according to the first embodiment. As an alternative, the electronic circuit is a phase-locked loop circuit; of course, the phase-locked loop circuit may also include other functional devices, such as a phase detector, a filter, a frequency divider, and the like.
Taking the phase-locked loop circuit as an example, the phase-locked loop circuit includes a differential voltage-controlled loop oscillator 100, a phase detector 200, a filter 300 and a frequency divider 400, wherein:
the phase detector 200 receives the reference signal and the feedback signal for converting a phase difference between the reference signal and the feedback signal into an electrical quantity, such as a voltage or an current;
the filter 300 is connected to the output end of the phase detector 200, and is used for filtering the electric quantity;
the differential voltage-controlled loop oscillator 100 is connected to the output end of the filter 300, and uses the filtered electric quantity as the NMOS gate control voltage vc of the voltage-controlled transmission gate 112a in the single-stage substructure 110 thereof, so as to generate an oscillating signal with a specific frequency according to the electric quantity;
the frequency divider 400 is connected to the output terminal of the differential voltage-controlled loop oscillator 100, and is configured to divide the oscillating signal to generate a feedback signal.
In summary, according to the differential voltage-controlled loop oscillator, the frequency adjusting method and the electronic circuit, the fixed impedance modules are connected in parallel at two ends of the voltage-controlled transmission gate in each single-order substructure, and the lower limit frequency of the oscillator is adjusted by using the value of the fixed impedance modules, so that the center frequency is adjusted, the actual oscillation frequency range of the oscillator is distributed on two sides of the target center frequency more symmetrically, and the problem that the lower limit frequency cannot be considered when the upper limit frequency is adjusted by the traditional oscillator structure is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The differential voltage-controlled loop oscillator is characterized by comprising M single-order substructures, wherein the single-order substructures are connected end to form an oscillation loop, and M is an odd number greater than or equal to 3;
the single-order substructure comprises an inverter unit and a transmission gate unit, wherein the transmission gate unit is connected with the output end of the inverter unit; wherein,
the transmission gate unit comprises a voltage-controlled transmission gate and a resistance-fixing module which are connected in parallel, wherein the voltage-controlled transmission gate is used for adjusting the upper limit frequency of the differential voltage-controlled loop oscillator, and the resistance-fixing module is used for adjusting the lower limit frequency of the differential voltage-controlled loop oscillator.
2. The differential voltage-controlled loop oscillator of claim 1, wherein the voltage-controlled transmission gate comprises a first NMOS tube and a first PMOS tube, the first NMOS tube and the first PMOS tube are connected in parallel, and gates of the first NMOS tube and the first PMOS tube are connected with a set of differential control signals; wherein the voltage controlled transmission gate has a minimum impedance and a maximum impedance, and the value of the upper limit frequency is adjusted by the value of the minimum impedance.
3. The differential voltage controlled loop oscillator of claim 2, wherein the number of voltage controlled transmission gates is 1 or more; when the number of the voltage-controlled transmission gates is greater than 1, the voltage-controlled transmission gates are connected in parallel, and the parallel structure has the minimum impedance and the maximum impedance.
4. A differential voltage controlled loop oscillator according to any of claims 1-3, characterized in that the resistance-determining module is implemented with a normally open transmission gate, a resistor series-parallel structure or a resistor-capacitor series-parallel structure, the value of the fixed impedance of the resistance-determining module is larger than the value of the minimum impedance of the voltage controlled transmission gate and smaller than the value of the maximum impedance of the voltage controlled transmission gate, and the value of the lower limit frequency is adjusted by the value of the fixed impedance.
5. The differential voltage-controlled loop oscillator of claim 4, wherein the normally-on transmission gate comprises a second NMOS transistor and a second PMOS transistor, the second NMOS transistor and the second PMOS transistor are connected in parallel, a gate of the second NMOS transistor is connected to an on voltage, and a gate of the second PMOS transistor is connected to a ground reference.
6. The differential voltage controlled loop oscillator of claim 5, wherein the number of normally open transmission gates is 1 or more; when the number of the normally open transmission gates is greater than 1, the normally open transmission gates are connected in parallel, and the parallel structure has the fixed impedance.
7. The differential voltage controlled loop oscillator of claim 5, wherein the voltage controlled transmission gate is controlled to be turned on or off by a set of differential control signals, wherein a set of the differential control signals includes an NMOS gate control voltage and a PMOS gate control voltage, the PMOS gate control voltage being a difference voltage between the turn-on voltage and the NMOS gate control voltage.
8. An electronic circuit comprising a differential voltage controlled loop oscillator as claimed in any one of claims 1 to 7.
9. A method of frequency adjustment for a differential voltage controlled loop oscillator, the method comprising:
the two ends of the voltage-controlled transmission gate of each single-order substructure in the differential voltage-controlled loop oscillator are connected with a resistance-fixing module in parallel;
and adjusting the upper limit frequency of the differential voltage-controlled loop oscillator through the voltage-controlled transmission gate, and adjusting the lower limit frequency of the differential voltage-controlled loop oscillator through the resistance-fixing module.
10. The method of claim 9, wherein the voltage controlled transmission gate has a minimum impedance and a maximum impedance, and the fixed impedance block has a fixed impedance, wherein the fixed impedance of the fixed impedance block has a value that is greater than the value of the minimum impedance of the voltage controlled transmission gate and less than the value of the maximum impedance of the voltage controlled transmission gate; the value of the upper limit frequency is adjusted by the value of the minimum impedance, and the value of the lower limit frequency is adjusted by the value of the fixed impedance.
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| CN101501691A (en) * | 2006-08-09 | 2009-08-05 | 高通股份有限公司 | Circuit simulator parameter extraction using a configurable ring oscillator |
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| CN104242876A (en) * | 2013-03-15 | 2014-12-24 | 英特尔公司 | On-die trim-able passive components for high volume manufacturing |
| CN104285375A (en) * | 2012-03-19 | 2015-01-14 | 英特尔公司 | Self-biased oscillator |
| CN110830007A (en) * | 2018-08-14 | 2020-02-21 | 武汉芯泰科技有限公司 | Low-phase-noise broadband ring oscillator |
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| CN101501691A (en) * | 2006-08-09 | 2009-08-05 | 高通股份有限公司 | Circuit simulator parameter extraction using a configurable ring oscillator |
| CN101567678A (en) * | 2009-05-27 | 2009-10-28 | 清华大学 | Numerical control ring-shaped oscillator with adjustable grade |
| CN104285375A (en) * | 2012-03-19 | 2015-01-14 | 英特尔公司 | Self-biased oscillator |
| CN104242876A (en) * | 2013-03-15 | 2014-12-24 | 英特尔公司 | On-die trim-able passive components for high volume manufacturing |
| CN110830007A (en) * | 2018-08-14 | 2020-02-21 | 武汉芯泰科技有限公司 | Low-phase-noise broadband ring oscillator |
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