CN117059572A - Wafer packaging and cutting method and chip package - Google Patents

Wafer packaging and cutting method and chip package Download PDF

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Publication number
CN117059572A
CN117059572A CN202310922621.4A CN202310922621A CN117059572A CN 117059572 A CN117059572 A CN 117059572A CN 202310922621 A CN202310922621 A CN 202310922621A CN 117059572 A CN117059572 A CN 117059572A
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CN
China
Prior art keywords
wafer
substrate layer
groove
cutting
package
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Pending
Application number
CN202310922621.4A
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Chinese (zh)
Inventor
刘磊
胡津津
王利国
陈瑞田
张强波
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Sky Chip Interconnection Technology Co Ltd
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Sky Chip Interconnection Technology Co Ltd
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Priority to CN202310922621.4A priority Critical patent/CN117059572A/en
Publication of CN117059572A publication Critical patent/CN117059572A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

The application discloses a packaging and cutting method of a wafer and a chip packaging body. The packaging method comprises the following steps: manufacturing a cutting channel, and forming a blind groove on one surface of the substrate layer with the crystal grains; sticking a protective film, and thinning the substrate layer to enable the blind groove to be a through groove; sticking a cutting film on one surface of a substrate layer of a wafer, and removing the protective film; to leak out the grains; carrying out plastic package on the wafer, and enabling the plastic package material to cover the crystal grains and extend to cover the groove walls of the through grooves; cutting along the through groove after plastic packaging to obtain the chip packaging body. According to the method, when the cutting channels are manufactured to cut each grain, the grains are still connected into a whole through the cutting film, the plastic package material not only covers the grains during plastic package, but also fills the through grooves, after the plastic package material in the through grooves is cut, the surface of the substrate layer is covered by the plastic package material, the side face of the substrate layer of the obtained chip package can be effectively protected, the risk that the subsequent flow process bumps the side face of the substrate layer by mistake is avoided, and the product reliability of the chip package is higher.

Description

Wafer packaging and cutting method and chip package
Technical Field
The present application relates to the field of semiconductor processing technology, and in particular, to a wafer packaging and dicing method and a chip package.
Background
The wafer comprises a plurality of crystal grains, the packaging of the existing wafer product is that a silicon surface on the back of the wafer is cut after an adhesive film is arranged on the silicon surface, the siliceous side surface of the obtained chip product is completely exposed, the risk of mistakenly touching the siliceous side surface exists during the later chip sorting and surface mounting processes, and the silicon is fragile, so that scraps and cracks are easy to generate during collision, and the reliability of the chip product is low or even fails.
Disclosure of Invention
The application mainly solves the technical problem of providing a wafer packaging and cutting method and a chip packaging body so as to avoid the problem that the side surface of a base layer is exposed after the wafer packaging and cutting, and the reliability of a product is not high.
In order to solve the above technical problems, a first technical solution adopted by the present application is to provide a method for dicing a wafer package, the method comprising: obtaining a wafer, wherein the wafer comprises a substrate layer and a plurality of crystal grains positioned on the substrate layer; making cutting paths between adjacent crystal grains so as to form blind grooves on one surface of the substrate layer with the crystal grains; attaching a protective film on one surface of the wafer with the crystal grains, and thinning the substrate layer to enable the blind groove to be a through groove; sticking a cutting film on one surface of the substrate layer of the wafer, and removing the protective film; to leak out the grains; carrying out plastic package on the wafer, and enabling a plastic package material to cover the crystal grains and extend to cover the groove walls of the through grooves; and cutting along the through groove after plastic packaging to obtain the chip packaging body.
In one possible embodiment, the step of making a scribe line between adjacent dies specifically includes: coating photoresist on one surface of the wafer with the crystal grains, and exposing and developing the photoresist to remove the photoresist in a preset area; wherein the preset area is positioned between two adjacent crystal grains; and performing dry etching treatment by using plasma so as to etch and form the blind groove in the preset area.
In a possible implementation manner, a metal layer and a dielectric layer are further included between adjacent crystal grains, and the metal layer and the dielectric layer are sequentially stacked on the substrate layer; the dry etching treatment comprises the following steps: and sequentially etching the dielectric layer, the metal layer and the substrate layer.
In one possible implementation manner, the step of thinning the substrate layer to make the blind groove become a through groove specifically includes: and grinding the surface of the substrate layer, which is opposite to the crystal grains, so that the blind grooves become through grooves.
In one possible implementation manner, the dicing film is a plastic material film, and after the step of attaching the dicing film to one surface of the substrate layer of the wafer and removing the protective film, the method further includes: and performing film expansion treatment on the cutting film so as to increase the opening size of the through groove.
In one possible embodiment, the opening size of the through groove is greater than 80 microns after the film expansion treatment.
In one possible implementation manner, the step of performing plastic packaging on the wafer, and enabling the plastic packaging material to cover the crystal grains and extend to cover the groove walls of the through grooves specifically includes: covering a plastic package material on one surface of the wafer with the crystal grains, and filling the through grooves with the plastic package material; solidifying the plastic packaging material to form a plastic packaging medium; cutting the region of the plastic package medium corresponding to the through groove, and covering the groove wall of the through groove with the plastic package medium.
In one possible embodiment, the thickness of the molding medium on the walls of the through-grooves is controlled to be greater than 10 micrometers.
In one possible embodiment, the substrate layer is a siliceous layer.
In order to solve the above technical problems, a second technical solution adopted by the present application is to provide a chip package. The chip package is processed by the above-described package dicing method of the wafer.
The beneficial effects of the application are as follows: in contrast to the prior art, the present application provides a method for dicing a wafer and a chip package, the method for dicing a wafer includes: obtaining a wafer, wherein the wafer comprises a substrate layer and a plurality of crystal grains positioned on the substrate layer; making cutting paths between adjacent grains so as to form blind grooves on one surface of the substrate layer with the grains; sticking a protective film on the surface of the wafer with the crystal grains, and thinning the substrate layer to enable the blind groove to be a through groove; sticking a cutting film on one surface of a substrate layer of a wafer, and removing the protective film; to leak out the grains; carrying out plastic package on the wafer, and enabling the plastic package material to cover the crystal grains and extend to cover the groove walls of the through grooves; cutting along the through groove after plastic packaging to obtain the chip packaging body. According to the method, when the cutting channels are manufactured to cut each grain, the grains are still connected into a whole through the cutting film, the plastic package material not only covers the grains during plastic package, but also fills the through grooves, after the plastic package material in the through grooves is cut, the surface of the substrate layer is covered by the plastic package material, the side face of the substrate layer of the obtained chip package can be effectively protected, the risk that the subsequent flow process bumps the side face of the substrate layer by mistake is avoided, and the product reliability of the chip package is higher.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an embodiment of a method for dicing a wafer according to the present application;
FIG. 2 is a flowchart of an embodiment of fabricating a scribe line in S12 of FIG. 1;
FIG. 3 is a flowchart of the step S15 of FIG. 1 for performing plastic packaging on a wafer according to an embodiment;
FIG. 4A is a schematic cross-sectional view of the wafer in S11 of FIG. 1;
FIG. 4B is a schematic diagram of the wafer structure after step S121;
FIG. 4C is a schematic diagram of the wafer structure after the step S122;
FIG. 4D is a schematic view of the wafer structure after step S13;
FIG. 4E is a schematic diagram of the wafer structure after step S14;
FIG. 4F is a schematic view of a wafer structure after a film expansion process;
FIG. 4G is a schematic diagram of the wafer structure after step S151;
fig. 4H is a schematic diagram of the wafer structure after step S153.
100 parts of a wafer; 10. a substrate layer; 20. a crystal grain; 30. a photoresist; 40. cutting the channel; 50. a metal layer; 60. a dielectric layer; 70. a protective film; 80. cutting the film; 90. and (5) plastic packaging material.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The packaging and cutting of the existing wafer product are carried out, after the back adhesive film is arranged on the back substrate layer of the wafer, the side face of the substrate layer of the obtained chip product is completely exposed, the side face of the substrate layer is not packaged and coated, scraps and cracks are easily generated by mistaken touch, and the reliability of the product is low.
Based on the above problems, the application provides a packaging and cutting method for a wafer and a chip package, which can effectively solve the above problems by forming a blind groove and a through groove, and cutting after a plastic package material covers the groove wall of the groove.
The following describes a wafer package dicing method and a chip package according to the present application in detail with reference to the drawings and the embodiments.
Referring to fig. 1, fig. 1 is a flow chart illustrating an embodiment of a method for dicing a wafer according to the present application. In one embodiment, the method for dicing a wafer package may include:
s11: a wafer is obtained, the wafer comprising a substrate layer and a plurality of dies located on the substrate layer.
Please refer to fig. 4A in combination. Fig. 4A is a schematic cross-sectional view of the wafer in S11 of fig. 1.
The substrate layer 10 may be a semiconductor substrate or a semiconductor-on-insulator substrate in particular. The semiconductor material of the semiconductor substrate and the semiconductor-on-insulator substrate may comprise an elemental semiconductor or an alloy semiconductor. For example, the elemental semiconductor may include silicon or germanium, etc., and the alloy semiconductor may include silicon-germanium alloy, silicon carbide alloy, silicon-germanium-carbon alloy, etc. In this embodiment, the substrate layer 10 is a semiconductor substrate, specifically a siliceous layer substrate. In other embodiments, the kind of the substrate layer 10 is not particularly limited.
The substrate layer 10 is formed with a plurality of dies 20, and the dies 20 may include active devices and passive devices to form an integrated circuit. In some embodiments, the integrated circuits in the plurality of dies 20 may be the same as or different from each other. In addition, the shape of the die 20 on the substrate layer 10 may be circular, square, irregular, or the like, and is not particularly limited. After the wafer 100 is subjected to the package dicing process, a single chip package can be obtained.
S12: dicing streets are formed between adjacent dies to form blind trenches in the side of the substrate layer having the dies.
This step produces a dicing street 40 having a width dimension of at least 60 microns. Any reasonable number, such as 60 microns, 61 microns, 64 microns, etc., is not particularly limited. The dicing streets 40 are made to pre-dice the dies 20 on the substrate layer 10 into groups. Wherein, when making the scribe line 40, a blind groove is formed on the substrate layer 10 to incompletely cut off the substrate layer 10, so that the substrate layer 10 can still connect and position each die 20, and each die 20 can still be integrated, thereby facilitating the subsequent integral plastic packaging.
Referring to fig. 2 in combination, fig. 2 is a flow chart of an embodiment of making a scribe line in S12 of fig. 1. In one embodiment, the step of forming scribe lines 40 between adjacent dies 20 includes:
s121: coating photoresist on one surface of the wafer with the crystal grains, and exposing and developing the photoresist to remove the photoresist in a preset area; the preset area is located between two adjacent crystal grains.
Referring to fig. 4B in combination, fig. 4B is a schematic view of the wafer structure after step S121.
Specifically, the photoresist 30 is coated on one surface of the die 20 of the wafer 100, which is used to protect the microstructure of the die 20 when the scribe line 40 is formed, so as to prevent impurities from falling on the die 20 and affecting the normal function of the die 20. After the photoresist 30 is coated, the photoresist 30 is further cured, which may be specifically performed by baking the wafer 100 coated with the photoresist 30 in an oven.
The preset area is an area where the dicing street 40 needs to be formed. The exposure process is specifically performed by irradiating the photoresist 30 with ultraviolet light, and in this embodiment, the photoresist 30 is specifically a negative photoresist 30. The negative photoresist 30 can absorb light energy to decompose into free radicals under the irradiation of ultraviolet light, and the free radicals trigger the photosensitive polymerization monomer to perform polymerization crosslinking reaction, so that a macromolecular structure insoluble in weak alkaline water is formed after the reaction, and the non-exposure part can be dissolved by the developing solution. When the ultraviolet light is irradiated, the ultraviolet light is specifically irradiated to a non-preset region of the photoresist 30, so that the photoresist 30 of the preset region can be dissolved at the time of development processing after the exposure processing.
S122: and performing dry etching treatment by using plasma to etch and form blind grooves in the preset area.
Referring to fig. 4C in combination, fig. 4C is a schematic view of the wafer structure after step S122.
Specifically, the principle of dry etching by plasma is to etch a substance to be etched by depositing a material that can react with the substance to be etched to form a volatile substance. Which has the advantage of facilitating control of etching efficiency. And the blind groove is formed on the basal layer by dry etching with plasma, so that the wall of the blind groove is subjected to nondestructive etching, mechanical stress of the wall of the blind groove is avoided, and the reliability is higher.
In a specific embodiment, the metal layer 50 and the dielectric layer 60 are further included between the adjacent grains 20, and the metal layer 50 and the dielectric layer 60 are sequentially stacked on the substrate layer 10. Specifically, metal layer 50 is electrically conductive to form an integrated circuit between die 20. Dielectric layer 60 is used to protect metal layer 50. The dry etching process comprises the following steps: the dielectric layer 60 etch, the metal layer 50 etch, and the substrate layer 10 etch are performed sequentially. The etching of the different layers is performed using different plasmas.
Wherein, after coating the photoresist 30 to complete the dicing streets 40, the photoresist 30 needs to be removed.
S13: and sticking a protective film on the surface of the wafer with the crystal grains, and thinning the substrate layer to enable the blind groove to be a through groove.
Referring to fig. 4D in combination, fig. 4D is a schematic view of the wafer structure after step S13.
Specifically, the protective film 70 is used to protect the die 20 during the thinning process, and is also used to keep each die 20 as a whole through the protective film 70 after the substrate layer 10 is thinned to make the blind trench a through trench. In one embodiment, the step of thinning the substrate layer 10 to make the blind trench a through trench specifically includes: the side of the substrate layer 10 facing away from the die 20 is polished to make the blind trenches through.
S14: and sticking a cutting film on one surface of the substrate layer of the wafer, and removing the protective film. To leak out the die.
Referring to fig. 4E in combination, fig. 4E is a schematic view of the wafer structure after step S14.
The protective film 70 covers the die 20 surface of the wafer 100, in order to perform plastic packaging on the die 20 on the wafer 100, the protective film 70 needs to be removed first, and in order to make each die 20 still be an integral, convenient and integral plastic packaging, a dicing film 80 is stuck on one surface of the substrate layer 10 of the wafer 100 first, then the protective film 70 is removed, and the step of removing the protective film 70 can ensure that the process of leaking the die 20 from the wafer 100 is always kept as an integral, so that the subsequent integral plastic packaging on the wafer 100 is convenient.
Still further, in a preferred embodiment, the dicing film 80 is a plastic material film. After the step of attaching the dicing film 80 to the substrate layer 10 of the wafer 100 and removing the protective film 70, the method further comprises: the dicing film 80 is subjected to a film-enlarging process so that the opening size of the through groove increases. Specifically, referring to fig. 4F in combination, fig. 4F is a schematic view of a wafer structure after the film expansion process. This step expands the through-slot cut 40 to a larger size to facilitate the subsequent overall plastic packaging to also plastic package the through-slot, and after the plastic package cut to enable the thickness of the molding compound 90 on the wall of the through-slot to reach a predetermined thickness to better protect the side of the substrate layer. The components of the dicing film 80 may include one or more of polyurethane, diol, and isocyanate, and the specific components are not limited. In a preferred embodiment, the opening size of the through-slot is greater than 80 microns after the film expansion process. The opening size of the through groove can be specifically expanded to 80 micrometers, 85 micrometers, 90 micrometers, 95 micrometers and the like, and the specific size is not limited. The through groove is expanded to the size, and after the plastic package material 90 covers the groove wall of the through groove, the thickness of the plastic package material 90 on the groove wall of the through groove after the subsequent cutting can reach more than 10 micrometers.
S15: and (3) carrying out plastic package on the wafer, and enabling the plastic package material to cover the crystal grains and extend to cover the groove walls of the through grooves.
In the plastic packaging process, the surface of the wafer 100 with the die 20 is subjected to plastic packaging, so that the plastic packaging material 90 covers the die 20, and the die 20 is protected. In the plastic packaging of the existing wafer 100, only the surface and the back surface of the die 20 are subjected to plastic packaging protection, the side surface of the basal layer of the chip product obtained after cutting is completely exposed, and the risk of mistakenly touching the siliceous side surface exists in the later chip sorting and surface mounting processes. In the present embodiment, after the blind groove is formed by processing and then the through groove is formed, and after the expansion treatment is performed on the through groove, the plastic sealing material 90 is further covered on the groove wall of the through groove, and after the chip package is separated, the side surface of the base layer of the chip package is also covered by the plastic sealing material 90, so that the side surface of the base layer can be effectively protected.
Referring to fig. 3 in combination, fig. 3 is a flow chart illustrating an embodiment of performing plastic packaging on the wafer in S15 in fig. 1. In one embodiment, the step of molding the wafer 100, and covering the die 20 with the molding compound 90 and extending the walls of the through-slot specifically includes:
s151: and covering the surface of the wafer with the crystal grains with a plastic package material, and filling the through grooves with the plastic package material.
Referring to fig. 4G in combination, fig. 4G is a schematic view of the wafer structure after step S151.
Specifically, the molding compound 90 may specifically include one or more of epoxy resins, polyimides, bismaleimide triazines (BismaleimideTriazine, BT), and ceramic bases. The specific components thereof are not limited.
S152: and curing the plastic packaging material to form a plastic packaging medium.
The wafer 100 is placed into a bake oven for baking to cure the molding compound 90 to form a molding medium that not only encapsulates the die 20 on the wafer 100, but also fills the through-slots to encapsulate the sidewalls of the substrate layer 10. Wherein the baking temperature is controlled to be 90 degrees to 100 degrees, such as 90 degrees, 93 degrees, 96 degrees, 100 degrees, etc., and the baking time period is controlled to be 80 minutes to 125 minutes, such as 80 minutes, 90 minutes, 100 minutes, 110 minutes, 125 minutes, etc. The specific baking temperature and baking time period are not limited.
S153: cutting the region of the plastic packaging medium corresponding to the through groove, and covering the groove wall of the through groove by the plastic packaging medium.
Referring to fig. 4H in combination, fig. 4H is a schematic view of the wafer structure after step S153.
Cutting the plastic package medium in the through groove, cutting the plastic package medium, conveniently separating each crystal grain 20, and ensuring that the groove wall of the through groove is covered by the plastic package medium after cutting. The cutting method may specifically be cutting by laser or cutting by a milling groove machine, and the cutting mode is not particularly limited. The thickness of the plastic package medium on the wall of the through groove after cutting is only required to be more than 10 micrometers. For example, the thickness of the plastic package medium on the wall of the through groove after cutting is 11 microns, 12 microns, 13 microns, 14 microns, etc.
S16: and dividing the cutting film along the through grooves to obtain the chip packaging body.
After step S15, the molding compound 90 has covered the die 20 and the side surfaces of the substrate layer 10, and each die 20 is integrally connected by the dicing film 80. By cutting the dicing film 80, each chip package can be obtained, and the side surface of the substrate layer 10 of each chip package is covered and protected by the plastic sealing material 90.
Unlike the prior art, the application provides a wafer packaging and cutting method. According to the packaging and cutting method of the wafer, when the crystal grains are cut off through the manufacturing cutting channels, the crystal grains are still connected into a whole through the cutting films, the cutting films are plastic material films, the size of each through groove is enlarged through the film expansion technology, the plastic packaging material not only covers the crystal grains during plastic packaging, but also fills the through grooves, after the plastic packaging material in the through grooves is cut, the surface of the substrate layer is covered by the plastic packaging material, the side face of the substrate layer of the obtained chip packaging body can be effectively protected, the risk that the subsequent flow process mistakenly touches the side face of the substrate layer is avoided, and the product reliability of the chip packaging body is higher.
Correspondingly, the application also provides a chip package body which is processed by the packaging and cutting method of the wafer.
The foregoing description is only illustrative of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent principles of the present application or direct or indirect application in other related arts are included in the scope of the present application.

Claims (10)

1. The method for cutting the wafer package is characterized by comprising the following steps:
obtaining a wafer, wherein the wafer comprises a substrate layer and a plurality of crystal grains positioned on the substrate layer;
making cutting paths between adjacent crystal grains so as to form blind grooves on one surface of the substrate layer with the crystal grains;
attaching a protective film on one surface of the wafer with the crystal grains, and thinning the substrate layer to enable the blind groove to be a through groove;
sticking a cutting film on one surface of the substrate layer of the wafer, and removing the protective film; to leak out the grains;
carrying out plastic package on the wafer, and enabling a plastic package material to cover the crystal grains and extend to cover the groove walls of the through grooves;
and cutting along the through groove after plastic packaging to obtain the chip packaging body.
2. The package dicing method of claim 1, wherein the step of making dicing streets between adjacent ones of the dies, specifically comprises:
coating photoresist on one surface of the wafer with the crystal grains, and exposing and developing the photoresist to remove the photoresist in a preset area; wherein the preset area is positioned between two adjacent crystal grains;
and performing dry etching treatment by using plasma so as to etch and form the blind groove in the preset area.
3. The package dicing method according to claim 2, wherein,
a metal layer and a dielectric layer are further arranged between the adjacent crystal grains, and the metal layer and the dielectric layer are sequentially stacked on the substrate layer;
the dry etching treatment comprises the following steps: and sequentially etching the dielectric layer, the metal layer and the substrate layer.
4. The package dicing method of claim 1, wherein the step of thinning the substrate layer to make the blind trench a through trench, specifically comprises:
and grinding the surface of the substrate layer, which is opposite to the crystal grains, so that the blind grooves become through grooves.
5. The package dicing method according to claim 1, wherein,
the cutting film is a plastic material film,
and after the step of sticking a cutting film on one surface of the substrate layer of the wafer and removing the protective film, the method further comprises the following steps:
and performing film expansion treatment on the cutting film so as to increase the opening size of the through groove.
6. The package dicing method of claim 5, wherein,
after the film expansion treatment, the opening size of the through groove is larger than 80 microns.
7. The package dicing method of claim 1, wherein the step of molding the wafer and covering the die with the molding compound and extending the groove walls covering the through grooves specifically comprises:
covering a plastic package material on one surface of the wafer with the crystal grains, and filling the through grooves with the plastic package material;
solidifying the plastic packaging material to form a plastic packaging medium;
cutting the region of the plastic package medium corresponding to the through groove, and covering the groove wall of the through groove with the plastic package medium.
8. The package dicing method of claim 7, wherein,
and controlling the thickness of the plastic package medium on the wall of the through groove to be more than 10 micrometers.
9. The package dicing method according to claim 1, wherein,
the substrate layer is a siliceous layer.
10. A chip package processed by the method of dicing a wafer according to any one of claims 1 to 9.
CN202310922621.4A 2023-07-25 2023-07-25 Wafer packaging and cutting method and chip package Pending CN117059572A (en)

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