CN117038602B - Semiconductor device stacking and packaging structure - Google Patents
Semiconductor device stacking and packaging structure Download PDFInfo
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- CN117038602B CN117038602B CN202310985936.3A CN202310985936A CN117038602B CN 117038602 B CN117038602 B CN 117038602B CN 202310985936 A CN202310985936 A CN 202310985936A CN 117038602 B CN117038602 B CN 117038602B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052802 copper Inorganic materials 0.000 claims abstract description 37
- 239000010949 copper Substances 0.000 claims abstract description 37
- 238000005538 encapsulation Methods 0.000 claims abstract 6
- 230000006978 adaptation Effects 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 26
- 238000001125 extrusion Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 239000000428 dust Substances 0.000 description 27
- 230000017525 heat dissipation Effects 0.000 description 23
- 238000010586 diagram Methods 0.000 description 5
- 230000002035 prolonged effect Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a semiconductor device stacking and packaging structure; including base plate, first chip, the second chip, encapsulation casing, support frame and radiator unit, radiator unit includes two spacing, two sets of locating parts, the mounting bracket, two radiator fan, two support frames, first copper, second copper and many heat conduction posts, two sets of locating parts respectively with corresponding spacing looks adaptation, the mounting bracket all runs through the louvre that corresponds respectively with two locating part fixed connection, first copper and mount fixed connection, the second copper is connected with the second chip, and first copper and second copper are connected with the heat conduction post that corresponds respectively, two support frames all with encapsulation casing fixed connection, every radiator fan sets up respectively in the support frame that corresponds, the realization can improve the radiating effect of semiconductor chip in the operation process, avoid heat to pile up, the life-span of using semiconductor chip has been increased.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a stacked package structure of a semiconductor device.
Background
From the structural aspect of SIP packaging, mainly the arrangement of multiple functional chips and the compatibility and layout of passive components are provided. From the current mature product structure, the chip and the passive element are mainly in a tiled structure, so that the whole size of the element is increased, or a substrate embedding process of the passive element is selected, the processing period and cost of the substrate are increased, and the yield of the substrate is poor. The chip adopts a three-dimensional stacking structure, and due to the technological influence of the patch and the bonding wire, when the size of the upper chip is far larger than that of the lower chip, the chip cannot be stacked.
In the prior art patent CN206789542U discloses a semiconductor device stacking and packaging structure, when in use, since the placement positions of the first chip and the passive element are provided through the bottom structure, the first chip and the passive element can be stably placed in the bottom structure, so that the position structures of the first chip and the passive element can be consolidated, and the second chip is mounted on the upper surface of the bottom structure, so that the probability of contact between the second chip and the first chip or the passive element can be effectively reduced, and then, the mutual influence between different chips can be reduced. Therefore, the structural stability of the lower-layer components in the system-in-package is improved.
However, in the above-described method, the heat of the semiconductor chip is not easily dissipated during the operation, and the heat is accumulated in the semiconductor chip, which may affect the service life of the semiconductor chip.
Disclosure of Invention
The invention aims to provide a semiconductor device stacking and packaging structure, which solves the problem that heat is not easy to dissipate in the operation process of a semiconductor chip, and the service life of the semiconductor chip can be influenced due to the fact that the heat is accumulated in the semiconductor chip.
In order to achieve the above object, the semiconductor device stacking and packaging structure comprises a substrate, a first chip, a second chip, a packaging shell, a supporting frame and a heat dissipation assembly, wherein the fixing frame is arranged above the substrate, the first chip is arranged in the fixing frame, the second chip is arranged above the supporting frame, the packaging shell is arranged above the substrate, the heat dissipation assembly comprises two limiting frames, two groups of limiting pieces, a mounting frame, two heat dissipation fans, two supporting frames, a first copper plate, a second copper plate and a plurality of heat conduction columns, the packaging shell is provided with a plurality of heat dissipation holes, the two limiting frames are symmetrically arranged on the outer wall of the packaging shell, the two groups of limiting pieces are respectively matched with the corresponding limiting frames, the mounting frame is fixedly connected with the two limiting pieces, the plurality of heat conduction columns are respectively connected with the mounting frame in a penetrating mode through the corresponding heat dissipation holes, the first copper plate is fixedly connected with the fixing frame, the first chip is arranged above the first chip, the second copper plate is correspondingly connected with the second copper plate, the packaging shell is respectively connected with the two copper plates, and the two copper plates are respectively arranged in the packaging shell.
The limiting piece comprises a clamping block, a limiting rod and a limiting spring, wherein the limiting rod is fixedly connected with the packaging shell and is positioned on the outer wall of the packaging shell, the clamping block is slidably connected with the limiting rod and sleeved on the outer wall of the limiting rod, and two ends of the limiting spring are respectively fixedly connected with the mounting frame and the clamping block and sleeved on the outer wall of the limiting rod.
The limiting piece further comprises a limiting block, wherein the limiting block is fixedly connected with the limiting rod and located at the other end, far away from the packaging shell, of the limiting rod.
The semiconductor device stacking and packaging structure further comprises two groups of fixing components, wherein the fixing frame is provided with two grooves, and the two groups of fixing components are symmetrically arranged above the substrate and are respectively matched with the corresponding grooves.
The fixing assembly comprises a pull rod, a supporting spring, an embedded block and a fixing seat, wherein the fixing seat is fixedly connected with the base plate and is located above the base plate, the pull rod is in sliding connection with the base plate and penetrates through the base plate, the embedded block is fixedly connected with the pull rod and is matched with the groove, and two ends of the supporting spring are respectively fixedly connected with the fixing seat and the embedded block and are sleeved on the outer wall of the pull rod.
The fixing assembly comprises an extrusion arc block, wherein the extrusion arc block is fixedly connected with the embedded block and is positioned on the outer wall of the embedded block.
According to the stacked packaging structure of the semiconductor device, when the stacked packaging structure is used, the mounting frame is fixed on the packaging shell through the matching of the two groups of limiting pieces and the two limiting pieces, when the stacked packaging structure is used, the first copper plate and the second copper plate respectively guide heat generated by operation into the heat conducting columns, the heat conducting columns transfer the heat of the first chip and the heat of the second chip into air for heat dissipation, meanwhile, the heat dissipating fans in the supporting frame are started respectively, the heat dissipating fans can send cold air into the packaging shell, the cold air exchanges heat in the packaging shell and is discharged through the heat dissipating holes, so that the heat generated by the first chip and the second chip is quickly exchanged with the outside, the heat dissipation efficiency is improved, the heat dissipation effect of the semiconductor chip in the operation process is improved, the heat accumulation is avoided, and the service life of the semiconductor chip is prolonged.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a first embodiment of the present invention.
Fig. 2 is a schematic structural view of a second embodiment of the present invention.
Fig. 3 is an enlarged view of the partial structure at a of fig. 2 according to the present invention.
Fig. 4 is a schematic structural view of a third embodiment of the present invention.
Fig. 5 is an enlarged view of the partial structure at B of fig. 4 according to the present invention.
101-Base plate, 102-first chip, 103-second chip, 104-package shell, 105-fixing frame, 106-limit frame, 107-mounting frame, 108-radiator fan, 109-first copper plate, 110-second copper plate, 111-heat conduction column, 112-limit block, 113-clamping block, 114-limit rod, 115-limit spring, 116-heat dissipation hole, 117-support frame, 201-pull rod, 202-supporting spring, 203-jogged block, 204-fixing seat, 205-extrusion arc block, 206-groove, 301-limit bolt, 302-air inlet grille, 303-dust screen and 304-pull block.
Detailed Description
The first embodiment is:
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment. The invention provides a semiconductor device stacking and packaging structure, which comprises a substrate 101, a first chip 102, a second chip 103, a packaging shell 104, a fixing frame 105 and a heat dissipation assembly, wherein the heat dissipation assembly comprises two limiting frames 106, two groups of limiting pieces, a mounting frame 107, two heat dissipation fans 108, two supporting frames 117, a first copper plate 109, a second copper plate 110 and a plurality of heat conduction columns 111, and the limiting pieces comprise clamping blocks 113, limiting rods 114, limiting springs 115 and limiting blocks 112;
For this embodiment, the fixing frame 105 is disposed above the substrate 101, the first chip 102 is disposed in the fixing frame 105, the second chip 103 is disposed above the supporting frame 105, the package housing 104 is disposed above the substrate 101, the supporting frame 105 is used to provide a placement position for the first chip 102, and the second chip 103 is mounted on an upper surface of the supporting frame 105, so that a probability of contact between the second chip 103 and the first chip 102 can be effectively reduced, and then, interactions among different chips can be reduced, thereby improving structural stability of lower-layer components in the system-in-package.
Wherein the package housing 104 has a plurality of heat dissipation holes 116, two limiting frames 106 are symmetrically disposed on an outer wall of the package housing 104, two groups of limiting members are respectively adapted to the corresponding limiting frames 106, the mounting frame 107 is fixedly connected with the two limiting members, a plurality of heat conduction columns 111 are fixedly connected with the mounting frame 107 and respectively penetrate through the corresponding heat dissipation holes 116, the first copper plate 109 is fixedly connected with the fixing frame 105 and is disposed above the first chip 102, the second copper plate 110 is connected with the second chip 103, the first copper plate 109 and the second copper plate 110 are respectively connected with the corresponding heat conduction columns 111, the two supporting frames 117 are respectively fixedly connected with the package housing 104 and are symmetrically disposed on an outer wall of the package housing 104, each heat dissipation fan 108 is respectively disposed in the corresponding supporting frame 108, in use, the mounting frame 107 is fixed on the package housing 104 by matching two sets of the limiting members with two limiting frames 106, when the first chip 102 and the second chip 103 are in use, the first copper plate 109 and the second copper plate 110 respectively guide heat generated by operation into the heat conducting column 111, the heat conducting column 111 transfers the heat of the first chip 102 and the second chip 103 into the air for heat dissipation, meanwhile, the heat dissipating fans 108 in the supporting frame 117 are respectively started, the heat dissipating fans 108 can feed cold air into the package housing 104, the cold air exchanges heat in the package housing 104 and is discharged through the heat dissipating holes 116, so that the heat generated by the first chip 102 and the second chip 103 is quickly exchanged with the outside, the heat dissipation efficiency is improved, the heat dissipation effect of the semiconductor chip in the operation process can be improved, heat accumulation is avoided, and the service life of the semiconductor chip is prolonged.
Secondly, the stop lever 114 is fixedly connected with the packaging shell 104 and is located on the outer wall of the packaging shell 104, the clamping block 113 is slidably connected with the stop lever 114 and is sleeved on the outer wall of the stop lever 114, two ends of the stop spring 115 are respectively fixedly connected with the mounting frame 107 and the clamping block 113 and are sleeved on the outer wall of the stop lever 114, when the mounting frame 107 is fixed on the packaging shell 104, the heat conducting columns 111 are respectively penetrated through the packaging shell 104 correspondingly, so that the heat conducting columns 111 are respectively contacted with the first copper plate 109 and the second copper plate 110, and meanwhile, the pull rod 201 is pulled, and the mounting frame 107 is fixed above the packaging shell 104 through the stop spring 115 and the clamping block 113.
Meanwhile, the limiting block 112 is fixedly connected with the limiting rod 114 and is located at the other end of the limiting rod 114 far away from the packaging shell 104, the limiting block 112 limits the moving range of the limiting rod 114 on the mounting frame 107, and the limiting rod 114 is prevented from moving out of the mounting frame 107.
When the semiconductor packaging structure is used, each heat conducting column 111 correspondingly penetrates through the packaging shell 104, each heat conducting column 111 is respectively in contact with the first copper plate 109 and the second copper plate 110, meanwhile, the pull rod 201 is pulled, the mounting frame 107 is fixed above the packaging shell 104 through the limiting spring 115 and the clamping block 113, when the first chip 102 and the second chip 103 are used, heat generated by operation is respectively led into the heat conducting column 111 by the first copper plate 109 and the second copper plate 110, the heat conducting column 111 transfers the heat of the first chip 102 and the second chip 103 into air for heat dissipation, meanwhile, the heat dissipation fan 108 in the supporting frame 117 is started respectively, the heat dissipation fan 108 can feed cold air into the packaging shell 104, the cold air exchanges heat in the packaging shell 104 and is discharged through the heat dissipation holes 116, the heat generated by the first chip 102 and the second chip 103 is quickly exchanged with the semiconductor chip, the heat dissipation effect of the semiconductor packaging structure is improved, the heat dissipation effect of the semiconductor packaging structure is prolonged, and the service life of the semiconductor packaging structure is prolonged.
The second embodiment is:
on the basis of the first embodiment, please refer to fig. 2 and 3, wherein fig. 2 is a schematic structural diagram of the second embodiment, and fig. 3 is a partial enlarged structural diagram of fig. 2 at a. The invention provides a semiconductor device stacking and packaging structure, which also comprises two groups of fixing components, wherein the fixing components comprise a pull rod 201, a supporting spring 202, a jogging block 203, a fixing seat 204 and an extrusion arc block 205;
For this embodiment, the fixing frame 105 has two grooves 206, and the two fixing assemblies are symmetrically disposed above the substrate 101 and respectively adapted to the corresponding grooves 206, so that the fixing assemblies can facilitate the fixing frame 105 to be detached from the substrate 101, and facilitate the subsequent inspection or maintenance of the first chip 102.
The fixing base 204 is fixedly connected with the substrate 101 and is located above the substrate 101, the pull rod 201 is slidably connected with the substrate 101 and penetrates through the substrate 101, the embedded block 203 is fixedly connected with the pull rod 201 and is matched with the groove 206, two ends of the supporting spring 202 are respectively fixedly connected with the fixing base 204 and the embedded block 203 and are sleeved on the outer wall of the pull rod 201, when the first chip 102 below the fixing frame 105 is overhauled, the pull rod 201 drives the embedded block 203 to leave the groove 206 of the fixing frame 105 by respectively pulling the pull rod 201 outwards, at this time, the supporting spring 202 is compressed, so that the fixing frame 105 can be detached from the substrate 101, otherwise, the fixing frame 105 can be installed on the substrate 101, the fixing frame 105 can be detached from the substrate 101 conveniently, and the first chip 102 can be checked or maintained conveniently.
Next, the extrusion arc block 205 is fixedly connected with the fitting block 203 and is located on the outer wall of the fitting block 203, the extrusion arc block 205 has an arc surface, and the fitting block 203 enters the groove 206.
When the first chip 102 below the fixing frame 105 is overhauled, the pull rods 201 are pulled outwards respectively, the pull rods 201 drive the embedded blocks 203 to leave the grooves 206 of the fixing frame 105, the supporting springs 202 are compressed at the moment, so that the fixing frame 105 is detached from the substrate 101, otherwise, the fixing frame 105 can be installed on the substrate 101, the extruded arc blocks 205 are provided with cambered surfaces, the embedded blocks 203 can conveniently enter the grooves 206, and the fixing frame 105 can be conveniently detached from the substrate 101, so that the first chip 102 can be conveniently inspected or maintained later.
The third embodiment is:
On the basis of the second embodiment, please refer to fig. 4 and 5, wherein fig. 4 is a schematic structural diagram of the third embodiment, and fig. 5 is an enlarged partial structural diagram at B of fig. 4. The invention provides a semiconductor device stacking and packaging structure which also comprises a dustproof assembly, wherein the dustproof assembly comprises a plurality of limit bolts 301, an air inlet grille 302, a dustproof net 303 and a pull block 304;
To this concrete embodiment, dustproof subassembly with mounting bracket 107 fixed connection, and be located radiator fan 108's top, through dustproof subassembly can avoid the dust to pile up in the mounting bracket 107, avoid influencing the radiating effect.
Wherein, air inlet grille 302 with mounting bracket 107 fixed connection, and be located the top of radiator fan 108, dust screen 303 set up in the top of air inlet grille 302, every limit bolt 301 all runs through dust screen 303, and with mounting bracket 107 screw-thread fit, the heat passes through louvre 116 with heat conduction post 111 outwards transmits to the air, dust screen 303 passes through limit bolt 301 is fixed on the mounting bracket 107, dust screen 303 blocks the dust, avoids the dust to get into will in the mounting bracket 107 the louvre 116 blocks up, when the dust is too much on the dust screen 303 is found, through taking off limit bolt 301, and to dust screen 303 changes, guarantees the filter effect to the dust, realizes can avoiding the dust to pile up in the mounting bracket 107, avoids influencing the radiating effect.
Secondly, the pull block 304 is fixedly connected with the dust screen 303, and is located above the dust screen 303, and the dust screen 303 can be conveniently taken and placed through the pull block 304, so that the dust screen 303 can be conveniently taken and placed.
Heat passes through the louvre 116 with heat conduction post 111 outwards transmits to the air, the dust screen 303 passes through stop bolt 301 is fixed on the mounting bracket 107, the dust screen 303 dust blocks, avoids the dust to get into will in the mounting bracket 107 the louvre 116 blocks up, when finding dust screen 303 goes up the dust too much, through will stop bolt 301 takes off, through pull block 304 will dust screen 303 takes off, then right dust screen 303 changes, guarantees the filter effect to the dust, realizes can avoiding the dust to pile up in the mounting bracket 107, avoids influencing the radiating effect.
The above disclosure is only a preferred embodiment of the present invention, and it should be understood that the scope of the invention is not limited thereto, and those skilled in the art will appreciate that all or part of the procedures described above can be performed according to the equivalent changes of the claims, and still fall within the scope of the present invention.
Claims (6)
1. The semiconductor device stacking and packaging structure comprises a substrate, a first chip, a second chip, a packaging shell and a fixing frame, wherein the fixing frame is arranged above the substrate, the first chip is arranged in the fixing frame, the second chip is arranged above the fixing frame, the packaging shell is arranged above the substrate,
Still include radiating component, radiating component includes two spacing, two sets of locating parts, mounting bracket, two radiator fan, two support frames, first copper, second copper and many heat conduction posts, the encapsulation casing have a plurality of louvres, two the spacing symmetry set up in the outer wall of encapsulation casing, two sets of the locating parts respectively with corresponding spacing looks adaptation, the mounting bracket all with two locating part fixed connection, many the heat conduction post all with mounting bracket fixed connection to run through respectively corresponding louvre, first copper with mount fixed connection, and be located the top of first chip, the second copper with the second chip is connected, just first copper with the second copper is connected with corresponding heat conduction post respectively, two the support frames all with encapsulation casing fixed connection, and the symmetry set up in encapsulation casing's outer wall, every the fan sets up respectively in corresponding support frame.
2. The semiconductor device package-on-package structure of claim 1, wherein,
The limiting piece comprises a clamping block, a limiting rod and a limiting spring, wherein the limiting rod is fixedly connected with the packaging shell and is positioned on the outer wall of the packaging shell, the clamping block is slidably connected with the limiting rod and sleeved on the outer wall of the limiting rod, and two ends of the limiting spring are respectively fixedly connected with the mounting frame and the clamping block and sleeved on the outer wall of the limiting rod.
3. The semiconductor device package-on-package structure of claim 2, wherein,
The limiting piece further comprises a limiting block, wherein the limiting block is fixedly connected with the limiting rod and is located at the other end, far away from the packaging shell, of the limiting rod.
4. The semiconductor device stack package of claim 3,
The semiconductor device stacking and packaging structure further comprises two groups of fixing components, the fixing frame is provided with two grooves, and the two groups of fixing components are symmetrically arranged above the substrate and are respectively matched with the corresponding grooves.
5. The semiconductor device package-on-package structure of claim 4, wherein,
The fixing assembly comprises a pull rod, a supporting spring, an embedded block and a fixing seat, wherein the fixing seat is fixedly connected with the base plate and is positioned above the base plate, the pull rod is in sliding connection with the base plate and penetrates through the base plate, the embedded block is fixedly connected with the pull rod and is matched with the groove, and two ends of the supporting spring are respectively fixedly connected with the fixing seat and the embedded block and are sleeved on the outer wall of the pull rod.
6. The semiconductor device package-on-package structure of claim 5,
The fixing component comprises an extrusion arc block which is fixedly connected with the embedded block and is positioned on the outer wall of the embedded block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310985936.3A CN117038602B (en) | 2023-08-07 | 2023-08-07 | Semiconductor device stacking and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310985936.3A CN117038602B (en) | 2023-08-07 | 2023-08-07 | Semiconductor device stacking and packaging structure |
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| Publication Number | Publication Date |
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| CN117038602A CN117038602A (en) | 2023-11-10 |
| CN117038602B true CN117038602B (en) | 2024-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310985936.3A Active CN117038602B (en) | 2023-08-07 | 2023-08-07 | Semiconductor device stacking and packaging structure |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321468A (en) * | 1996-05-30 | 1997-12-12 | Toshiba Corp | Heat radiating device |
| CN213459724U (en) * | 2020-10-22 | 2021-06-15 | 爱微(江苏)电力电子有限公司 | High heat dissipating EPS power module |
| CN214542193U (en) * | 2021-01-31 | 2021-10-29 | 晋江市小芯电子科技有限公司 | Three-dimensional chip that piles up of area heat dissipation function |
| CN114843234A (en) * | 2022-05-07 | 2022-08-02 | 中山市木林森微电子有限公司 | Semiconductor packaging structure |
| WO2023010915A1 (en) * | 2021-08-02 | 2023-02-09 | 华为技术有限公司 | Electronic device |
-
2023
- 2023-08-07 CN CN202310985936.3A patent/CN117038602B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321468A (en) * | 1996-05-30 | 1997-12-12 | Toshiba Corp | Heat radiating device |
| CN213459724U (en) * | 2020-10-22 | 2021-06-15 | 爱微(江苏)电力电子有限公司 | High heat dissipating EPS power module |
| CN214542193U (en) * | 2021-01-31 | 2021-10-29 | 晋江市小芯电子科技有限公司 | Three-dimensional chip that piles up of area heat dissipation function |
| WO2023010915A1 (en) * | 2021-08-02 | 2023-02-09 | 华为技术有限公司 | Electronic device |
| CN114843234A (en) * | 2022-05-07 | 2022-08-02 | 中山市木林森微电子有限公司 | Semiconductor packaging structure |
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| Publication number | Publication date |
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| CN117038602A (en) | 2023-11-10 |
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