CN117015266A - Package substrate, manufacturing method thereof and display assembly - Google Patents
Package substrate, manufacturing method thereof and display assembly Download PDFInfo
- Publication number
- CN117015266A CN117015266A CN202210449960.0A CN202210449960A CN117015266A CN 117015266 A CN117015266 A CN 117015266A CN 202210449960 A CN202210449960 A CN 202210449960A CN 117015266 A CN117015266 A CN 117015266A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- circuit
- circuit layer
- embedded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 246
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 claims abstract description 14
- 238000003466 welding Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 540
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 84
- 239000011889 copper foil Substances 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 43
- 229910052802 copper Inorganic materials 0.000 claims description 31
- 239000010949 copper Substances 0.000 claims description 31
- 239000012790 adhesive layer Substances 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 230000002378 acidificating effect Effects 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 229920000106 Liquid crystal polymer Polymers 0.000 description 6
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 6
- 238000009459 flexible packaging Methods 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- -1 Polyethylene terephthalate Polymers 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229920001225 polyester resin Polymers 0.000 description 2
- 239000004645 polyester resin Substances 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a packaging substrate which comprises a first outer circuit layer, a first substrate layer, a first inner circuit layer, a second substrate layer, a second outer circuit layer and a buried circuit board. The first substrate layer and the second substrate layer are respectively arranged on two opposite sides of the first inner circuit layer, the first outer circuit layer is arranged on the first substrate layer, and the second outer circuit layer is arranged on the first inner circuit layer. The embedded circuit board is arranged between the second substrate layer and the first inner circuit layer, the embedded circuit board comprises an embedded substrate layer and a second inner circuit layer, the embedded substrate layer is arranged between the second inner circuit layer and the first inner circuit layer, the second inner circuit layer comprises a plurality of welding pads and a plurality of golden fingers, the welding pads are electrically connected with the first inner circuit layer or the second outer circuit layer, the packaging substrate is provided with an opening, the opening penetrates through the second outer circuit layer and the second substrate layer, and the golden fingers are exposed out of the opening. In addition, the application also provides a manufacturing method of the packaging substrate and a display assembly.
Description
Technical Field
The application relates to a packaging substrate, a manufacturing method thereof and a display assembly.
Background
The flexible OLED display screen can be manufactured through a flexible circuit board and screen module vertical packaging process. The packaging process mainly comprises the following steps: firstly, arranging a driving chip on a golden finger on one side of a flexible packaging substrate in a crimping manner; and then, the display screen is arranged at the input and output ends of the other side of the flexible packaging substrate in a crimping mode.
In general, since the flexible packaging substrate is easy to deform, the other side of the flexible packaging substrate, which is provided with the input and output ends, is easy to dent in the process of crimping the driving chip, and the input and output ends in the dent area cannot be normally crimped with the display screen.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method for manufacturing a package substrate to solve the above-mentioned problems.
In addition, it is also necessary to provide a package substrate.
In addition, it is also necessary to provide a display assembly.
A method of manufacturing a package substrate, comprising the steps of: the method comprises the steps of providing a copper-clad carrier plate, wherein the copper-clad carrier plate comprises a carrier plate and a carrier plate copper foil layer, and the carrier plate copper foil layer is arranged on one side of the carrier plate. Etching the copper foil layer of the carrier plate to form a first outer circuit layer. The first circuit substrate is arranged on one side, far away from the carrier plate, of the first outer circuit layer, the first circuit substrate comprises a first substrate layer and a first inner circuit layer, and the first substrate layer is arranged between the first outer circuit layer and the first inner circuit layer. The embedded circuit board is arranged on one side, far away from the first outer circuit layer, of the first circuit substrate, forward projection of the embedded circuit board is located in the first circuit substrate, the embedded circuit board comprises an embedded substrate layer and a second inner circuit layer, the embedded substrate layer is arranged between the second inner circuit layer and the first inner circuit layer, and the second inner circuit layer comprises a plurality of golden fingers and welding pads. And a second circuit substrate is arranged on one side, far away from the first outer circuit layer, of the first circuit substrate and the embedded circuit board, the second circuit substrate comprises a second substrate layer and a second outer circuit layer, and the second substrate layer is arranged on one side, close to the first circuit substrate, of the second outer circuit layer.
Removing the carrier plate to obtain a substrate intermediate, and arranging a first opening in the substrate intermediate, wherein the first opening penetrates through the second outer circuit layer and the second base material layer, and the golden finger is exposed out of the bottom of the first opening to obtain the packaging substrate.
Further, the step of "before the first circuit substrate is disposed on the side of the first outer circuit layer away from the carrier" further includes: and a first bonding layer is arranged between the first substrate layer and the first outer circuit layer.
The step of disposing a second circuit substrate on a side of the first circuit substrate far away from the first outer circuit layer, before the step of disposing a second circuit substrate on a side of the embedded circuit board far away from the first outer circuit layer, further includes: and a second bonding layer is arranged between the first inner circuit layer and the second substrate layer, a second opening is formed in the second bonding layer in a penetrating manner, the second opening corresponds to part of the embedded circuit board, and the other part of the embedded circuit board is embedded into the second bonding layer.
Further, the embedded circuit board further includes a third inner circuit layer, the third inner circuit layer is disposed on a side of the embedded substrate layer facing away from the second inner circuit layer, and the step of "before the second bonding layer is disposed between the first inner circuit layer and the second substrate layer" further includes: and a conductive adhesive layer is arranged between the third inner circuit layer and the first inner circuit layer.
Further, the step of disposing a first circuit substrate on a side of the first outer circuit layer away from the carrier plate includes: and arranging a first copper-clad substrate on one side, far away from the first outer circuit layer, of the first bonding layer, wherein the first copper-clad substrate comprises the first base material layer and a first copper foil layer, and a first copper-clad intermediate is obtained. And a first through hole is formed in the first copper-clad intermediate, the first through hole penetrates through the first copper foil layer, the first base material layer and the first bonding layer, and part of the first outer circuit layer is exposed at the bottom of the first through hole. And a first conducting body is arranged in the first through hole and is electrically connected with the first copper foil layer and the first outer circuit layer, and the first copper foil layer is etched to form the first inner circuit layer, and the first inner circuit layer and the first substrate layer form the first circuit substrate.
Further, the step of disposing a second circuit substrate on a side of the first circuit substrate, which is far away from the first outer circuit layer, of the embedded circuit board includes: and arranging a second copper-clad substrate on one side, far away from the first inner circuit layer, of the second bonding layer, wherein the second copper-clad substrate comprises the second base material layer and a second copper foil layer, and a second copper-clad intermediate is obtained. And a second through hole is formed in the second copper-clad intermediate, the second through hole penetrates through the second copper foil layer, the second base material layer and the second bonding layer, and part of the first inner circuit layer is exposed at the bottom of the second through hole. And a second conductive body is arranged in the second through hole and is electrically connected with the second copper foil layer, the first inner circuit layer and the second outer circuit layer, and the second outer circuit layer and the second substrate layer form the second circuit substrate.
Further, before the step of etching the second copper foil layer to form the second outer line layer, further includes: and a third through hole is formed in the second copper-clad intermediate, the third through hole penetrates through the second copper foil layer, the second base material layer and part of the second bonding layer, and the welding pad is exposed out of the bottom of the second through hole. And a third conducting body is arranged in the third through hole and is electrically connected with the second copper foil layer and the welding pad.
Further, the manufacturing method of the embedded circuit board comprises the following steps: providing a third copper-clad substrate, wherein the third copper-clad substrate comprises the base material mother board and at least one base copper layer, and the base copper layer is arranged on at least one side surface of the base material mother board. And arranging a conductive pattern on the surface of the base copper layer, wherein the conductive pattern is provided with a plurality of wire grooves, and part of the base copper layer is exposed out of the bottoms of the wire grooves. And removing part of the base copper layer exposed at the bottom of the wire slot to form the second inner side circuit layer and/or the third inner side circuit layer, wherein the substrate motherboard and the second inner side circuit layer or the substrate motherboard, the second inner side circuit layer and the third inner side circuit layer form a buried circuit motherboard. Dividing the embedded circuit motherboard to obtain a plurality of independent embedded circuit boards, wherein each embedded circuit board comprises an embedded substrate layer, a second inner circuit layer and/or a third inner circuit layer.
Further, the method further comprises the steps of: and a solder mask layer is arranged on the surface, far away from the first circuit substrate, of the second circuit substrate, the solder mask layer is provided with a plurality of solder mask windows, and the first open holes and part of the second outer circuit layers are exposed at the bottoms of the solder mask windows.
Further, the method further comprises the steps of: and arranging a first protection layer on the surface of the first outer circuit layer. And a second protective layer is arranged on the surface of the second outer line layer in the anti-welding window, and a third protective layer is arranged on the surface of the golden finger.
Further, the carrier comprises a copper-carrying layer and a resist layer, the resist layer is disposed between the copper-carrying layer and the copper foil layer of the carrier, and the step of removing the carrier to obtain a substrate intermediate comprises: the copper-carrying layer is removed with a first etchant that is acidic and the resist layer is removed with a second etchant that is alkaline.
A package substrate comprises a first outer circuit layer, a first substrate layer, a first inner circuit layer, a second substrate layer, a second outer circuit layer and a buried circuit board. The first substrate layer and the second substrate layer are respectively arranged on two opposite sides of the first inner circuit layer, the first outer circuit layer is arranged on one side, deviating from the first inner circuit layer, of the first substrate layer, the first outer circuit layer comprises a plurality of conductive connecting pads, and the second outer circuit layer is arranged on one side, deviating from the first inner circuit layer, of the second substrate layer. The embedded circuit board is arranged between the second substrate layer and the first inner circuit layer, and the forward projection of the embedded circuit board is positioned in the first inner circuit layer. The embedded circuit board comprises an embedded substrate layer and a second inner circuit layer, wherein the embedded substrate layer is arranged between the second inner circuit layer and the first inner circuit layer, the second inner circuit layer comprises a plurality of welding pads and a plurality of golden fingers, and the welding pads are electrically connected with the first inner circuit layer or the second outer circuit layer. The packaging substrate is provided with a first opening, the first opening penetrates through the second outer circuit layer and the second base material layer, and a plurality of golden fingers are exposed out of the bottom of the first opening.
Further, the circuit board further comprises a first bonding layer and a second bonding layer, wherein the first bonding layer is arranged between the first substrate layer and the first outer circuit layer, the second bonding layer is arranged between the first inner circuit layer and the second substrate layer and covers part of the embedded circuit board, and the first opening further penetrates part of the second bonding layer.
Further, the circuit further comprises a first conducting body, a second conducting body and a third conducting body, wherein the first conducting body is arranged between the first outer circuit layer and the first inner circuit layer, the second conducting body is arranged between the second outer circuit layer and the first inner circuit layer, and the third conducting body is arranged between the second outer circuit layer and the second inner circuit layer.
Further, the embedded circuit board further comprises a third inner circuit layer, the third inner circuit layer is arranged on one side, away from the second inner circuit layer, of the embedded substrate layer, the packaging substrate further comprises a conductive adhesive layer, and the conductive adhesive layer is arranged between the third inner circuit layer and the first inner circuit layer.
Further, the first substrate layer and the second substrate layer have flexibility, and the embedded substrate layer has rigidity.
Further, one surface of each adjacent two of the conductive connection pads facing away from the first substrate layer is flush.
Further, the electric wire connecting pad further comprises a first protection layer, a second protection layer and a third protection layer, wherein the first protection layer is arranged on the surface of the electric wire connecting pad, the second protection layer is arranged on the surface of a part of the second outer circuit layer, and the third protection layer is arranged on the surface of the golden finger.
The display assembly comprises a display screen module, a driving chip and the packaging substrate, wherein the driving chip is arranged in the first opening, the driving chip is electrically connected with the golden finger, the display screen module is arranged on the first outer circuit layer, and the display screen module is electrically connected with the conductive connecting pad.
Compared with the prior art, the manufacturing method of the packaging substrate provided by the application has the advantages that the hard embedded circuit substrate is locally embedded, the embedded circuit substrate can be accurately embedded, unnecessary areas can be omitted, the material cost is saved, the product yield is improved, the embedded circuit substrate is made of the hard substrate, the reliability and the quality of the thin golden finger are facilitated, and the compression joint stability of the electronic element on the packaging substrate can be improved. Meanwhile, the embedded circuit substrate is embedded in the interior, so that the overall thickness of the packaging substrate is not additionally increased.
Drawings
Fig. 1 is a schematic cross-sectional view of a copper-clad carrier according to a first embodiment of the present application.
FIG. 2 is a schematic cross-sectional view of the copper-clad support plate shown in FIG. 1 after etching to form a first outer circuit layer.
Fig. 3 is a schematic cross-sectional view of a first copper-clad intermediate according to a first embodiment of the present application.
FIG. 4 is a schematic cross-sectional view of the first copper foil layer shown in FIG. 1 after etching to form a first inner circuit layer.
Fig. 5 is a schematic cross-sectional view of the first inner circuit layer shown in fig. 4 after the embedded circuit board is disposed on one side of the first inner circuit layer.
Fig. 6a to fig. 6d are schematic views illustrating a manufacturing process of the inner circuit board according to the first embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a second copper-clad intermediate according to a first embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of the second copper-clad intermediate shown in fig. 7 after etching to form a second outer line layer.
Fig. 9 is a schematic cross-sectional view of the copper-bearing layer of fig. 8 after removal.
Fig. 10 is a schematic cross-sectional view of a substrate intermediate according to a first embodiment of the present application.
Fig. 11 is a schematic cross-sectional view of the substrate intermediate shown in fig. 10 after the first opening is provided.
Fig. 12 is a schematic cross-sectional view of the second circuit board shown in fig. 11 after a solder mask layer is disposed on the surface thereof.
Fig. 13 is a schematic cross-sectional view of a package substrate according to a first embodiment of the present application.
Fig. 14 is a schematic cross-sectional view of a display assembly according to a first embodiment of the present application.
Fig. 15 is a schematic cross-sectional view of a package substrate according to a second embodiment of the present application.
Fig. 16a to 16e are schematic views illustrating a manufacturing process of an inner circuit board according to a second embodiment of the present application.
Fig. 17 is a schematic cross-sectional view of a display assembly according to a second embodiment of the present application.
Description of the main reference signs
Package substrate 100, 100'
Copper-clad carrier plate 10
Carrier plate 11
Copper-carrying layer 111
Resist layer 112
Copper foil layer 12 of carrier plate
First outer circuit layer 121
Conductive connection pad 122
First copper-clad substrate 20
First adhesive layer 21
First copper-clad intermediate 22
First substrate layer 23
First copper foil layer 24
First through hole 221
First conductive body 222
First inner circuit layer 25
First circuit substrate 26
Built-in circuit board 30, 30'
Buried substrate layer 31
Fourth through hole 311
Second inner circuit layer 32
Bonding pad 321
Golden finger 323
Third copper-clad substrate 33
Substrate motherboard 34
Base copper layer 35
Conductive pattern 351
Wire slot 352
Second adhesive layer 36
Second opening 361
Independent line 37
Fourth via 38
Conductive adhesive layer 381
Third inner circuit layer 39
Second copper-clad substrate 40
Second copper-clad intermediate 41
Second through hole 411
Second conductor 412
Third through hole 413
Third conductive body 414
Second substrate layer 42
Second copper foil layer 43
Second outside wiring layer 44
Second circuit board 45
Substrate intermediate 50
First opening 51
Solder mask layer 52
Welding-proof window 521
First protective layer 531
Second protective layer 532
Third protective layer 533
Display assembly 300
Display screen module 301
Drive chip 302
The application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.
Referring to fig. 1 to 13, a first embodiment of the present application provides a method for manufacturing a package substrate 100, which includes the steps of:
referring to fig. 1, a copper-clad carrier 10 is provided, wherein the copper-clad carrier 10 includes a carrier 11 and a carrier copper foil layer 12, and the carrier copper foil layer 12 is disposed on a side surface of the carrier 11.
In this embodiment, the carrier 11 includes a copper-carrying layer 111 and a resist layer 112, and the resist layer 112 is disposed between the copper-carrying layer 111 and the copper foil layer 12 of the carrier. The material of the resist layer 112 may be nickel, nichrome, nickel-phosphorus alloy, or the like. It will be appreciated that in other embodiments of the present application, the carrier plate 11 may include a release carrier plate (not shown) and a release film (not shown) disposed between the carrier plate copper foil layer 12 and the release carrier plate.
Referring to fig. 2, the carrier copper foil layer 12 is etched to form a first outer circuit layer 121. The first outer circuit layer 121 includes a plurality of conductive connection pads 122, and a plurality of conductive connection pads 122 are flush toward one side of the resist layer 112. The carrier 11 supports or loads the carrier copper foil layer 12, so that the carrier copper foil layer 12 has a better flatness, and further the plurality of conductive connection pads 122 have a better flatness. Specifically, a height difference (not shown) of a side of the plurality of conductive connection pads 122 toward the resist layer 112 is within 1 μm.
Referring to fig. 3, a first bonding layer 21 is disposed on the surface of the first outer circuit layer 121, and a first copper-clad substrate 20 is disposed on the surface of the first bonding layer 21, so as to obtain a first copper-clad intermediate 22. The first copper-clad substrate 20 includes a first base material layer 23 and a first copper foil layer 24, and the first base material layer 23 is disposed between the first copper foil layer 24 and the first adhesive layer 21.
In this embodiment, in step S103, the first substrate layer 23 has flexibility, and the material of the first substrate layer 23 includes at least one of Polyimide (PI), polyester resin (Polyethylene terephthalate, PET), polyethylene naphthalate (PEN), liquid crystal polymer (liquid crystal polymer, LCP), and modified Polyimide (modified Polyimide, MPI).
Referring to fig. 4, a first through hole 221 is formed in the first copper-clad intermediate 22, and the first through hole 221 penetrates through the first copper foil layer 24, the first substrate layer 23 and the first adhesive layer 21, so that a portion of the first outer circuit layer 121 is exposed at the bottom of the first through hole 221 on a side facing away from the resist layer 112.
Referring to fig. 4 again, the first via 221 is filled with copper to form a first via 222, and the first copper foil layer 24 is etched to form a first inner circuit layer 25. The first via 222 is electrically connected to the first inner circuit layer 25 and the first outer circuit layer 121. The first inner wiring layer 25 and the first base material layer 23 constitute a first wiring substrate 26.
S106, referring to FIG. 5, the first inner circuit layer 25 and one embedded circuit board 30 are aligned and pressed by the fixing post alignment or machine vision recognition. The front projection of the embedded circuit board 30 is located in the first inner circuit layer 25, and the embedded circuit board 30 is disposed substantially in the middle of the first inner circuit layer 25. The embedded wiring board 30 includes an embedded base material layer 31 and a second inner wiring layer 32. The embedded substrate layer 31 is disposed between the second inner circuit layer 32 and the first inner circuit layer 25. The second inner circuit layer 32 includes a plurality of pads 321 and a plurality of gold fingers 323.
In the present embodiment, the embedded substrate layer 31 has rigidity, and the embedded wiring board 30 is a hard board having a modulus of more than 20 GPa. The material of the embedded substrate layer 31 includes at least one of a hard substrate material such as polypropylene, epoxy resin, ceramic, glass, etc.
In this embodiment, referring to fig. 6a to 6d, in step S106, the embedded circuit board 30 may be manufactured by a semi-additive process (SAP), and the specific manufacturing method includes the steps of:
referring to fig. 6a, a third copper-clad substrate 33 is provided, wherein the third copper-clad substrate 33 includes the base motherboard 34 and a base copper layer 35. One of the base copper layers 35 is disposed on one side of the substrate motherboard 34.
Referring to fig. 6b, a conductive pattern 351 is disposed on the surface of the base copper layer 35 by electroplating, the conductive pattern 351 has a plurality of trenches 352, and a portion of the base copper layer 35 is exposed at the bottom of the trenches 352.
Referring to fig. 6c, a portion of the base copper layer 35 exposed at the bottom of the trench 352 is removed to form the second inner circuit layer 32.
Referring to fig. 6d, the substrate motherboard 34 and the second inner circuit layer 32 are divided to obtain a plurality of independent embedded circuit boards 30. Each of the embedded circuit boards 30 includes one embedded substrate layer 31 and one second inner circuit layer 32. The second inner circuit layer 32 is disposed on at least one side of the embedded substrate layer 31. The second inner circuit layer 32 is manufactured by a semi-additive method, which is advantageous for forming the golden finger 323 with smaller line width and line distance.
Referring to fig. 7, a second bonding layer 36 is disposed on the surface of the first circuit substrate 26 and a part of the embedded circuit board 30, and a second copper-clad substrate 40 is disposed on the surface of the second bonding layer 36, so as to obtain a second copper-clad intermediate 41. The second adhesive layer 36 is provided with a second opening 361, the middle portion of the embedded circuit board 30 is exposed out of the second opening 361, and other portions of the embedded circuit board 30 are embedded in the second adhesive layer 36. The second copper-clad substrate 40 includes a second base material layer 42 and a second copper foil layer 43, and the second base material layer 42 is disposed between the second copper foil layer 43 and the second adhesive layer 36.
In this embodiment, in step S107, the second substrate layer 42 has flexibility, and the material of the second substrate layer 42 includes at least one of Polyimide (PI), polyester resin (Polyethylene terephthalate, PET), polyethylene naphthalate (PEN), liquid crystal polymer (liquid crystal polymer, LCP), and modified Polyimide (modified Polyimide, MPI).
Referring to fig. 8, a second through hole 411 is formed in the second copper clad intermediate 41. The second through hole 411 penetrates the second copper foil layer 43, the second base material layer 42 and the second adhesive layer 36, so that a portion of the first inner circuit layer 25 is exposed at the bottom of the second through hole 411.
In this embodiment, step S8 further includes:
referring to fig. 8, a third through hole 413 is formed in the second copper clad intermediate 41, and the third through hole 413 is disposed corresponding to the embedded circuit board 30. The third through hole 413 penetrates the second copper foil layer 43, the second base material layer 42 and a part of the second adhesive layer 36, and a part of the pad 321 is exposed at the bottom of the third through hole 413.
Referring to fig. 8 again, the second via 411 is filled with copper to form a second via 412, and the second copper foil layer 43 is etched to form a second outer circuit layer 44. The second via 412 is electrically connected to the second outer circuit layer 44 and the first inner circuit layer 25. The second outer circuit layer 44 and the second base material layer 42 form a second circuit substrate 45.
In this embodiment, step S109 further includes:
referring to fig. 8 again, copper is filled in the third via 413 to form a third via 414, and the third via 414 is electrically connected to the second outer circuit layer 44 and a portion of the pad 321.
Referring to fig. 9 to 10, the carrier 11 is removed to obtain a substrate intermediate 50.
In this embodiment, step S110 specifically includes:
Referring to fig. 9, the copper-carrying layer 111 is etched and removed by a first etchant (not shown), which may be performed simultaneously with the etching of the second copper foil layer 43 in step S109, and the second copper foil layer 43 is etched and removed by an acidic first etchant (e.g., acidic copper chloride) to form the second outer circuit layer 44, because the material of the second copper foil layer 43 is the same as that of the copper-carrying layer 111. At this time, the resist layer 112 is made of a material different from the second copper foil layer 43 and the copper-carrying layer 111, so that the first etchant cannot etch the resist layer 112.
Referring to fig. 10, the resist layer 112 is etched and removed by a second etchant (not shown) so that the first outer circuit layer 121 is exposed. The second etchant is alkaline (e.g., alkaline copper chloride) and may remove the resist layer without affecting the second outer wiring layer 44 and the first outer wiring layer 121.
Referring to fig. 11, a first opening 51 is disposed in the substrate intermediate 50, and the first opening 51 is disposed substantially corresponding to the second opening 361. The first opening 51 penetrates the second outer circuit layer 44, the second base material layer 42, and a portion of the second adhesive layer 36. The plurality of golden fingers 323 of the second inner circuit layer 32 are exposed at the bottom of the first opening 51. In particular, the first opening 51 may be formed by laser cutting or mechanical drilling.
Referring to fig. 12, a solder mask layer 52 is disposed on a surface of the second circuit substrate 45 away from the first circuit substrate 26, the solder mask layer 52 has a plurality of solder mask windows 521, the first openings 51 and a portion of the second outer circuit layers 44 are exposed in the solder mask windows 521, and a portion of the solder mask windows 521 are disposed corresponding to the second vias 412.
Referring to fig. 13, a first protection layer 531 is disposed on the surface of the conductive connection pad 122; a second protective layer 532 is disposed on the surface of the second outer line layer 44 in the solder mask window 521; and disposing a third protection layer 533 on the surface of the gold finger 323 to obtain the package substrate 100. The first protection layer 531, the second protection layer 532 and the third protection layer 533 are made of nickel gold or nickel palladium, which can prevent the copper of the conductive connection pad 122 and the gold finger 323 from being oxidized or corroded, and are used for soldering and contact.
Compared with the prior art, the manufacturing method of the package substrate 100 provided by the application has the advantages that the hard embedded circuit board 30 is embedded in the part of the package substrate 100 which is flexible as a whole, and the embedded circuit board 30 is provided with the plurality of golden fingers 323 for connecting other electronic components (for example, the driving chip 302), so that the stability of the electronic components when being in pressure connection with the package substrate 100 can be improved. Meanwhile, when the electronic component is crimped, the hard embedded circuit board 30 can ensure that the side (i.e., the first outer circuit layer 121) of the package substrate 100, on which the electronic component is not disposed, has good flatness, so as to reduce poor connection caused by the subsequent arrangement of other electronic components (e.g., the display screen module 301) on the surface of the first outer circuit layer 121. Furthermore, the embedded circuit board 30 is embedded in the second adhesive layer 36, so that the overall thickness of the package substrate 100 is not increased.
Referring to fig. 13, the present application further provides a package substrate 100, where the package substrate 100 includes a first outer circuit layer 121, a first substrate layer 23, a first inner circuit layer 25, a second substrate layer 42, a second outer circuit layer 44, and a buried circuit board 30.
The first substrate layer 23 and the second substrate layer 42 are respectively disposed on two opposite sides of the first inner circuit layer 25, the first outer circuit layer 121 is disposed on one side of the first substrate layer 23 facing away from the first inner circuit layer 25, and the second outer circuit layer 44 is disposed on one side of the second substrate layer 42 facing away from the first inner circuit layer 25.
The embedded circuit board 30 is disposed between the second substrate layer 42 and the first inner circuit layer 25, and the forward projection of the embedded circuit board 30 is located in the first inner circuit layer 25.
The embedded circuit board 30 includes an embedded substrate layer 31 and a second inner circuit layer 32, the embedded substrate layer 31 is disposed between the second inner circuit layer 32 and the first inner circuit layer 25, the second inner circuit layer 32 includes a plurality of pads 321 and a plurality of fingers 323, and the pads 321 are electrically connected to the first inner circuit layer 25 or the second outer circuit layer 44.
The package substrate 100 is provided with a first opening 51, the first opening 51 penetrates the second outer circuit layer 44 and the second base material layer 42, and the plurality of gold fingers 323 are exposed at the bottom of the first opening 51.
Referring to fig. 15, a method for manufacturing a package substrate 100' is also provided in a second embodiment of the present application, which is different from the first embodiment. The embedded circuit board 30' further includes a third inner circuit layer 39 and a fourth conductive body 38. The third inner circuit layer 39 and the second inner circuit layer 32 are respectively disposed on two opposite sides of the embedded substrate layer 31. The fourth via 38 is connected between the third inner wiring layer 39 and the second inner wiring layer 32. Referring to fig. 16a to 16e, unlike the embedded circuit board 30 of the first embodiment, the method for manufacturing the embedded circuit board 30' includes:
referring to fig. 16a, another third copper-clad substrate 33 is provided, and the another third copper-clad substrate 33 includes the base motherboard 34 and two base copper layers 35, wherein the two base copper layers 35 are respectively disposed on two opposite sides of the base motherboard 34.
Referring to fig. 16b, a plurality of fourth through holes 311 are formed through the surface of the third copper-clad substrate 33, and the fourth through holes 311 penetrate through the two copper-clad layers 35 and the substrate motherboard 34.
Referring to fig. 16c, conductive patterns 351 are respectively disposed on the surfaces of the two copper-based layers 35 by electroplating, and a portion of the conductive patterns 351 is filled into the fourth via holes 311 to form the fourth via 38. Each conductive pattern 351 has a plurality of trenches 352, and a portion of the base copper layer 35 is exposed at the bottom of the trench 352.
Referring to fig. 16d, a portion of the base copper layer 35 exposed at the bottom of the trench 352 is removed to form a plurality of independent circuits 37, and the independent circuits 37 are respectively disposed on two opposite sides of the substrate motherboard 34. The plurality of independent wires 37 are combined to form the second inner wire layer 32 and the third inner wire layer 39.
S205 referring to fig. 16e, the substrate motherboard 34, the second inner circuit layer 32 and the third inner circuit layer 39 are divided to obtain a plurality of embedded circuit boards 30'. Each embedded circuit board 30' includes one embedded substrate layer 31, one second inner circuit layer 32 and one third inner circuit layer 39, where the second inner circuit layer 32 and the third inner circuit layer 39 are disposed on two sides of the embedded substrate layer 31.
Referring again to fig. 15, in the second embodiment of the present application, unlike the package substrate 100 in the first embodiment, the method for manufacturing the package substrate 100' further includes:
s206, disposing a conductive adhesive layer 381 between the third inner circuit layer 39 and the first inner circuit layer 25. The conductive adhesive layer 381 electrically connects the third inner circuit layer 39 and the first inner circuit layer 25. In other embodiments of the present application, the third inner circuit layer 39 and the first inner circuit layer 25 may be electrically connected by electroplating, copper paste plugging and soldering.
In the second embodiment of the present application, by disposing the conductive adhesive layer 381 in the embedded circuit board 30', the conductive adhesive layer 381 can be electrically connected to the second inner circuit layer 32 through the fourth conductive member 38, so as to electrically connect the second inner circuit layer 32 to the first inner circuit layer 25. For different wiring requirements, the package substrate 100' of the second embodiment of the present application may be used.
Referring to fig. 15 again, the second embodiment of the present application further provides a package substrate 100', wherein the package substrate 100' includes a first outer circuit layer 121, a first substrate layer 23, a first inner circuit layer 25, a second substrate layer 42, a second outer circuit layer 44, a buried circuit board 30', and a conductive adhesive layer 381.
The first substrate layer 23 and the second substrate layer 42 are respectively disposed on two opposite sides of the first inner circuit layer 25, the first outer circuit layer 121 is disposed on one side of the first substrate layer 23 facing away from the first inner circuit layer 25, and the second outer circuit layer 44 is disposed on one side of the second substrate layer 42 facing away from the first inner circuit layer 25.
The embedded circuit board 30 'is disposed between the second substrate layer 42 and the first inner circuit layer 25, and the forward projection of the embedded circuit board 30' is located in the first inner circuit layer 25.
The embedded circuit board 30' includes an embedded substrate layer 31, a second inner circuit layer 32, a third inner circuit layer 39 and a fourth via 38. The second inner circuit layer 32 and the third inner circuit layer 39 are respectively disposed on opposite sides of the buried substrate layer 31, and the fourth via 38 is connected between the second inner circuit layer 32 and the third inner circuit layer 39. The second inner circuit layer 32 is disposed toward the second base material layer 42, and the third inner circuit layer 39 is disposed toward the first inner circuit layer 25. The conductive adhesive layer 381 is connected between the first inner circuit layer 25 and the third inner circuit layer 39. The second inner circuit layer 32 includes a plurality of pads 321 and a plurality of gold fingers 323, and the pads 321 are electrically connected to the fourth conductive body 38.
The package substrate 100' is provided with a first opening 51, the first opening 51 penetrates the second outer circuit layer 44 and the second base material layer 42, and the plurality of gold fingers 323 are exposed at the bottom of the first opening 51.
Referring to fig. 14 and 17, the first embodiment or the second embodiment of the present application further provides a display assembly 300, where the display assembly 300 includes a display module 301, a driving chip 302, and the package substrate (100, 100'), and the driving chip 302 is disposed in the first opening 51. The driving chip 302 is electrically connected to the golden finger 323, and the display module 301 is disposed on the plurality of conductive connection pads 122 connected to the first outer circuit layer 121.
Further, other variations within the spirit of the present application will occur to those skilled in the art, and it is intended, of course, that such variations be included within the scope of the application as claimed herein.
Claims (18)
1. A method of manufacturing a package substrate, comprising the steps of:
providing a copper-clad carrier plate, wherein the copper-clad carrier plate comprises a carrier plate and a carrier plate copper foil layer, and the carrier plate copper foil layer is arranged on one side of the carrier plate;
etching the copper foil layer of the carrier plate to form a first outer circuit layer;
A first circuit substrate is arranged on one side, far away from the carrier plate, of the first outer circuit layer, the first circuit substrate comprises a first substrate layer and a first inner circuit layer, and the first substrate layer is arranged between the first outer circuit layer and the first inner circuit layer;
an embedded circuit board is arranged on one side, far away from a first outer circuit layer, of the first circuit substrate, forward projection of the embedded circuit board is positioned in the first circuit substrate, the embedded circuit board comprises an embedded substrate layer and a second inner circuit layer, the embedded substrate layer is arranged between the second inner circuit layer and the first inner circuit layer, and the second inner circuit layer comprises a plurality of golden fingers and welding pads;
a second circuit substrate is arranged on one side, far away from the first outer circuit layer, of the first circuit substrate and the embedded circuit board, the second circuit substrate comprises a second base material layer and a second outer circuit layer, and the second base material layer is arranged on one side, close to the first circuit substrate, of the second outer circuit layer;
removing the carrier plate to obtain a substrate intermediate; and
and a first opening is formed in the substrate intermediate, the first opening penetrates through the second outer circuit layer and the second base material layer, and the golden finger is exposed out of the bottom of the first opening to obtain the packaging substrate.
2. The method of claim 1, wherein the step of disposing a first circuit substrate on a side of the first outer circuit layer away from the carrier further comprises:
a first bonding layer is arranged between the first substrate layer and the first outer circuit layer;
the step of disposing a second circuit substrate on a side of the first circuit substrate far away from the first outer circuit layer, before the step of disposing a second circuit substrate on a side of the embedded circuit board far away from the first outer circuit layer, further includes:
and a second bonding layer is arranged between the first inner circuit layer and the second substrate layer, a second opening is formed in the second bonding layer in a penetrating manner, the second opening corresponds to part of the embedded circuit board, and the other part of the embedded circuit board is embedded into the second bonding layer.
3. The method of manufacturing of claim 2, wherein the embedded circuit board further comprises a third inner circuit layer disposed on a side of the embedded substrate layer facing away from the second inner circuit layer, and the step of disposing a second adhesive layer between the first inner circuit layer and the second substrate layer further comprises, prior to:
and a conductive adhesive layer is arranged between the third inner circuit layer and the first inner circuit layer.
4. The method of manufacturing according to claim 2, wherein the disposing a first circuit substrate on a side of the first outer circuit layer away from the carrier plate comprises:
arranging a first copper-clad substrate on one side, far away from the first outer circuit layer, of the first bonding layer, wherein the first copper-clad substrate comprises the first base material layer and a first copper foil layer, so as to obtain a first copper-clad intermediate;
a first through hole is formed in the first copper-clad intermediate, the first through hole penetrates through the first copper foil layer, the first base material layer and the first bonding layer, and part of the first outer circuit layer is exposed out of the bottom of the first through hole;
a first conducting body is arranged in the first through hole and is electrically connected with the first copper foil layer and the first outer circuit layer; and
etching the first copper foil layer to form the first inner circuit layer, wherein the first inner circuit layer and the first substrate layer form the first circuit substrate.
5. The method of manufacturing according to claim 2, wherein the step of disposing a second wiring substrate on a side of the first wiring substrate and the embedded wiring board away from the first outer wiring layer comprises:
Arranging a second copper-clad substrate on one side, far away from the first inner circuit layer, of the second bonding layer, wherein the second copper-clad substrate comprises a second base material layer and a second copper foil layer, and a second copper-clad intermediate is obtained;
a second through hole is formed in the second copper-clad intermediate, the second through hole penetrates through the second copper foil layer, the second base material layer and the second bonding layer, and part of the first inner circuit layer is exposed out of the bottom of the second through hole;
a second conductive body is arranged in the second through hole and is electrically connected with the second copper foil layer and the first inner circuit layer; and
etching the second copper foil layer to form the second outer line layer, wherein the second outer line layer and the second substrate layer form the second line substrate.
6. The method of manufacturing of claim 5, wherein prior to the step of etching the second copper foil layer to form the second outer line layer further comprises:
a third through hole is formed in the second copper-clad intermediate, the third through hole penetrates through the second copper foil layer, the second base material layer and part of the second bonding layer, and the welding pad is exposed out of the bottom of the second through hole;
And a third conducting body is arranged in the third through hole and is electrically connected with the second copper foil layer and the welding pad.
7. The manufacturing method according to claim 1 or 3, wherein the manufacturing method of the embedded wiring board comprises:
providing a third copper-clad substrate, wherein the third copper-clad substrate comprises the base material mother board and at least one base copper layer, and the base copper layer is arranged on at least one side surface of the base material mother board;
arranging a conductive pattern on the surface of the base copper layer, wherein the conductive pattern is provided with a plurality of wire grooves, and part of the base copper layer is exposed out of the bottoms of the wire grooves;
removing part of the base copper layer exposed at the bottom of the wire slot to form the second inner side circuit layer and/or the third inner side circuit layer, wherein the base material motherboard and the second inner side circuit layer or the base material motherboard, the second inner side circuit layer and the third inner side circuit layer form a buried circuit motherboard;
dividing the embedded circuit motherboard to obtain a plurality of independent embedded circuit boards, wherein each embedded circuit board comprises an embedded substrate layer, a second inner circuit layer and/or a third inner circuit layer.
8. The method of manufacturing of claim 1, further comprising the step of:
and a solder mask layer is arranged on the surface, far away from the first circuit substrate, of the second circuit substrate, the solder mask layer is provided with a plurality of solder mask windows, and the first open holes and part of the second outer circuit layers are exposed at the bottoms of the solder mask windows.
9. The method of manufacturing of claim 8, further comprising the step of:
a first protective layer is arranged on the surface of the first outer circuit layer;
a second protective layer is arranged on the surface of the second outer line layer in the welding prevention window; and
and a third protective layer is arranged on the surface of the golden finger.
10. The method of claim 1, wherein the carrier comprises a copper-bearing layer and a resist layer disposed between the copper-bearing layer and the copper foil layer of the carrier, the step of removing the carrier to obtain a substrate intermediate comprising:
removing the copper-carrying layer by using a first etchant, wherein the first etchant is acidic; and
and removing the resist layer by adopting a second etchant, wherein the second etchant is alkaline.
11. A packaging substrate is characterized by comprising a first outer circuit layer, a first substrate layer, a first inner circuit layer, a second substrate layer, a second outer circuit layer and a buried circuit board,
The first substrate layer and the second substrate layer are respectively arranged on two opposite sides of the first inner circuit layer, the first outer circuit layer is arranged on one side of the first substrate layer, which is away from the first inner circuit layer, the first outer circuit layer comprises a plurality of conductive connection pads, the second outer circuit layer is arranged on one side of the second substrate layer, which is away from the first inner circuit layer,
the embedded circuit board is arranged between the second substrate layer and the first inner circuit layer, the forward projection of the embedded circuit board is positioned in the first inner circuit layer,
the embedded circuit board comprises an embedded substrate layer and a second inner circuit layer, the embedded substrate layer is arranged between the second inner circuit layer and the first inner circuit layer, the second inner circuit layer comprises a plurality of welding pads and a plurality of golden fingers, the welding pads are electrically connected with the first inner circuit layer or the second outer circuit layer,
the packaging substrate is provided with a first opening, the first opening penetrates through the second outer circuit layer and the second base material layer, and a plurality of golden fingers are exposed out of the bottom of the first opening.
12. The package substrate of claim 11, further comprising a first adhesive layer disposed between the first substrate layer and the first outer circuit layer and a second adhesive layer disposed between the first inner circuit layer and the second substrate layer and covering a portion of the embedded circuit board, the first opening further extending through a portion of the second adhesive layer.
13. The package substrate of claim 11, further comprising a first via disposed between the first outer circuit layer and the first inner circuit layer, a second via disposed between the second outer circuit layer and the first inner circuit layer, and a third via disposed between the second outer circuit layer and the second inner circuit layer.
14. The package substrate of claim 11, wherein the embedded circuit board further comprises a third inner circuit layer disposed on a side of the embedded substrate layer facing away from the second inner circuit layer, the package substrate further comprising a conductive adhesive layer disposed between the third inner circuit layer and the first inner circuit layer.
15. The package substrate of claim 11, wherein the first substrate layer and the second substrate layer are flexible and the buried substrate layer is rigid.
16. The package substrate of claim 11, wherein a side of each adjacent two of the conductive connection pads facing away from the first substrate layer is flush.
17. The package substrate of claim 16, further comprising a first protective layer, a second protective layer and a third protective layer, wherein the first protective layer is disposed on a surface of the conductive connection pad, the second protective layer is disposed on a surface of a portion of the second outer circuit layer, and the third protective layer is disposed on a surface of the gold finger.
18. A display assembly, comprising a display screen module, a driving chip and the package substrate according to any one of claims 11 to 17, wherein the driving chip is disposed in the first opening, the driving chip is electrically connected to the golden finger, the display screen module is disposed on the first outer circuit layer, and the display screen module is electrically connected to the conductive connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210449960.0A CN117015266A (en) | 2022-04-26 | 2022-04-26 | Package substrate, manufacturing method thereof and display assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210449960.0A CN117015266A (en) | 2022-04-26 | 2022-04-26 | Package substrate, manufacturing method thereof and display assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117015266A true CN117015266A (en) | 2023-11-07 |
Family
ID=88562255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210449960.0A Pending CN117015266A (en) | 2022-04-26 | 2022-04-26 | Package substrate, manufacturing method thereof and display assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117015266A (en) |
-
2022
- 2022-04-26 CN CN202210449960.0A patent/CN117015266A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107645824B (en) | Flexible circuit board, chip on film module and electronic device including flexible circuit board | |
| US6404052B1 (en) | Multi-layer flexible printed wiring board | |
| US10043726B2 (en) | Embedded component substrate with a metal core layer having an open cavity and pad electrodes at the bottom of the cavity | |
| US20100014265A1 (en) | Flex-rigid wiring board and electronic device | |
| CN108076584B (en) | Flexible circuit board, circuit board element and manufacturing method of flexible circuit board | |
| KR20060048212A (en) | Method of manufacturing a wiring board by utilizing electro plating | |
| KR101477818B1 (en) | Printed circuit board and method of manufacturing the same | |
| CN112314061A (en) | Circuit board, preparation method and backlight plate | |
| JP2004063710A (en) | Wiring board and electronic evice, and method for manufacturing the same | |
| CN110972413B (en) | Composite circuit board and manufacturing method thereof | |
| JP5562551B2 (en) | Manufacturing method of multilayer flexible printed wiring board | |
| KR20130055990A (en) | Rigid-flexible printed circuit board and method for manufacturing the same | |
| CN117015266A (en) | Package substrate, manufacturing method thereof and display assembly | |
| JP2000012773A (en) | Semiconductor device and its manufacture | |
| US7135204B2 (en) | Method of manufacturing a wiring board | |
| KR20040107359A (en) | Manufacturing method of semiconductor device | |
| JP2006339276A (en) | Substrate for connection and manufacturing method thereof | |
| CN113747661B (en) | Circuit board with embedded electronic element and manufacturing method thereof | |
| JPH01183196A (en) | Manufacture of multilayer printed wiring board device | |
| CN211959658U (en) | Soft and hard circuit board | |
| KR101449022B1 (en) | Printed circuit board and method for manufacturing thereof | |
| KR101510379B1 (en) | Printed circuit board assembly | |
| CN115621130A (en) | Package structure and method for manufacturing the same | |
| JP2002016330A (en) | Substrate for mounting component and its manufacturing method | |
| JP4388168B2 (en) | Resin molded substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |