CN117012645A - Method for manufacturing double-gate SGT semiconductor device - Google Patents
Method for manufacturing double-gate SGT semiconductor device Download PDFInfo
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- CN117012645A CN117012645A CN202310829840.8A CN202310829840A CN117012645A CN 117012645 A CN117012645 A CN 117012645A CN 202310829840 A CN202310829840 A CN 202310829840A CN 117012645 A CN117012645 A CN 117012645A
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- 238000000034 method Methods 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 210000000746 body region Anatomy 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method of a double-gate SGT semiconductor device, which comprises the following steps: step one, more than one first groove is formed in a selected area of a semiconductor substrate, and a gate dielectric layer and a gate conductive material layer are formed in the first groove. And step two, forming a body region. And thirdly, forming a source region. And step four, forming an interlayer film. Step five, forming a shielding grid, which comprises the following steps: step 51, etching the interlayer film and the semiconductor substrate in the forming area of the second groove in sequence to form the second groove, wherein the second groove is positioned at two sides of each first groove; the depth of the second trench in the semiconductor substrate is greater than the depth of the first trench. And 52, forming a shielding dielectric layer on the inner side surface of the second groove. And step 53, filling metal in the second groove to form the shielding grid field plate. The invention can well control the number of layers of the photomask, can manufacture the double-gate SGT under the condition of simplifying the process, and can reduce the process difficulty and increase the process controllability.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an inter-gate dielectric layer of a double gate (dual gate) Shielded Gate Trench (SGT) semiconductor device.
Background
The SGT MOSFET is a novel power semiconductor device, has lower conduction loss than the traditional deep trench MOSFET, has lower switching loss, has obvious cost advantage in the high-performance field, and is an advanced core technology of the current forefront of the medium-low voltage (less than 100V-250V) MOSFET.
SGT MOSFETs have two gates of polysilicon (Poly) with the underlying gate being a shielded gate, i.e., source polysilicon, to assist in the depletion of the voltage-withstanding region charge during reverse voltage-withstanding. The upper gate is a control gate, i.e., a conventional polysilicon gate, used to control the switching of the device.
The most important one-step process in SGT semiconductor devices such as SGT MOSFETs is the isolation process between the gate of two Poly (Poly) s in the gate trench, i.e., the polysilicon shield gate and the polysilicon gate, typically with an Oxide dielectric, known as Inter Poly Oxide (IPO). The polysilicon shield gate will be connected to the source electrode composed of the front side metal layer, so the polysilicon shield gate is also called source polysilicon; the polysilicon gate is connected to the gate electrode composed of the front metal layer; the thickness and stability of the IPO not only affect the isolation effect of the gate and the source, but also affect the input capacitance, which is critical to the SGT process.
Currently, there are two main approaches in the industry, i.e., forming IPO by thermal oxidation process and depositing IPO by High Density Plasma (HDP) Chemical Vapor Deposition (CVD) process.
In the process of forming IPO by a thermal oxidation process, heavy ion implantation is performed after the source polycrystalline silicon at the bottom is formed, so that defects are further formed on the surface of the source polycrystalline silicon; the semiconductor material such as silicon at the side surface of the gate trench, i.e. the side wall channel region of the Mesa (Mesa), is kept in a good monocrystalline structure, and then a thermal oxidation process is performed to form IPO at the top of the source polysilicon, and simultaneously form a gate oxide layer (GOX) at the side surface of the gate trench, so that the thickness of IPO is greater than that of the gate oxide layer by utilizing the characteristic of more defects on the surface of the source polysilicon. The process has simple steps, but has larger process difficulty, fixed ratio of IPO to GOX thickness, smaller thickness adjustable range, inapplicability to thin gate oxide products, and easy existence of weak points of obviously thinner IPO at the top angle (poly burner) position of source polycrystalline silicon.
In the deposition of IPO by HDP CVD, an oxide layer is formed by HDP CVD to completely fill the gate trench, and then the oxide layer is etched back to form the IPO with the desired thickness. The thickness adjustable range of the IPO in the process is large, the IPO is not influenced by the thickness of the gate oxide layer, but the process steps are complicated, and the cost is high. And is limited by HDP fill capability, with aspect ratios greater than 3 being difficult to achieve. The IPO thickness depends on the back etching of the oxide layer, and the fluctuation is larger.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a double-gate SGT semiconductor device, which can well control the number of layers of a photomask and manufacture the double-gate SGT under the condition of simplifying the process, thereby reducing the process difficulty and increasing the process controllability.
In order to solve the technical problems, the manufacturing method of the double-gate SGT semiconductor device provided by the invention comprises the following steps:
forming more than one first groove with a first depth in a selected area of a semiconductor substrate, forming a gate dielectric layer on the inner side surface of the first groove, and then filling a gate conductive material layer in the first groove; and forming a trench gate by the gate dielectric layer and the gate conductive material layer filled in the first trench.
And secondly, performing second conductivity type ion implantation in the selected region and advancing to form a second conductivity type doped body region, wherein the first groove penetrates through the body region.
And thirdly, carrying out first conductivity type heavy doping ion implantation in the selected area and pushing to form a source region, wherein the second side surface of the source region and the side surface of the first groove are self-aligned.
And step four, forming an interlayer film, wherein the interlayer film covers the surface of the semiconductor substrate on which the trench gate, the body region and the source region are formed.
Step five, forming a shielding grid, which comprises the following steps:
step 51, defining a second trench forming area, and etching the interlayer film and the semiconductor substrate in the second trench forming area in sequence to form a second trench, wherein the second trench is positioned at two sides of each first trench; the depth of the second groove in the semiconductor substrate is a second depth, and the second depth is larger than the first depth.
And 52, forming a shielding dielectric layer on the inner side surface of the second groove.
And step 53, filling metal in the second groove to form a shielding grid field plate.
The shielding grid is formed by the shielding dielectric layer and the shielding grid field plate which are filled in the second groove; and when the device is in reverse voltage resistance, the shielding grid field plates are used for exhausting the drift region formed in the semiconductor substrate and doped with the first conductive type between the shielding grid field plates so as to improve the voltage resistance of the device.
A further improvement is that step two is placed before step one or after step one.
A further improvement is that step three is placed before or after step one and step three is placed before or after step two.
In a further improvement, in the first step, a first epitaxial layer doped with the first conductivity type is further formed on the surface of the semiconductor substrate, the first trench and the second trench are both located in the first epitaxial layer, and the drift region is composed of the first epitaxial layer located at the bottom of the body region.
The further improvement is that the material of the shielding dielectric layer adopts an oxide layer.
In a further improvement, in step 52, the shielding dielectric layer also extends over the surface of the interlayer film outside the second trench.
In step 53, the metal of the shielded gate field plate also extends onto the surface of the shield dielectric layer outside the second trench.
Thereafter, the method further comprises:
and removing the metal of the shielding grid field plate on the surface of the shielding dielectric layer outside the second groove, and leveling the top surface of the shielding grid field plate in the second groove area and the top surface of the shielding dielectric layer outside the second groove, wherein the shielding dielectric layer outside the second groove remains.
A further improvement is that in step 51:
before defining the formation region of the second trench, further comprising forming a protective layer on the surface of the interlayer film;
etching the protective layer in the etching of the second groove, and then etching the interlayer film and the semiconductor substrate;
defining a forming area of the second groove by adopting a photoresist pattern formed by a photoetching process; and etching the second groove by using the photoresist pattern as a mask, or transferring the photoresist pattern into the protective layer and then etching the second groove by using the patterned protective layer as a mask.
In step 52, the shielding dielectric layer is further extended on the surface of the protection layer outside the second trench; and then removing the shielding dielectric layer outside the second groove and removing the protective layer.
In step 53, the metal of the shielded gate field plate also extends onto the surface of the interlayer film outside the second trench.
Thereafter, the method further comprises:
and removing the metal of the shielding gate field plate outside the second trench and leveling the top surface of the shielding gate field plate and the top surface of the interlayer film in the second trench region.
A further improvement is that the protective layer adopts a first nitride layer or adopts an overlapped layer of the first nitride layer and a second oxide layer
In a further improvement, in step 53, the metal material of the shielded gate field plate includes W, ti, TIN, or Al.
In the first step, the gate dielectric layer is formed by an oxide layer and a thermal oxidation process.
In a further improvement, in the first step, the gate conductive material layer is made of polysilicon.
Further improvement is that after the fifth step, the method further comprises:
and forming contact holes in selected areas, wherein the contact holes penetrate through the interlayer film, and are formed in the corresponding contact holes at the tops of the source region and the grid conductive material layer.
Forming a front metal layer, performing patterned etching on the front metal layer to form a source electrode and a grid electrode, wherein the source region is connected to the source electrode through the contact hole corresponding to the top, and the grid electrode conductive material layer is connected to the grid electrode through the contact hole corresponding to the top; the top of the shielded gate field plate is connected to the source.
Forming contact pads.
And finishing the back surface process.
Further improvements are that the backside process comprises:
and thinning the back surface of the semiconductor substrate.
The semiconductor substrate is heavily doped with the first conduction type, and the thinned semiconductor substrate is directly used as a heavily doped drain region of the first conduction type; or carrying out back injection of the first conductivity type heavy doping on the thinned semiconductor substrate to form a drain region.
And forming a back metal layer on the back of the drain region.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
In a further improvement, a 7-layer photomask is used in the process flow of the double-gate SGT semiconductor device, and is used for defining the forming areas of the first groove, the body region, the source region, the second groove, the contact hole, the front metal layer pattern and the contact liner respectively.
The double-gate SGT semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; alternatively, the dual-gate SGT semiconductor device is a P-type device and the first conductivity type is P-type and the second conductivity type is N-type.
Compared with the prior SGT gate structure adopting a superposition structure formed in the same gate trench, the invention forms the gate conductive material layer and the shielding gate field plate in the SGT in the first trench and the second trench separately, thus simplifying the forming process of the whole SGT gate structure, and the invention places the forming process of the second trench after the interlayer film is formed, thus realizing the filling of the second trench and being used as the shielding gate field plate by utilizing the metal of the back end process (BEOL) after the interlayer film.
The first trench and the second trench of the invention are defined by two layers of photomasks, but the invention can control the number of layers of the whole photomask of the device, such as by adopting 7 layers of photomasks, and compared with the prior art that the inter-polysilicon oxide layer of the SGT is formed by adopting an HDP oxide layer and back etching when adopting the same grid trench, the number of layers of the photomask of the invention is not increased, which is beneficial to further controlling the cost of the process.
Because the SGT grid structure is formed by adopting the grid dielectric layer and the grid conductive material layer which are formed in the first groove and the shielding dielectric layer and the shielding grid field plate which are formed in the second groove, an isolation oxide layer is not required to be arranged between the grid conductive material layer and the shielding grid field plate, the defect of increased process complexity caused by the isolation oxide layer is eliminated, and the process difficulty and the process controllability can be reduced.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method of fabricating a dual gate SGT semiconductor device according to an embodiment of the present invention;
FIG. 2 is a flow chart corresponding to a method of fabricating a dual-gate SGT semiconductor device according to an embodiment of the present invention and shown in a photomask order;
fig. 3A-3F are schematic cross-sectional views of a device during various steps in a method for fabricating a dual-gate SGT semiconductor device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a flow chart of a method of fabricating a dual gate SGT semiconductor device in accordance with an embodiment of the present invention; as shown in fig. 3A to 3F, a schematic cross-sectional structure of a device in each step of a method for manufacturing a dual-gate SGT semiconductor device according to an embodiment of the present invention is shown; the manufacturing method of the double-gate SGT semiconductor device comprises the following steps:
step one, as shown in fig. 3A, forming one or more first trenches 103 with a first depth in a selected region of a semiconductor substrate 101, forming a gate dielectric layer 104 on an inner side surface of the first trench 103, and then filling a gate conductive material layer 105 in the first trench 103; a trench gate is formed by the gate dielectric layer 104 and the gate conductive material layer 105 filled in the first trench 103.
In the embodiment of the present invention, a first epitaxial layer 102 doped with a first conductivity type is further formed on the surface of the semiconductor substrate 101, the first trench 103 and the second trench 110 are both located in the first epitaxial layer 102, and the drift region is formed by the first epitaxial layer 102 located at the bottom of the body region 106.
The semiconductor substrate 101 includes a silicon substrate. The first epitaxial layer 102 comprises a silicon epitaxial layer.
In the embodiment of the present invention, the gate dielectric layer 104 is formed by using an oxide layer and a thermal oxidation process.
The gate conductive material layer 105 is made of polysilicon.
Step two, as shown in fig. 3A, performing a second conductivity type ion implantation in the selected region and advancing the formation of a second conductivity type doped body region 106, the first trench 103 penetrating the body region 106.
In the embodiment of the present invention, the second step is placed after the first step. In other embodiments can also be: step two is placed before step one.
Step three, as shown in fig. 3A, performing a first conductivity type heavily doped ion implantation in the selected region and advancing the formation of the source region 107, the second side of the source region 107 and the side of the first trench 103 being self-aligned.
In the embodiment of the invention, the third step is arranged after the first step and after the second step; in other embodiments can also be: step three is arranged before the step one and before the step two; alternatively, step three is placed after step one and before step two.
In an embodiment of the present invention, the step of performing the second conductivity type heavily doped ion implantation to form the body contact region 108 is further included, where the body contact region 108 is located outside the first side of the source region 107.
In step four, as shown in fig. 3B, an interlayer film 109 is formed, and the interlayer film 109 covers the surface of the semiconductor substrate 101 where the trench gate, the body region 106, and the source region 107 are formed.
Step five, forming a shielding grid, which comprises the following steps:
step 51, as shown in fig. 3C, defining a formation region of a second trench 110, and sequentially etching the interlayer film 109 and the semiconductor substrate 101 in the formation region of the second trench 110 to form the second trench 110, where the second trench 110 is located at two sides of each of the first trenches 103; the second trench 110 is located in the semiconductor substrate 101 to a second depth, which is greater than the first depth.
In the embodiment of the present invention, in step 51:
as shown in fig. 3B, before defining the formation region of the second trench 110, a protective layer is further formed on the surface of the interlayer film 109. In some embodiments, the protective layer employs a first nitride layer 201. In other embodiments can also be: the protective layer employs an overlying layer of a first nitride layer 201 and a second oxide layer (not shown).
As shown in fig. 3C, the protective layer is etched first in the etching of the second trench 110, and then the interlayer film 109 and the semiconductor substrate 101 are etched.
In some embodiments, a photoresist pattern formed by a photolithography process defines a formation region of the second trench 110; and etching (with PR) for forming the second groove 110 by using the photoresist pattern as a mask, and then removing the photoresist pattern. In other embodiments can also be: defining a formation region of the second trench 110 by using a photoresist pattern formed by a photolithography process, transferring the photoresist pattern into the protective layer, and performing etching (witout PR) for forming the second trench 110 by using the patterned protective layer as a mask, wherein the second depth is deeper, so that the protective layer needs to be thicker after the photoresist pattern is removed, and at this time, the protective layer needs to be an overlapped layer of the first nitride layer 201 and the second oxide layer; after the second trench 110 is etched, the second oxide layer is removed.
In step 52, as shown in fig. 3D, a shielding dielectric layer 111 is formed on the inner surface of the second trench 110.
In the embodiment of the present invention, the material of the shielding dielectric layer 111 is an oxide layer.
The shielding dielectric layer 111 also extends on the surface of the protective layer outside the second trench 110, that is, the surface of the first nitride layer 201; then, the shielding dielectric layer 111 outside the second trench 110 is removed and the protection layer is removed.
Step 53, as shown in fig. 3E, filling metal in the second trench 110 to form a shielded gate field plate 112.
In the embodiment of the present invention, the metal of the shielding gate field plate 112 also extends onto the surface of the interlayer film 109 outside the second trench 110. Thereafter, the method further comprises:
the metal of the shield gate field plate 112 outside the second trench 110 is removed and the top surface of the shield gate field plate 112 and the top surface of the interlayer film 109 in the region of the second trench 110 are made flat.
The shielding gate is formed by the shielding dielectric layer 111 and the shielding gate field plate 112 filled in the second trench 110; at the time of reverse withstand voltage, the shield gate field plates 112 are used to deplete a drift region of the first conductivity type doping formed in the semiconductor substrate 101 between the shield gate field plates 112 to improve device withstand voltage.
In the embodiment of the present invention, the metal material of the shielding gate field plate 112 includes W, ti, TIN or Al, which can be implemented by a subsequent process.
In other embodiments can also be: the protective layer is not used in step 51.
In step 52, the shield dielectric layer 111 is further extended on the surface of the interlayer film 109 outside the second trench 110.
In step 53, the metal of the shielding gate field plate 112 also extends onto the surface of the shielding dielectric layer 111 outside the second trench 110. Thereafter, the method further comprises:
the metal of the shield gate field plate 112 on the surface of the shield dielectric layer 111 outside the second trench 110 is removed and the top surface of the shield gate field plate 112 in the region of the second trench 110 and the top surface of the shield dielectric layer 111 outside the second trench 110 are leveled, the shield dielectric layer 111 outside the second trench 110 remaining.
In the embodiment of the present invention, after the fifth step, the method further includes:
as shown in fig. 3F, a contact hole 113 is formed in a selected region, the contact hole 113 penetrating the interlayer film 109 and being formed in the corresponding contact hole 113 at the top of the source region 107 and the gate conductive material layer 105.
Forming a front metal layer 114, performing patterned etching on the front metal layer 114 to form a source electrode and a grid electrode, wherein the source region 107 is connected to the source electrode through the contact hole 113 corresponding to the top, and the grid electrode conductive material layer 105 is connected to the grid electrode through the contact hole 113 corresponding to the top; the top of the shielded gate field plate 112 is connected to the source.
Forming contact pads.
And finishing the back surface process.
The back side process comprises the following steps:
the semiconductor substrate 101 is thinned on the back side.
The semiconductor substrate 101 is heavily doped with the first conductivity type, and the thinned semiconductor substrate 101 is directly used as a heavily doped drain region of the first conductivity type; or performing back implantation of the first conductive type heavy doping on the thinned semiconductor substrate 101 to form a drain region.
And forming a back metal layer on the back of the drain region.
In the embodiment of the invention, the double-gate SGT semiconductor device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments can also be: the dual gate SGT semiconductor device is a P-type device and the first conductivity type is P-type and the second conductivity type is N-type.
FIG. 3 is a flow chart corresponding to a method of fabricating a dual-gate SGT semiconductor device according to an embodiment of the present invention and shown in a photomask order; in the embodiment of the present invention, a 7-layer photomask is used in the process flow of the dual-gate SGT semiconductor device, and is used to define the first trench 103, the body region 106, the source region 107, the second trench 110, the contact hole 113, the front metal layer 114 pattern, and the formation region of the contact pad, respectively. The following will be described according to the mask layer:
and etching the gate groove by a first layer photoetching process to form a sacrificial oxide layer, a gate oxide layer and a polysilicon gate. The gate trench is the first trench. The first layer photolithography process corresponds to step one.
A second layer lithography process, body implant and drive. The second layer of mask process corresponds to the second step.
And a third layer of photoetching process, and implanting and advancing source regions. The third layer of photomask process corresponds to step three.
And a fourth layer photoetching process, interlayer film deposition, second groove etching, shielding dielectric layer and shielding grid field plate deposition and back etching. The fourth layer of mask process corresponds to step five.
And fifth photoetching process, contact hole etching, body region leading-out area injection and pushing and filling tungsten plug. The fifth layer mask process corresponds to a process of forming the contact hole 112. After the opening of the contact hole 112 is opened, the body region extraction implantation is usually performed, and for the N-type device, the body region extraction region is p+ implantation, and then the p+ implantation ions are pushed into the well; then, the contact hole 112 is formed by filling a metal layer, typically tungsten, in the opening of the contact hole 112, so called a tungsten plug.
And a sixth layer of photoetching process, depositing and etching the front metal layer. A sixth layer of photolithography process corresponds to the front side metal layer 113 forming and patterning etching process.
A seventh layer of photoetching process, deposition and etching of Contact PADs (CP); and (5) a back surface process.
Compared with the prior SGT gate structure adopting the superposition structure formed in the same gate trench, the embodiment of the invention forms the gate conductive material layer 105 and the shielding gate field plate 112 in the SGT in the first trench 103 and the second trench 110 separately, so that the forming process of the whole SGT gate structure can be simplified, and the forming process of the second trench 110 is placed after the forming of the interlayer film 109, so that the filling of the second trench 110 can be realized by utilizing the metal of the back end of line (BEOL) after the interlayer film 109 and can be used as the shielding gate field plate 112, compared with the filling of polysilicon in the front end of line as the shielding gate field plate 112, the embodiment of the invention can further simplify the forming process of the shielding gate field plate 112, so that the forming process of the SGT gate structure, namely the shielding gate and the trench gate can be simplified, the process difficulty can be reduced, and the process controllability can be increased.
Although the first trench 103 and the second trench 110 in the embodiment of the present invention need to be defined by two layers of masks, the number of layers of the entire mask of the device can be controlled by using 7 layers of masks, and compared with the existing process of forming the inter-polysilicon oxide layer of the SGT by using the HDP oxide layer and back etching when using the same gate trench, the number of layers of the mask in the embodiment of the present invention is not increased, which is beneficial to further controlling the process cost.
Because the SGT gate structure of the embodiment of the present invention is formed by using the gate dielectric layer 104 and the gate conductive material layer 105 formed in the first trench 103 and the shield dielectric layer 111 and the shield gate field plate 112 formed in the second trench 110, there is no need to provide an isolation oxide layer between the gate conductive material layer 105 and the shield gate field plate 112, so that the defect of increased process complexity caused by this is eliminated, and thus the process difficulty can be reduced and the process controllability can be increased.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (16)
1. A method of fabricating a dual gate SGT semiconductor device comprising the steps of:
forming more than one first groove with a first depth in a selected area of a semiconductor substrate, forming a gate dielectric layer on the inner side surface of the first groove, and then filling a gate conductive material layer in the first groove; forming a trench gate by the gate dielectric layer and the gate conductive material layer filled in the first trench;
step two, performing ion implantation of a second conductivity type in the selected region and advancing to form a body region doped with the second conductivity type, wherein the first groove penetrates through the body region;
step three, carrying out first conductivity type heavy doping ion implantation in the selected area and pushing to form a source area, wherein the second side surface of the source area and the side surface of the first groove are self-aligned;
forming an interlayer film, wherein the interlayer film covers the surface of the semiconductor substrate on which the trench gate, the body region and the source region are formed;
step five, forming a shielding grid, which comprises the following steps:
step 51, defining a second trench forming area, and etching the interlayer film and the semiconductor substrate in the second trench forming area in sequence to form a second trench, wherein the second trench is positioned at two sides of each first trench; the depth of the second groove in the semiconductor substrate is a second depth, and the second depth is larger than the first depth;
step 52, forming a shielding dielectric layer on the inner side surface of the second groove;
step 53, filling metal in the second groove to form a shielding grid field plate;
the shielding grid is formed by the shielding dielectric layer and the shielding grid field plate which are filled in the second groove; and when the device is in reverse voltage resistance, the shielding grid field plates are used for exhausting the drift region formed in the semiconductor substrate and doped with the first conductive type between the shielding grid field plates so as to improve the voltage resistance of the device.
2. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: step two is placed before step one or after step one.
3. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 2, wherein: step three is placed before or after step one, and step three is placed before or after step two.
4. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 3, wherein: in the first step, a first epitaxial layer doped with the first conductivity type is further formed on the surface of the semiconductor substrate, the first groove and the second groove are both located in the first epitaxial layer, and the drift region is composed of the first epitaxial layer located at the bottom of the body region.
5. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: and the shielding dielectric layer is made of an oxide layer.
6. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 5, wherein: in step 52, the shielding dielectric layer is further extended on the surface of the interlayer film outside the second trench;
in step 53, the metal of the shielding gate field plate further extends onto the surface of the shielding dielectric layer outside the second trench;
thereafter, the method further comprises:
and removing the metal of the shielding grid field plate on the surface of the shielding dielectric layer outside the second groove, and leveling the top surface of the shielding grid field plate in the second groove area and the top surface of the shielding dielectric layer outside the second groove, wherein the shielding dielectric layer outside the second groove remains.
7. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 5, wherein: in step 51:
before defining the formation region of the second trench, further comprising forming a protective layer on the surface of the interlayer film;
etching the protective layer in the etching of the second groove, and then etching the interlayer film and the semiconductor substrate;
defining a forming area of the second groove by adopting a photoresist pattern formed by a photoetching process; etching the second groove by using the photoresist pattern as a mask, or etching the second groove by using the patterned protective layer as a mask after transferring the photoresist pattern into the protective layer;
in step 52, the shielding dielectric layer is further extended on the surface of the protection layer outside the second trench; then, removing the shielding dielectric layer outside the second groove and removing the protective layer;
in step 53, the metal of the shielded gate field plate also extends onto the surface of the interlayer film outside the second trench;
thereafter, the method further comprises:
and removing the metal of the shielding gate field plate outside the second trench and leveling the top surface of the shielding gate field plate and the top surface of the interlayer film in the second trench region.
8. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 7, wherein: the protective layer adopts a first nitride layer or adopts an overlapped layer of the first nitride layer and a second oxide layer.
9. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: in step 53, the metal material of the shielded gate field plate includes W, ti, TIN, or Al.
10. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: in the first step, the gate dielectric layer is formed by adopting an oxidation layer and adopting a thermal oxidation process.
11. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: in the first step, the gate conductive material layer is made of polysilicon.
12. The method of fabricating a dual-gate SGT semiconductor device as set forth in claim 1, further comprising, after step five:
forming a contact hole in a selected region, wherein the contact hole penetrates through the interlayer film, and the contact hole is formed on the tops of the source region and the gate conductive material layer;
forming a front metal layer, performing patterned etching on the front metal layer to form a source electrode and a grid electrode, wherein the source region is connected to the source electrode through the contact hole corresponding to the top, and the grid electrode conductive material layer is connected to the grid electrode through the contact hole corresponding to the top; the top of the shielding grid field plate is connected to the source electrode;
forming a contact pad;
and finishing the back surface process.
13. The method of fabricating a dual gate SGT semiconductor device as claimed in claim 12 wherein said backside process comprises:
thinning the back surface of the semiconductor substrate;
the semiconductor substrate is heavily doped with the first conduction type, and the thinned semiconductor substrate is directly used as a heavily doped drain region of the first conduction type; or carrying out back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form a drain region;
and forming a back metal layer on the back of the drain region.
14. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 1, wherein: the semiconductor substrate includes a silicon substrate.
15. The method of fabricating a dual-gate SGT semiconductor device as claimed in claim 12, wherein: a7-layer photomask is used in the process flow of the double-gate SGT semiconductor device and is used for defining the first groove, the body region, the source region, the second groove, the contact hole, the front metal layer pattern and the forming area of the contact liner respectively.
16. A method of fabricating a dual-gate SGT semiconductor device as claimed in any one of claims 1 to 15, wherein: the double-gate SGT semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; alternatively, the dual-gate SGT semiconductor device is a P-type device and the first conductivity type is P-type and the second conductivity type is N-type.
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| CN202310829840.8A CN117012645A (en) | 2023-07-07 | 2023-07-07 | Method for manufacturing double-gate SGT semiconductor device |
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| CN202310829840.8A CN117012645A (en) | 2023-07-07 | 2023-07-07 | Method for manufacturing double-gate SGT semiconductor device |
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