CN116995032A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN116995032A
CN116995032A CN202210446727.7A CN202210446727A CN116995032A CN 116995032 A CN116995032 A CN 116995032A CN 202210446727 A CN202210446727 A CN 202210446727A CN 116995032 A CN116995032 A CN 116995032A
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China
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channel material
layer
material layer
forming
planarization
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王洪岩
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210446727.7A priority Critical patent/CN116995032A/en
Publication of CN116995032A publication Critical patent/CN116995032A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region for forming a first device and a second region for forming a second device, and a first channel material layer formed on the substrate, and the first channel material layer is used for forming a channel of the first device; sequentially forming a stacked planarization stop layer, a protective layer and a hard mask layer on the first channel material layer; forming openings in the planarization stop layer, the protective layer, the hard mask layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of a second device; removing the hard mask layer; removing the hard mask layer, and performing oxidation removal treatment on the surface of the second channel material layer; after the deoxidation treatment, the planarization stop layer, the protection layer and the second channel material layer which are higher than the top surface of the first channel material layer are subjected to planarization treatment. The embodiment of the invention is beneficial to improving the performance of the semiconductor device.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
The fabrication of semiconductor integrated circuits (Integarted circuit, ICs) utilizes a series of processes such as photolithography, etching, implantation, and deposition to form a large number of various types of complex devices on the same substrate and interconnect them to have complete electronic functions. With the rapid development of ultra-large-scale integrated circuits, the integration level of chips is higher and higher, the size of components is smaller and smaller, and the influence of various effects caused by high density and small size of components on the manufacturing result of semiconductor processes is also increasingly prominent.
The flatness of the wafer plays a critical role in the quality of the semiconductor device. A wafer with poor flatness can adversely affect the device manufacturing process. Such as: uneven contact between the uneven wafer and the substrate during the epitaxial growth process can cause uneven thermal field distribution on the wafer surface, thereby causing uneven stress distribution within the wafer.
Currently, the performance of semiconductor devices is to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which improves the performance of a semiconductor device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base comprising a substrate and a first channel material layer formed on the substrate, wherein the base comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device; sequentially forming a stacked planarization stop layer, a protective layer and a hard mask layer on the first channel material layer; forming openings in the hard mask layer, the protective layer, the planarization stop layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device; removing the hard mask layer; after the hard mask layer is removed, performing oxidation removal treatment on the surface of the second channel material layer; and after the deoxidation treatment, carrying out planarization treatment on the planarization stop layer, the protective layer and the second channel material layer which are higher than the top surface of the first channel material layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the protective layer is added between the planarization stop layer and the hard mask layer, so that when the surface of the second channel material layer is subjected to the oxidation removal treatment, the protective layer protects the planarization stop layer, and the process window for the oxidation removal treatment can be increased, so that the probability of oxide remained on the surface of the second channel material layer is reduced, further, the subsequent planarization treatment of the planarization stop layer, the protective layer and the second channel material layer which are higher than the top surface of the first channel material layer is facilitated, the problem that the removal rate of the second channel material layer in each region is inconsistent due to overlarge difference of the removal rates of the oxide and the second channel material layer is avoided, namely, the uniformity of the removal rate of the second channel material layer in each region is facilitated to be improved, the flatness of the second channel material layer after the planarization treatment is further improved, and the performance of a semiconductor device is correspondingly facilitated to be improved.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the performance of the semiconductor device is required to be improved. The reason why the performance of a semiconductor device is to be improved is now analyzed in conjunction with a method of forming a semiconductor structure.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a base 100 is provided, including a substrate 1001 and a first channel material layer 1002 formed on the substrate 1001, the base 100 including a first region I for forming a first device and a second region II for forming a second device, the first channel material layer of the first region I being for forming a channel of the first device.
Referring to fig. 2, a mask stack 180 including a planarization stop layer 101 and a hard mask layer 103 stacked in order from bottom to top is formed on the substrate 100.
Referring to fig. 3, in the second region II, an opening 110 in the hard mask layer 103 and the first channel material layer 1002 is formed.
Referring to fig. 4, a second channel material layer 111 is filled in the opening 110, and the second channel material layer 111 is used to form a channel of the second device.
Referring to fig. 5, the hard mask layer 103 is removed.
Referring to fig. 6, the second channel material layer 111 is planarized.
When the hard mask layer 103 is removed, the surface of the second channel material layer 111 is easily oxidized, thereby forming an oxide (not shown) on the surface of the second channel material layer 111. When the second channel material layer 111 is planarized, the removal rate of the oxide is lower than the removal rate of the second channel material layer 111, and there is a possibility that the thicknesses of the oxide in the respective regions are inconsistent, so that the removal rate of the second channel material layer 111 in the respective regions is inconsistent, which results in lower flatness of the second channel material layer 111 after the planarization, and thus, performance degradation of the semiconductor device is easily caused.
In order to solve the technical problem, the embodiment of the invention also provides a method for forming a semiconductor structure, which comprises a substrate and a first channel material layer formed on the substrate, wherein the substrate comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device; sequentially forming a stacked planarization stop layer, a protective layer and a hard mask layer on the first channel material layer; forming openings in the hard mask layer, the protective layer, the planarization stop layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device; removing the hard mask layer; after the hard mask layer is removed, performing oxidation removal treatment on the surface of the second channel material layer; and after the deoxidation treatment, carrying out planarization treatment on the planarization stop layer, the protective layer and the second channel material layer which are higher than the top surface of the first channel material layer.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the protective layer is added between the planarization stop layer and the hard mask layer, so that when the surface of the second channel material layer is subjected to the oxidation removal treatment, the protective layer protects the planarization stop layer, and the process window for the oxidation removal treatment can be increased, so that the probability of oxide remained on the surface of the second channel material layer is reduced, further, the subsequent planarization treatment of the planarization stop layer, the protective layer and the second channel material layer which are higher than the top surface of the first channel material layer is facilitated, the problem that the removal rate of the second channel material layer in each region is inconsistent due to overlarge difference of the removal rates of the oxide and the second channel material layer is avoided, namely, the uniformity of the removal rate of the second channel material layer in each region is facilitated to be improved, the flatness of the second channel material layer after the planarization treatment is further improved, and the performance of a semiconductor device is correspondingly facilitated to be improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a base 200 is provided, comprising a substrate 2001 and a first channel material layer 2002 formed on the substrate 2001, the base 200 comprising a first region I for forming a first device, the first channel material layer of the first region I being for forming a channel of the first device, and a second region II for forming a second device.
The substrate 200 is used to provide a process platform for forming semiconductor structures.
In this embodiment, the substrate 200 is a silicon substrate, i.e., the material of the substrate 200 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The substrate 2001 is used to provide support for subsequently formed fins and to provide a process platform for subsequent processes that are formed after the fins are formed.
The first channel material layer 2002 is then patterned to form channels of the first device.
In this embodiment, the material of the first channel material layer is silicon, and in other embodiments, the material of the first channel material layer may also be silicon germanium.
In this embodiment, the first device is an NMOS device, and the second device is a PMOS device.
The first channel material layer 2002 is used for forming a channel of a first device later, and the substrate 200 is a silicon substrate, so that the substrate 200 can meet the requirements of an NMOS device for channel materials.
In other embodiments, the first device may be a PMOS device and the second device may be an NMOS device.
In other embodiments, the first device and the second device may also be devices having the same channel conductivity type (e.g., both NMOS devices or both PMOS devices), but different channel materials.
In this embodiment, the base 200 includes a substrate 2001 and a first channel material layer 2002 formed on the substrate 2001, where the substrate 2001 and the first channel material layer 2002 are integrally formed.
In other embodiments, the first channel material layer may be a film layer of another material formed on the substrate by an epitaxial process according to actual process requirements.
It should be noted that, in this embodiment, the substrate 200 includes a pattern sparse region (not labeled) and a pattern dense region (not labeled), the pattern density of the pattern sparse region is lower than that of the pattern dense region, and the pattern dense region and the pattern sparse region both include the first region and the second region.
Specifically, the pattern sparse region is a region with smaller opening size which is subsequently formed in the first channel material layer 2002; the pattern-dense region is a region where the opening size subsequently formed in the first channel material layer 2002 is large.
Referring to fig. 8, a planarization stop layer 201, a protective layer 202, and a hard mask layer 203 are sequentially formed on the first channel material layer 2002.
When the top surface of the planarization stop layer 201 is used for removing the protective layer 202 by a planarization process, the substrate 200 and the second channel material layer 211 are protected, thereby reducing damage to the substrate 200 and the second channel material layer 211.
In addition, the top surface of the planarization stop layer 201 can define a stop position when patterning the hard mask layer 203 and the protective layer 202 later, thereby reducing the probability of damage to the substrate 200 and the second channel material layer 211.
As an example, the material of the planarization stop layer 201 is silicon oxide. In other embodiments, the material of the planarization stop layer 201 further includes: silicon nitride, a low dielectric constant (LowK) dielectric layer, a metal oxide, and a metal nitride. Here, low dielectric constant means that the dielectric constant k is less than 3.9.
The protective layer 202 is used to protect the planarization stop layer 201 and the substrate 200.
Specifically, when the surface of the second channel material layer 211 is subjected to the subsequent oxidation removal treatment, the protection layer 202 can protect the planarization stop layer 201, so that when the material of the planarization stop layer 201 is silicon oxide, the probability that the oxidation treatment causes the misetching to the planarization stop layer 201 is reduced, the probability that the exposed substrate 200 is further damaged due to the removal of the planarization stop layer 201 is correspondingly reduced, and the process window for the subsequent oxidation treatment and the planarization treatment to the second channel material layer 211 is advantageously enlarged.
In this embodiment, the material of the protective layer 202 satisfies: the subsequent oxidation treatment has a higher etching selectivity ratio to the oxide and the protective layer 202, so that when the subsequent oxidation removal treatment is performed, the etching loss of the protective layer 202 is reduced, and the protective layer 202 is ensured to be capable of protecting the planarization stop layer 201 and the substrate 200. And, when the planarization stop layer 201, the protection layer 202 and the second channel material layer 211, which are higher than the top surface of the first channel material layer 2002, are subsequently planarized, the removal rates of the protection layer 202 and the second channel material layer are similar, so that the protection layer 202 is removed while the second channel material layer is removed when the planarization stop layer 202 and the second channel material layer are subsequently planarized. Thus, the materials of the protective layer 202 include: one or more of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. As an example, the material of the protective layer 202 is monocrystalline silicon.
It should be noted that, the thickness of the protective layer 202 should not be too small or too large, if the thickness of the protective layer 202 is too small, then, when the subsequent oxidation removal treatment is performed, the mis-etching of the planarization stop layer 201 and the substrate 200 located under the protective layer 202 is easily caused, which is not beneficial to ensure that the protective layer 202 can protect the planarization stop layer 201 and the substrate 200; if the thickness of the protective layer 202 is too large, the time required for removing the protective layer 202 later is increased, which is disadvantageous in terms of saving the process cost. For this purpose, in the present embodiment, the thickness of the protective layer 202 is 30 angstromsTo 200 angstroms.
The hard mask layer 203 is used as an etching mask for forming openings later.
In this embodiment, the material of the hard mask layer 203 is silicon nitride.
In this embodiment, the process of forming the planarization stop layer 201, the protection layer 202 and the hard mask layer 203 is a chemical vapor deposition process, so that the formation of the planarization stop layer 201, the protection layer 202 and the hard mask layer 203 with dense and uniform film layers is facilitated, and the process of forming the planarization stop layer 201, the protection layer 202 and the hard mask layer 203 is the same, so that the improvement of process compatibility is facilitated.
In other embodiments, the process of forming any one of the planarization stop layer 201, the protective layer 202, and the hard mask layer 203 further includes a furnace tube process or an epitaxial process.
Referring to fig. 9, in the second region, an opening 210 is formed in the hard mask layer 203, the protective layer 202, the planarization stop layer 201, and the first channel material layer 2002.
The openings 210 are used to provide a forming space for a subsequent formation of a second channel material layer.
Specifically, a photoresist layer (not shown) is formed on the hard mask layer 203 before forming the openings 210 in the planarization stop layer 201, the protective layer 202, the hard mask layer 203, and the first channel material layer 2002;
and patterning the photoresist layer by means of exposure and development to form a pattern layer. Specifically, the photoresist layer may be formed by coating.
The photoresist layer is converted into a pattern layer (not shown) by means of exposure and development, thereby defining the location of the opening 210.
In this embodiment, the hard mask layer 203 is etched by using the pattern layer as a mask; accordingly, the etching of the protection layer 202, the planarization stop layer 201, and the first channel material layer 2002 is continued with the remaining hard mask layer 203 after the etching as a mask, so as to form openings 210 in the hard mask layer 203, the protection layer 202, the planarization stop layer 201, and the first channel material layer 2002.
It should be noted that, in other embodiments, after etching the first channel material layer in the second region, a portion of the thickness of the substrate may also be etched, so that the bottom of the opening is located in the portion of the thickness of the substrate.
Referring to fig. 10, a second channel material layer 211 is filled in the opening 210, and the second channel material layer 211 is used to form a channel of the second device.
The second channel material layer 211 is then patterned to form a channel of the second device.
In this embodiment, the second channel material layer 211 is formed by an epitaxial process, and in other embodiments, the process of forming the second channel material layer 211 further includes a chemical vapor deposition process, a furnace tube process, or an atomic layer deposition process.
In this embodiment, the top surface of the second channel material layer 211 is higher than the top surface of the first channel material layer 2002, so that it is beneficial to provide enough process windows for the subsequent planarization treatment of the second channel material layer 211, and further to improve the flatness of the top surfaces of the second channel material layer 211 and the first channel material layer 2002 after the planarization treatment.
The material of the second channel material layer 211 is determined according to the performance requirement of the second device. In this embodiment, the second device is a PMOS device, and therefore, the material of the second channel material layer 211 is silicon germanium. In other embodiments, the second channel material layer 211 may also be formed of silicon.
Referring to fig. 11, the hard mask layer 203 is removed.
The hard mask layer 203 is removed, thereby providing a process basis for subsequent planarization of the second channel material layer 211.
In this embodiment, after the second channel material layer 211 is filled in the opening 210, the hard mask layer 203 is removed, and during the process of performing an epitaxial process in the opening 210 to form the second channel material layer 211, the probability of performing epitaxial growth on the surface of the hard mask layer 203 on the second channel material layer 211 is low, so that the formation position of the second channel material layer 211 is limited in the opening 210.
Referring to fig. 12, after the hard mask layer 203 is removed, planarization is performed on the planarization stop layer 201, the protection layer 202, and the second channel material layer 211, which are higher than the top surface of the first channel material layer 2002.
When the planarization stop layer 201, the protection layer 202 and the second channel material layer 211 above the top surface of the first channel material layer 2002 are subjected to planarization, the protection layer 202 can protect the planarization stop layer 201, and can increase a process window for performing deoxidation treatment, so that the probability that oxide remains on the surface of the second channel material layer 211 is reduced, further, when the planarization stop layer 201, the protection layer 202 and the second channel material layer 211 above the top surface of the first channel material layer 2002 are subjected to subsequent planarization, the problem that the removal rates of the second channel material layer 211 in each region are inconsistent due to overlarge difference between the removal rates of the oxide 204 and the second channel material layer 211 is avoided, namely, the uniformity of the removal rate of the second channel material layer 211 in each region is improved, the flatness of the second channel material layer 211 after planarization is improved, and the performance of a semiconductor device is improved correspondingly.
Specifically, in this embodiment, the surface of the second channel material layer 211 is easily oxidized during the removal of the hard mask layer 203, and therefore, after the removal of the hard mask layer 203, the oxidation treatment is performed, so that the oxide 204 formed on the surface of the second channel material layer 211 due to the oxidation during the removal of the hard mask layer 203 can be removed.
In this embodiment, the pattern density of the pattern sparse region is lower than that of the pattern dense region, and the region with a sparse pattern density is easier to form the oxide 204, which is easy to cause that the oxide 204 formed on the pattern sparse region is more than the oxide 204 of the pattern dense region, and further, when the planarization process is performed on the second channel material layer 211 subsequently, the difference of the removed rates of the oxide 204 and the second channel material layer 211 affects the pattern sparse region greatly, so in this embodiment, by performing the deoxidation process on the surface of the second channel material layer 211 before the planarization process, even if the pattern sparse region and the pattern dense region exist, the top surface flatness and the height uniformity of the second channel material layer in the pattern sparse region and the pattern dense region are also favorable to be improved after the planarization process.
In this embodiment, the manner of performing the oxidation removal treatment on the surface of the second channel material layer 211 includes etching treatment.
In this embodiment, the etching process is a wet etching process, so that the oxide 204 is uniformly etched, and the second channel material layer 211 is less damaged. Specifically, the etching solution adopted by the wet etching process comprises the following components: hydrofluoric acid solution.
In other embodiments, the etching process may also be a dry etching process. The etching gas adopted by the dry etching process comprises the following components: hydrogen Fluoride (HF), carbon tetrafluoride (CF) 4 ) Octafluoropropane (CF) 8 ) Or trifluoromethane (CHF) 3 )。
Referring to fig. 13, after the deoxidation process, a planarization process is performed on the planarization stop layer 201, the protective layer 202, and the second channel material layer 211, which are higher than the top surface of the first channel material layer 2002.
The planarization stop layer 201, the protection layer 202 and the second channel material layer 211, which are higher than the top surface of the first channel material layer 2002, are planarized to provide a process basis for the formation of a subsequent film layer (e.g., patterning the second channel material layer 211 and the substrate 200 to form fins (not shown) protruding above the remaining thickness of the substrate).
In this embodiment, the planarization process is a chemical mechanical polishing process. In other embodiments, other types of processes may also be employed for the planarization process.
In this embodiment, the material of the protective layer 202 includes one or more of monocrystalline silicon, polycrystalline silicon and amorphous silicon, the material of the first channel material layer 2002 is silicon, and the planarization stop layer 201 is used for isolating the protective layer 202 and the first channel material layer 2002 and protecting the first channel material layer 2002, so that the protective layer 202 and the first channel material layer 2002 can be distinguished, and the probability of damaging the first channel material layer 2002 is reduced while the protective layer 202 is removed.
In this embodiment, the planarizing the second channel material layer 211 includes: performing a first planarization process on the protective layer 202 and the second channel material layer 211 with the top surface of the planarization stop layer 201 as a stop position; after the first planarization process, a second planarization process is performed on the planarization stop layer 201 and the second channel material layer 211.
Specifically, when the difference between the height of the second channel material layer 211 and the top surface of the substrate 200 is large, a first planarization process is performed first, and the removal rate of the first planarization process to the second channel material layer 211 is large, so that it is beneficial to quickly removing the second channel material layer 211, reducing the difference between the height of the second channel material layer 211 and the top surface of the substrate 200, and improving the flatness of the top surface of the second channel material layer 211 in each region after the first planarization process, so as to improve the efficiency of the planarization process to the second channel material layer 211, and improve the flatness of the top surfaces of the second channel material layer 211 and the substrate 200 after the second planarization process.
In this embodiment, in the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the protection layer 202 is not too small, nor too large; if the ratio of the removal rates of the second channel material layer 211 and the protection layer 202 is too small, the removal rate of the second channel material layer 211 is low, and the surface height of the second channel material layer 211 is higher than the top surface height of the protection layer 202, it is difficult to quickly remove the second channel material layer 211 higher than the top surface of the planarization stop layer 201, which is unfavorable for performing the planarization process on the second channel material layer 211; if the ratio of the removal rates of the second channel material layer 211 and the protection layer 202 is too large, the removal rate of the protection layer 202 is easy to be too small, and in order to remove the protection layer 202 and the second channel material layer 211 that are higher than the top surface of the planarization stop layer 201, the process time of the first planarization treatment is easy to be too long, so that the influence of the first planarization treatment on the second channel material layer 211 is increased, and the thickness of the second channel material layer 211 is too small. For this reason, in the present embodiment, in the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the protective layer 202 is 0.8 to 1.2.
In the present embodiment, in the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is not preferably too small, and if the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too small, the planarization stop layer 201 is easily damaged when the second channel material layer 211 is removed, so that it is difficult to define the stop position of the first planarization process by the top surface of the planarization stop layer 201. For this reason, in the present embodiment, in the first planarization process, the removal rate ratio of the second channel material layer 211 to the planarization stop layer 201 is greater than 5.
After the first planarization process, a second planarization process is performed on the planarization stop layer 201 and the second channel material layer 211, so that the second planarization stop layer 201 and the second channel material layer 211 are performed when a difference in height between the second channel material layer 211 and the top surface of the substrate 200 is small.
Specifically, the second planarization process has a smaller difference in the removal rates of the second channel material layer 211 and the planarization stop layer 201, so that it is advantageous to perform the planarization process on the second channel material layer 211 and the planarization stop layer 201 at a smaller rate, and thus to improve the uniformity of the time required to remove the second channel material layer 211 and the planarization stop layer 201, and to more precisely control the stop time of the planarization process.
In the present embodiment, in the second planarization process, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is not preferably too small or too large. If the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too small, the removal rate of the second channel material layer 211 is too low, and the planarization stop layer 201 is removed first, thereby increasing the probability of damage to the first channel material layer 2002. If the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too large, the removal rate of the second channel material layer 211 is too large, and accordingly, more time is required to remove the planarization stop layer 201, in which the removal amount of the second channel material layer 211 is easily caused to be too large, which is rather disadvantageous to improve the surface flatness of the second channel material layer 211. For this reason, in the present embodiment, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is 0.8 to 1.2.
In other embodiments, when the surface height of the second channel material layer is similar to the top surface height of the protection layer, the planarization stop layer, the protection layer, and the second channel material layer may be subjected to a third planarization process in the same planarization step.
Specifically, the difference of the removal rates of the second channel material layer and the protection layer by the third planarization process is smaller, so that the planarization process is performed on the second channel material layer and the protection layer at the similar removal rate, and further, the consistency of the time required for removing the protection layer and the second channel material layer higher than the top surface of the planarization stop layer is improved, and the stop time of the planarization process is controlled more accurately.
In this embodiment, after the planarization process is performed on the second channel material layer 211, the method further includes: the second channel material layer 211 and the base 200 are patterned to form fins (not shown) protruding over the remaining thickness of the substrate, the fins being located on the remaining thickness of the substrate in the first region I and the second region II, respectively.
As one example, the first channel material layer 2002, the second channel material layer 211, and a portion of the thickness of the substrate are patterned to form fins protruding above the remaining thickness of the substrate.
Accordingly, the first channel material layer 2002 is used to form a fin located in the first region I, and the second channel material layer 211 is used to form a fin located in the second region II, so that the first device formed in the first region I and the second device formed in the second region II have channels of different materials.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A method of forming a semiconductor structure, comprising:
providing a base comprising a substrate and a first channel material layer formed on the substrate, wherein the base comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device;
sequentially forming a stacked planarization stop layer, a protective layer and a hard mask layer on the first channel material layer;
forming openings in the hard mask layer, the protective layer, the planarization stop layer and the first channel material layer in the second region;
filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device;
removing the hard mask layer;
after the hard mask layer is removed, performing oxidation removal treatment on the surface of the second channel material layer;
and after the deoxidation treatment, carrying out planarization treatment on the planarization stop layer, the protective layer and the second channel material layer which are higher than the top surface of the first channel material layer.
2. The method of forming a semiconductor structure of claim 1, wherein the performing a de-oxidation process on the surface of the second channel material layer comprises etching.
3. The method of forming a semiconductor structure of claim 1, wherein the process of forming the protective layer comprises: a chemical vapor deposition process, a furnace tube process, or an epitaxial process.
4. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer comprises: one or more of monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
5. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the protective layer, the protective layer has a thickness of 30 angstroms to 200 angstroms.
6. The method of forming a semiconductor structure of claim 2, wherein the etching process is a wet etching process, and the etching solution used in the wet etching process comprises: a hydrofluoric acid solution; or the etching treatment process is a dry etching process, and etching gas adopted by the dry etching process comprises the following components: hydrogen fluoride, carbon tetrafluoride, octafluoropropane or trifluoromethane.
7. The method of forming a semiconductor structure of claim 1, wherein planarizing the planarization stop layer, the protective layer, and the second channel material layer above the top surface of the first channel material layer comprises:
taking the top surface of the planarization stop layer as a stop position, and performing first planarization treatment on the protective layer and the second channel material layer; after the first planarization treatment, carrying out second planarization treatment on the planarization stop layer and the second channel material layer;
or, in the same planarization step, performing a third planarization process on the planarization stop layer, the protection layer and the second channel material layer.
8. The method of forming a semiconductor structure of claim 7, wherein in the first planarization process, a ratio of removal rates for the second channel material layer and the protective layer is 0.8 to 1.2, and a ratio of removal rates for the second channel material layer and the planarization stop layer is greater than 5;
in the second planarization process, a ratio of removal rates of the second channel material layer and the planarization stop layer is 0.8 to 1.2.
9. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein in the step of filling the opening with a second channel material layer, a top surface of the second channel material layer is higher than a top surface of the first channel material layer.
10. The method of forming a semiconductor structure of any of claims 1-8, wherein the hard mask layer is removed after filling the opening with a second channel material layer.
11. The method of forming a semiconductor structure of any one of claims 1-8, wherein the material of the first channel material layer comprises silicon or silicon germanium and the material of the second channel material layer comprises silicon germanium or silicon.
12. The method of forming a semiconductor structure of any one of claims 1-8, wherein the substrate comprises a pattern sparse region and a pattern dense region, the pattern sparse region has a pattern density lower than a pattern density of the pattern dense region, and the pattern dense region and the pattern sparse region each comprise the first region and the second region.
CN202210446727.7A 2022-04-26 2022-04-26 Method for forming semiconductor structure Pending CN116995032A (en)

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