CN116978954A - Groove type MOSFET device and manufacturing method - Google Patents
Groove type MOSFET device and manufacturing method Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The application discloses a groove type MOSFET device and a manufacturing method thereof, wherein the groove type MOSFET device comprises a source electrode, a grid electrode, a drain electrode, a source electrode region and a substrate, wherein the drain electrode, the source electrode and the grid electrode are positioned on the same side of the source electrode region; the drain contacts the substrate through the TSV. According to the application, the drain electrode at the bottom of the trench MOSFET device is connected to one side of the source electrode and the grid electrode through the TSV and is contacted with the substrate, and an extra device is not needed to lead out the pins of the drain electrode during packaging, so that the area and thickness of packaging are reduced.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a groove type MOSFET device and a manufacturing method thereof.
Background
One example of a semiconductor device is a metal oxide silicon field effect transistor device, known as a MOSFET device, which is used in many electronic devices including power supplies, automotive electronics, computers, and disk drives. MOSFET devices may be used in many applications, for example, in switches that connect a power source to a particular electronic device having a load. The MOSFET device can be formed in a trench that has been etched into the substrate or etched into the epitaxial layer. The MOSFET device operates by applying an appropriate voltage to the gate electrode of the MOSFET device, which turns the device on and forms a channel connecting the source and drain of the MOSFET device, allowing current to flow.
The power semiconductor device is used as a core power electronic device for power control and is applied to conversion and control of electric energy. In recent years, the demand of various fields such as new energy automobiles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, air conditioners and the like for power semiconductor devices is greatly increased, and the rapid development of the fields is promoted. The MOSFET is used as an important power semiconductor device, the grid electrode of the MOSFET can be switched on and off through voltage control, and the MOSFET has the advantages of high input impedance and low conduction loss, and is widely applied to the fields of switching power supplies, motor control, mobile communication and the like.
With the development of electronic manufacturing industry, the MOSFET is developed towards ultra-thin and miniaturized, and the trench MOSFET is a novel MOSFET device with a vertical structure which is optimized and developed from the conventional planar MOSFET structure. The source and gate of a conventional trench MOSFET device are located on top of the device and the drain is located at the bottom of the device and in contact with the substrate. The device structure with the source metal and the gate metal on different sides and the drain metal leads to the need of connecting the drain electrode to the front surface of the device by using a lead frame or a copper clip in the packaging process of the trench MOSFET device and then connecting the drain electrode with the PCB, and the processing packaging mode increases the packaging area and the packaging thickness of the MOSFET.
Disclosure of Invention
In order to solve at least one technical problem, the application aims to provide a trench MOSFET device and a manufacturing method thereof, wherein a drain electrode at the bottom of the trench MOSFET device is connected to one side of a source electrode and a grid electrode through a TSV and is contacted with a substrate, and an extra device is not needed to lead out a pin of the drain electrode during packaging, so that the area and the thickness of packaging are reduced.
The application adopts the following technical scheme:
in a first aspect, the present application provides a trench MOSFET device comprising a source, a gate, a drain, a source region, and a substrate, the drain being on the same side of the source region as the source and the gate; the drain contacts the substrate through the TSV.
Preferably, the semiconductor device further comprises an epitaxial layer and a body region, wherein the body region is positioned above the epitaxial layer;
the epitaxial layer is positioned above the substrate;
the body region is located below the source region;
the source region is in contact with a source.
Preferably, the semiconductor device further comprises a trench, the trench penetrates through the source region and the body region, the bottom of the trench is located inside the epitaxial layer, a gate oxide layer is arranged on the inner wall of the trench, and the gate oxide layer is in contact with the gate.
Preferably, the substrate is an n+ type substrate;
the epitaxial layer is an N-type epitaxial layer;
the body region is a P-type body region;
the source region is an N+ source region.
Preferably, the substrate is a p+ type substrate;
the epitaxial layer is a P-type epitaxial layer;
the body region is an N-type body region;
the source region is a P+ type source region.
Preferably, the diameter of the through hole of the TSV is 2-10um.
Preferably, the aspect ratio of the TSV is 3:1-15:1.
preferably, the filling material of the TSV is copper.
In a second aspect, the present application provides a method for manufacturing a trench MOSFET device, including:
depositing an epitaxial layer over a substrate;
forming a body region and a source region over the epitaxial layer;
a first through hole is formed in the source region and the body region, a groove is formed in the upper layer of the epitaxial layer, and the first through hole is connected with the groove;
and performing TSV processing.
Preferably, performing TSV processing includes:
a second through hole is formed in the source electrode region, and the bottom of the second through hole is located in the substrate;
depositing an insulating layer on the side wall of the second through hole;
depositing a barrier layer on the side wall of the second through hole;
filling the second through hole;
and the metal above the second through hole is connected with the substrate through the second through hole to form a drain electrode.
Compared with the prior art, the application has the beneficial effects that:
according to the application, the drain electrode at the bottom of the trench MOSFET device is connected to one side of the source electrode and the grid electrode through the TSV and is contacted with the substrate, and an extra device is not needed to lead out the pins of the drain electrode during packaging, so that the area and thickness of packaging are reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of a trench MOSFET device according to an embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing a trench MOSFET device according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present application.
The power semiconductor device is used as a core power electronic device for power control and is applied to conversion and control of electric energy. In recent years, the demand of various fields such as new energy automobiles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, air conditioners and the like for power semiconductor devices is greatly increased, and the rapid development of the fields is promoted. The MOSFET is used as an important power semiconductor device, the grid electrode of the MOSFET can be switched on and off through voltage control, and the MOSFET has the advantages of high input impedance and low conduction loss, and is widely applied to the fields of switching power supplies, motor control, mobile communication and the like.
With the development of electronic manufacturing industry, the MOSFET is developed towards ultra-thin and miniaturized, and the trench MOSFET is a novel MOSFET device with a vertical structure which is optimized and developed from the conventional planar MOSFET structure. The source and gate of a conventional trench MOSFET device are located on top of the device and the drain is located at the bottom of the device and in contact with the substrate. The device structure with the source metal and the gate metal on different sides and the drain metal leads to the need of connecting the drain electrode to the front surface of the device by using a lead frame or a copper clip in the packaging process of the trench MOSFET device and then connecting the drain electrode with the PCB, and the processing packaging mode increases the packaging area and the packaging thickness of the MOSFET. According to the application, the drain electrode at the bottom of the trench MOSFET device is connected to one side of the source electrode and the grid electrode through the TSV and is contacted with the substrate, and an extra device is not needed to lead out the pins of the drain electrode during packaging, so that the area and thickness of packaging are reduced.
Example 1
The application provides a groove type MOSFET device, which comprises a source electrode, a grid electrode, a drain electrode, a source electrode region and a substrate, wherein the drain electrode, the source electrode and the grid electrode are positioned on the same side of the source electrode region; the drain contacts the substrate through the TSV.
Trench MOSFETs are a common type of field effect transistor. The basic structure of a trench MOSFET includes a source, a drain, a gate, and a channel. Wherein the channel between the source and the drain is a channel through which current flows, and the gate is a switch that controls the current in the channel. The source electrode metal and the gate electrode metal of the groove type MOSFET are positioned above the silicon wafer, the lower part of the silicon wafer is a substrate, and the drain electrode is positioned below the silicon wafer and contacted with the substrate. Trench MOSFETs, also known as surface effect transistors, have gates buried in the body to form vertical channels, although their process is complex and cell uniformity is inferior to planar structures. However, the trench structure can increase the cell density, has no JFET effect, has smaller parasitic capacitance, has high switching speed and has very low switching loss; in addition, by selecting a proper channel crystal face and an optimally designed structure, the optimal channel mobility can be realized, and the on-resistance is obviously reduced. The trench MOSFET provided in this embodiment is different from the conventional trench MOSFET in that the drain electrode located at the bottom of the trench MOSFET device is connected to one side of the source electrode and the gate electrode through the TSV and is in contact with the substrate.
Preferably, the semiconductor device further comprises an epitaxial layer and a body region, wherein the body region is positioned above the epitaxial layer;
the epitaxial layer is positioned above the substrate;
the body region is positioned below the source region;
the source region is in contact with the source.
Epitaxy refers to the process of growing a new single crystal on a carefully processed single crystal substrate, which may be the same material as the substrate or a different material (homoepitaxy or heteroepitaxy). The nascent monocrystalline layer is grown in extension from the crystalline phase of the substrate and is thus called an epitaxial layer. The thickness of the epitaxial layer is typically a few microns, for example silicon: silicon epitaxial growth is meant to grow a layer of crystal with good lattice structural integrity having the same crystal orientation as the substrate and different in resistivity and thickness on a silicon single crystal substrate having a certain crystal orientation, and a substrate on which an epitaxial layer is grown is called an epitaxial wafer, i.e., epitaxial wafer = epitaxial layer + substrate. The fabrication of MOSFET devices is spread on the epitaxial layer.
For the traditional silicon semiconductor industry chain, the requirements of high breakdown voltage, small series resistance and small saturation voltage drop of a collector region cannot be met by manufacturing devices on a silicon wafer. While the development of epitaxial technology successfully addresses this difficulty. The epitaxy technology grows a layer of high-resistivity epitaxial layer on a silicon substrate with extremely low resistance, and devices are manufactured on the epitaxial layer, so that the high-resistivity epitaxial layer ensures that a tube has high breakdown voltage, and the low-resistance substrate reduces the resistance of the substrate, so that the saturation voltage drop is reduced, and the contradiction between the high-resistivity epitaxial layer and the low-resistance substrate is solved. In addition, the epitaxial techniques of III-V family, II-VI family and other molecular compound semiconductor materials such as GaAs are greatly developed, and the epitaxial techniques of vapor phase epitaxy, liquid phase epitaxy and the like are also becoming indispensable process techniques for manufacturing most microwave devices, photoelectric devices, power devices and the like, and particularly the successful application of molecular beam and metal organic vapor phase epitaxy techniques in thin layer epitaxy, superlattice epitaxy, quantum well epitaxy, strain superlattice and atomic thin layer epitaxy is laying a rammed foundation for the development of 'energy band engineering' in the new field of semiconductor research.
Preferably, the epitaxial layer further comprises a groove, the groove penetrates through the source region and the body region, the bottom of the groove is located inside the epitaxial layer, a gate oxide layer is arranged on the inner wall of the groove, and the gate oxide layer is in contact with the gate electrode.
The trench refers to a channel region, and the trench type MOSFET can change the performance and characteristics of the transistor by adjusting the size of the trench. In order to form a vertical channel structure, a groove is formed in an epitaxial layer of the groove type MOSFET, an oxide layer is manufactured on the surface of the groove, and polysilicon is filled in the groove to form a grid electrode. This structure embeds the gate into the body, forming a vertical channel, the current path flowing vertically from the lower substrate drain through the epitaxial layer, channel and source region, the channel and current direction being parallel. The difference between the trench MOSFET provided in this embodiment and the conventional trench MOSFET is that the drain metal is disposed in contact with the substrate through the TSV, and the drain metal and the source metal No. two gate metal are located on the same plane.
The gate oxide is a dielectric layer separating the gate from the source and drain of the MOSFET and the conductive channels connecting the source and drain when the transistor is on. The gate oxide layer is a thin silicon dioxide insulating layer formed by thermally oxidizing the silicon of the channel. The insulating silicon dioxide layer is formed by a self-limiting oxidation process described by the Deal-Grove model. A conductive gate material is then deposited over the gate oxide to form the transistor. The gate oxide acts as a dielectric layer so the gate can withstand lateral electric fields up to 1 to 5MV/cm to strongly modulate the conductance of the channel. Above the gate oxide is a thin electrode layer made of a conductor, which may be a refractory metal such as aluminum, highly doped silicon, tungsten, or a silicide (TiSi, moSi2, taSi, or WSi 2) or an interlayer of these layers. The gate electrode is commonly referred to as a gate metal or gate conductor. The geometric width of the gate conductor electrode (transverse to the direction of current flow) is referred to as the physical gate width. The physical gate width may be slightly different from the electrical channel width for an analog transistor because fringe fields can have an effect on conductors that are not directly under the gate.
The electrical characteristics of the gate oxide are critical to the formation of a conductive channel region under the gate. In NMOS type devices, the region under the gate oxide is a thin n-type inversion layer on the surface of a p-type semiconductor substrate. It is caused by the oxide electric field of the applied gate voltage VG. This is called the inversion channel. It is a conductive channel that allows electrons to flow from the source to the drain.
Preferably, the substrate is an n+ substrate;
the epitaxial layer is an N-type epitaxial layer;
the body region is a P-type body region;
the source region is an n+ type source region.
Preferably, the substrate is a p+ substrate;
the epitaxial layer is a P-type epitaxial layer;
the body region is an N-type body region;
the source region is a P+ type source region.
+ is heavily doped (high doping concentration), -is lightly doped (low doping concentration), P-type doped group IIIA element, for example: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and permalloy. Heavily doped semiconductors can be used to fabricate high performance electronic devices with a doping concentration of 10 19 cm -3 The above methods for preparing p+ doping include diffusion and ion implantation methods. The diffusion method comprises mixing impurity ions with semiconductor material, and heating the mixture to high temperature to diffuse the impurity ions into the semiconductor materialIn the conductor material, ion implantation is to accelerate impurity ions to a high speed and then implant them into the semiconductor material. Lightly doped semiconductors refer to semiconductor materials that are made by adding a low concentration of impurity atoms in the preparation of the semiconductor material. The doped impurity atoms can alter the electrical properties of the semiconductor material, thereby improving its performance and functionality. In lightly doped semiconductors, the concentration of impurity atoms incorporated is typically lower than the intrinsic concentration of the semiconductor material (intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The impurity atoms to be incorporated must also have a lattice size and an electronic structure similar to those of the semiconductor material atoms to ensure that they can be smoothly bonded to and move in the semiconductor material. After doping impurity atoms, the electrical properties of the lightly doped semiconductor will change accordingly. The most important of these is the improvement in conductivity. This is because the added impurity atoms may form additional free electrons or holes in the semiconductor, resulting in enhanced conductivity properties of the semiconductor material. In addition, the lightly doped semiconductor can also change the properties of the semiconductor material such as forbidden bandwidth, carrier mobility, optical absorption spectrum and the like, so that the application of the lightly doped semiconductor in the fields of electronics, optoelectronics, chemistry and the like is expanded. The lightly doped semiconductor is prepared by ion implantation, fusion diffusion and other technologies. The ion implantation is to accelerate the doping element to a high speed by a high voltage electric field, then bombard the semiconductor surface, and implant it into the semiconductor lattice. The fusion diffusion is to place the semiconductor chip on the doped material block, then heat to high temperature, and the doped atoms are fused and diffused into the semiconductor material. In practical application, lightly doped semiconductors are widely applied to the fields of circuits, solar cells, nano materials and the like. For example, after silicon is doped with aluminum element, n-type silicon can be formed, the conductivity of which is remarkably improved, and the silicon can be used for manufacturing a p-n junction solar cell. In addition, the lightly doped semiconductor can also be used for preparing microelectronic devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFET), low noise power amplifiers and the like. In the field of nanotechnology, the lightly doped semiconductor can be used for preparing various photoelectron and biochemical sensors, and has wide application prospect.
Preferably, the through hole diameter of the TSV is 2-10um.
The common filler metal copper has a much larger expansion coefficient than silicon, arsenizer and other materials, which easily causes reliability problems. To improve reliability, the smaller the TSV via diameter, the better should be, less than 10um. When the size of the through hole of the TSV is reduced to below 5um, the processing cost and the processing difficulty also need to be considered. The through hole diameter of the TSV of this embodiment is 2-10um.
Preferably, the aspect ratio of the TSV is 3:1-15:1.
the aspect ratio of the TSV is too large, the process is difficult to release, the resistance value is also increased, and the aspect ratio is 10: the transmission performance of the TSV in the 1 time is good. The aspect ratio of the TSV of this embodiment is 3:1-15:1.
preferably, the fill material of the TSV is copper.
The filling material of the TSV comprises metals such as copper, tungsten and nickel or nonmetal such as doped polysilicon. Copper is commonly used as a metal with good conductivity, low electromigration, and low cost for TSV via fill materials.
Example 2
The application provides a manufacturing method of a groove type MOSFET device, which comprises the following steps:
s100, depositing and forming an epitaxial layer above a substrate;
an epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of epitaxially recrystallizing an amorphous layer on a semiconductor single crystal at a temperature below the melting point or eutectic point of the material. The recrystallization process without epitaxy does not belong to solid phase epitaxy. There are two main growth modes of solid phase epitaxy: an amorphous layer is directly contacted with a monocrystalline substrate for epitaxial growth, and another is solid phase epitaxy by sandwiching a layer of metal or carbide between the amorphous layer and the monocrystalline silicon substrate. Metals and carbides act as transport media. There are various methods for forming polycrystalline or amorphous thin films. A method for directly implanting ions includes such steps as high-dose implantation of germanium ions on silicon monocrystal substrate to form GeSi amorphous thin layer, annealing at 475-575 deg.C, and growing again to obtain strain alloy layer. The other is to deposit a thin film, such as evaporation or sputtering. Compared with the common epitaxial method, the solid phase epitaxial substrate has low temperature and small impurity diffusion, and is favorable for manufacturing the epitaxial layer with the abrupt doping interface.
In the vapor phase state, a semiconductor material is deposited on a single crystal wafer such that it grows a single crystal layer having a desired thickness and resistivity along the crystal axis of the single crystal wafer, a process called vapor phase epitaxy. The method is characterized in that: the epitaxial growth temperature is high, and the growth time is long, so that a thicker epitaxial layer can be manufactured; the concentration and conductivity type of the impurities may be arbitrarily changed during the epitaxy process. The common vapor phase epitaxy process for industrial production is as follows: silicon tetrachloride (germanium) epitaxy, silicon (germanium) alkane epitaxy, trichlorosilane, dichlorosilane and the like (dichlorosilane has the advantages of low deposition temperature, high deposition speed, uniform deposition film and the like). Common concepts and principles of silicon vapor phase epitaxy: the silicon is reduced to silicon by chemical reaction or thermal decomposition of gaseous compounds of silicon (such as SiCl4 and SiH 4) with hydrogen gas on the surface of the heated silicon substrate, and deposited on the surface of the silicon substrate in a single crystal form. The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. Vapor phase epitaxy of semiconductors is the process in which a gaseous compound of silicon reacts with hydrogen or thermally decomposes itself to reduce to silicon at the heated substrate surface and deposits on the substrate surface in the form of a single crystal. The method specifically comprises the following steps: the reactant molecules are transferred from the gas phase to the surface of the growth layer in a diffusion manner; the reactant molecules are adsorbed by the growth layer; the adsorbed reactant molecules complete chemical reaction on the surface of the growth layer to produce semiconductors and other byproducts; byproduct molecules are resolved from the surface and discharged out of the reaction cavity along with the airflow; atoms generated by the reaction form a lattice or are added to the lattice to form a single crystal epitaxial layer.
The epitaxial system device includes: the system comprises a gas distribution and control system, a heating and temperature measuring device, a reaction chamber and an exhaust gas treatment device. The technological process includes the following steps: substrate and susceptor processing: the substrate treatment is mainly to remove oxide layer and dust particles on the surface of the substrate wafer, and the substrate is put into a graphite base after washing and drying. The already used graphite susceptor should be subjected to HCI etching in advance to remove the silicon that was left on the previous epitaxy. Preparing a doping agent: the dopant has a gaseous source such as phosphane PH3, borane B2H6, etc.; liquid sources such as POCI3 and BBr3, different devices have different requirements on the resistivity and the conductivity type of the epitaxial layer, and the dosage of the doping source must be precisely controlled according to the resistivity. And (3) epitaxial growth: the main procedures are as follows: charging and ventilation, nitrogen gas and then hydrogen gas are introduced, and then a substrate is heated for heat treatment or HCl polishing, epitaxial growth, hydrogen gas flushing, cooling and nitrogen gas flushing are carried out. And when the temperature of the base is reduced to below 300 ℃, opening the furnace to take tablets. The quality of the vapor phase epitaxy requires that the quality of the epitaxial layer should satisfy: the crystal structure is complete, the resistivity is accurate and uniform, the epitaxial layer thickness is uniform and in-range, the surface is smooth, no oxidation and white fog exist, and surface defects (pyramids, mastoid, star defects, etc.) and in-vivo defects (dislocation, stacking faults, slip lines, etc.) are few. The epitaxial quality inspection content comprises: resistivity, impurity concentration profile, epitaxial layer thickness, minority carrier lifetime, mobility, interlayer dislocation and stacking fault density, surface defects, and the like. Typical test items in production are defect density, resistivity and epitaxial layer thickness. The thickness measuring method of the epitaxial layer comprises a stacking fault method, a grinding angle or rolling groove dyeing method, a direct reading method, an infrared interferometry method and the like. The resistivity measurement method includes four-probe method, three-probe method, capacitance-voltage method and extended resistance method, and the capacitance-voltage method, the extended resistance method and the like are often adopted for epitaxial layers with higher resistivity or thinner thickness.
S200, forming a body region and a source region above the epitaxial layer;
the metal electrode deposition process is classified into chemical vapor deposition and physical vapor deposition. Chemical vapor deposition refers to a process of depositing a coating on a wafer surface by chemical means, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
Physical vapor deposition coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
S300, forming first through holes in the source region and the body region, forming grooves in the upper layer of the epitaxial layer, and connecting the first through holes with the grooves;
s400, TSV processing is performed.
Preferably, performing TSV processing includes:
s401, a second through hole is formed in the source region, and the bottom of the second through hole is located in the substrate;
the processing of through holes on a silicon wafer is the core of TSV technology, including deep reactive ion etching and laser drilling. Deep reactive ion etching is an ion-enhanced chemical reaction. The etching system uses an RF-powered plasma source to obtain ions and chemically reactive radicals. In deep silicon etching, the main source gas used is sulfur hexafluoride, providing a free fluorine plasma with highly reactive properties for high rate etching of silicon. Ions in the plasma are accelerated by an electric field between the plasma and the wafer and are directed toward the wafer with strong directionality. While an etch rate enhancement is achieved in the vertical direction, additional gas is also required to clock the etched sidewalls in order to achieve a highly anisotropic etch effect. There are two methods to provide sidewall passivation protection for deep silicon etching, the first is the traditional method, additional gases such as O2 and HBr are mixed with SF6, such steady state processes generally require the use of a hard mask of SiO2, the second is the Bosch process, during each etch cycle, the exposed silicon is isotropically etched by SF6, then a polymer protection layer is deposited on the via inner wall through C4F8, then the polymer is decomposed and removed, the exposed silicon is etched again, and the rapid cycle switching etching and passivation is repeated until the via reaches the process requirement, leaving scalloped undulations on the via sidewall during each etch cycle. The laser drilling technology is used as a process without a mask, and the process steps of photoresist coating, photoetching exposure, developing, photoresist removing and the like are avoided.
S402, depositing an insulating layer on the side wall of the second through hole;
an insulating layer must be deposited before the metal fill is completed to block the electrical conduction between the fill metal and the silicon body material. The material of the through hole insulating layer is silicon oxide, silicon nitride, polymer, etc. Different insulating layers require different deposition techniques. The PECVD technology has high deposition rate, low process temperature and strong film covering capability, and is widely applied to SiO deposition 2 、Si 3 N 4 And insulating materials. The vacuum vapor deposition technology is based on the principle that a gaseous precursor is converted into a solid material in a vacuum environment, the gaseous precursor is heated to a sublimation temperature to produce gaseous molecules, and then the gaseous molecules are conveyed to the surface of a substrate material to be coated, and chemical reaction occurs on the surface to generate a solid film. In the process, because no gas molecules are in the vacuum environment to diffuse or interfere with the reaction, a high-purity and high-quality film can be obtained and is commonly applied to the Parylene material.
S403, depositing a barrier layer on the side wall of the second through hole;
typically, the TSV is filled with a via using an electroplated copper process. The use of copper as a filler material suffers from the following drawbacks: copper diffuses rapidly in silicon dioxide medium, which is easy to degrade dielectric property; copper has a strong trap effect on the carrier of the semiconductor, and the diffusion of copper into the semiconductor bulk material can seriously affect the electrical characteristics of the semiconductor device; copper and silicon dioxide adhere poorly. Therefore, a diffusion barrier layer must be deposited between the copper and the insulating layer to prevent copper diffusion and to increase the adhesion of copper. Common deposition techniques include PVD, magnetron sputtering and PECVD, and common barrier layer materials are Cu, cr, ta and their compounds, ti and their compounds, and the like. PVD coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of PVD are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
S404, filling the second through hole;
the through-hole copper filling technology includes magnetron sputtering, CVD, ALD, electroplating and the like. In industrial production, the electroplating cost is lower and the deposition speed is higher, and the copper electroplating process becomes the first choice for filling the TSV through hole. Copper electroplating techniques typically employ a "bottom-up" electroplating process. The bottom-up electroplating technology can inhibit the deposition rate of the outer surface of the through hole during electroplating to accelerate the deposition in the through hole, and is realized by developing special electroplating additives, special electroplating equipment structures, special design of an electric field and other technical means. Specifically, a strong adsorption force inhibitor covers the atomic positions of the copper surface to inhibit surface copper deposition; the accelerator component is used for counteracting the action of the inhibitor to accelerate the deposition rate of copper at the bottom of the through hole; the leveling agent inhibits deposition of a high electric field region caused by surface curvature distribution and inhibits rapid nucleation of convex surface positions; the accelerator component gathers at the bottom of the via to counteract the effect of the inhibitor to accelerate the deposition rate of copper at the bottom of the via; optimizing the structure and specially designing the electric field, reducing the thickness of the fluid boundary, reducing the concentration of the accelerator on the surface of the wafer, and reducing the copper deposition rate; and electroplating is carried out by adopting periodic pulse reverse current, so that the growth of the sharp surface on the inner wall of the through hole is inhibited.
After the through-hole copper plating, a thicker, non-uniform copper layer is also deposited on the wafer surface, requiring the removal of excess copper and planarization by CMP techniques. The copper CMP technique mainly comprises: the oxidant in the alkaline polishing solution reacts with the copper surface to generate copper oxide and cuprous oxide, the integrating agent converts copper ions or cuprous ions into stable soluble integration substances which enter the solution, and under the action of a millstone, a polishing pad and an abrasive, the products of the chemical reaction are ground and carried away from the polishing surface by the polishing solution, so that the unreacted surface is exposed again.
And S405, connecting the metal above the second through hole with the substrate through the second through hole to form a drain electrode.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity. In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (digital versatile disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned storage medium includes: a read-only memory (ROM) or a random access memory (random access memory, RAM), a magnetic disk or an optical disk, or the like.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A trench MOSFET device comprising a source, a gate, a drain, a source region, and a substrate, the drain being on the same side of the source region as the source and the gate; the drain contacts the substrate through the TSV.
2. The trench MOSFET device of claim 1, further comprising an epitaxial layer and a body region, said body region being located above said epitaxial layer;
the epitaxial layer is positioned above the substrate;
the body region is located below the source region;
the source region is in contact with a source.
3. The trench MOSFET device of claim 2, further comprising a trench passing through said source region and said body region, said trench bottom being located inside said epitaxial layer, said trench inner wall having a gate oxide layer, said gate oxide layer being in contact with said gate electrode.
4. A trench MOSFET device according to claim 3, wherein said substrate is an n+ type substrate;
the epitaxial layer is an N-type epitaxial layer;
the body region is a P-type body region;
the source region is an N+ source region.
5. A trench MOSFET device according to claim 3, wherein said substrate is a p+ type substrate;
the epitaxial layer is a P-type epitaxial layer;
the body region is an N-type body region;
the source region is a P+ type source region.
6. The trench MOSFET device of claim 1, wherein said TSV has a via diameter of 2-10um.
7. The trench MOSFET device of claim 1, wherein said TSV has an aspect ratio of 3:1-15:1.
8. the trench MOSFET device of claim 1, wherein said TSV filler material is copper.
9. A method of fabricating a trench MOSFET device, comprising:
depositing an epitaxial layer over a substrate;
forming a body region and a source region over the epitaxial layer;
a first through hole is formed in the source region and the body region, a groove is formed in the upper layer of the epitaxial layer, and the first through hole is connected with the groove;
and performing TSV processing.
10. The method of fabricating a trench MOSFET device of claim 9, wherein performing TSV processing comprises:
a second through hole is formed in the source electrode region, and the bottom of the second through hole is located in the substrate;
depositing an insulating layer on the side wall of the second through hole;
depositing a barrier layer on the side wall of the second through hole;
filling the second through hole;
and the metal above the second through hole is connected with the substrate through the second through hole to form a drain electrode.
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| US20070132017A1 (en) * | 2005-12-06 | 2007-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of same |
| CN101095218A (en) * | 2004-08-03 | 2007-12-26 | 飞兆半导体公司 | Semiconductor power device having a top-side drain using a sinker trench |
| CN102610636A (en) * | 2011-02-07 | 2012-07-25 | 成都芯源***有限公司 | Vertical semiconductor device and method for manufacturing the same |
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2023
- 2023-09-25 CN CN202311235601.6A patent/CN116978954A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101095218A (en) * | 2004-08-03 | 2007-12-26 | 飞兆半导体公司 | Semiconductor power device having a top-side drain using a sinker trench |
| US20070132017A1 (en) * | 2005-12-06 | 2007-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of same |
| CN102610636A (en) * | 2011-02-07 | 2012-07-25 | 成都芯源***有限公司 | Vertical semiconductor device and method for manufacturing the same |
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