CN116959966A - Method for forming dislocation structure - Google Patents
Method for forming dislocation structure Download PDFInfo
- Publication number
- CN116959966A CN116959966A CN202310890175.3A CN202310890175A CN116959966A CN 116959966 A CN116959966 A CN 116959966A CN 202310890175 A CN202310890175 A CN 202310890175A CN 116959966 A CN116959966 A CN 116959966A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- gate
- forming
- auxiliary
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 238000002513 implantation Methods 0.000 claims abstract description 13
- 238000005280 amorphization Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000012010 growth Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009647 facial growth Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for forming a dislocation structure, which comprises the following steps: providing a semiconductor substrate; forming an auxiliary gate layer on the surface of the semiconductor substrate, and performing patterning etching on the auxiliary gate layer to form a gate pattern; performing pre-amorphization implantation on the semiconductor substrate by taking the gate pattern as a mask to form an amorphized region in the semiconductor substrate; removing the auxiliary gate layer forming the gate pattern; an annealing process is performed on the semiconductor substrate to form dislocation structures within the amorphized regions. The invention solves the problem that the existing dislocation structure is difficult to form in the technical node of 22nm and below.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a dislocation structure forming method.
Background
In the post gate process of the high-K metal gate, removing the dummy gate eliminates the high stress applied to the channel by the gate, and thus, the performance of the NMOS device needs to be improved by enhancing the stress memory effect (SMT) by enhancing the source/drain (S/D).
The currently used method is to implant high energy heavy ions in the source/drain regions to form an amorphous layer, and to cover the oxide layer (OX) and the high stress layer (SiN layer) with conventional stress memorization techniques for S/D activation. In the solid phase epitaxial growth process, the crystal face growth rate (001) > (110) > (111) finally forms crystal face defects on the (111), and the existence of the defects can enhance the tensile stress of the S/D region and the channel region, so that the carrier mobility is improved, and the performance of the NMOS device is further improved. However, the above method can have a significant effect on the 28nm process, but as the semiconductor process is extended to 22nm and below, the applicability of the above method is low, since as the process node is reduced, the distance between polysilicon gates is significantly reduced, in which case the pre-amorphization implant (PAI) region formed is reduced, thereby making dislocation structure formation more difficult.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a method for forming a dislocation structure, which is used for solving the problem that the existing dislocation structure is difficult to form in the technical node of 22nm and below.
To achieve the above and other related objects, the present invention provides a method of forming a dislocation structure, the method comprising:
providing a semiconductor substrate;
forming an auxiliary gate layer on the surface of the semiconductor substrate, and performing patterning etching on the auxiliary gate layer to form a gate pattern;
performing pre-amorphization implantation on the semiconductor substrate by taking the gate pattern as a mask to form an amorphized region in the semiconductor substrate;
removing the auxiliary gate layer forming the gate pattern;
an annealing process is performed on the semiconductor substrate to form dislocation structures within the amorphized regions.
Optionally, the material of the auxiliary gate layer includes photoresist.
Optionally, the size of the auxiliary gate included in the gate pattern is less than or equal to 20nm, and the space between adjacent auxiliary gates is 60 nm-150 nm.
Optionally, when the semiconductor substrate is pre-amorphized, the implanted ions include Ge, si or Xe.
Optionally, a package of process conditions is used when pre-amorphizing the semiconductor substrateThe method comprises the following steps: the implantation energy is 10 KeV-60 KeV, and the dosage is 1x10 13 /cm 2 ～1x10 15 /cm 2 The injection angle is 0-7 degrees, and the injection temperature is-100-25 ℃.
Optionally, the annealing process includes a rapid thermal anneal, a millisecond thermal anneal, a microsecond thermal anneal, a spike anneal, or a furnace tube anneal.
Optionally, the annealing temperature comprises 600 ℃ to 1100 ℃.
Optionally, after the annealing process is performed on the semiconductor substrate, the method further includes forming a plurality of gate structures on a surface of the semiconductor substrate, and a pitch between the gate structures is smaller than a pitch between the auxiliary gates, and a position of the dislocation structure is between the gate structures.
Optionally, the size of the gate structure is less than or equal to 22nm, and the interval between adjacent gate structures comprises 40 nm-100 nm.
Alternatively, suitable technology nodes include 22nm and below.
As described above, the dislocation structure forming method of the present invention forms the gate pattern by using the photoresist before forming the gate structure, and makes the space between the auxiliary gates in the gate pattern larger, so that the dislocation structure can be introduced in the process of 22nm and below to enhance the channel stress when the gate pattern is used as the mask for ion implantation, and the carrier mobility and the device performance can be improved.
Drawings
Fig. 1 shows a flow chart of a method of forming a dislocation structure in accordance with the present invention.
Fig. 2-6 are schematic cross-sectional views illustrating the process of forming dislocation structures in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for forming a dislocation structure, the method including:
providing a semiconductor substrate;
forming an auxiliary gate layer on the surface of the semiconductor substrate, and performing patterning etching on the auxiliary gate layer to form a gate pattern;
performing pre-amorphization implantation on the semiconductor substrate by taking the gate pattern as a mask to form an amorphized region in the semiconductor substrate;
removing the auxiliary gate layer forming the gate pattern;
an annealing process is performed on the semiconductor substrate to form dislocation structures within the amorphized regions.
In this embodiment, the semiconductor substrate includes, but is not limited to, a silicon substrate, a germanium substrate, or a silicon-on-insulator Substrate (SOI). In this embodiment, before the gate structure is formed on the surface of the semiconductor substrate, a pre-amorphization (PAI) implantation is performed using the gate pattern formed by the auxiliary gate layer as a mask layer for ion implantation, and the auxiliary gates in the gate pattern have smaller dimensions and larger spacing between the auxiliary gates, so that the region of the PAI implantation is enlarged to facilitate the growth of dislocation structures.
Specifically, the material of the auxiliary gate layer includes photoresist.
Specifically, the size of the auxiliary gate included in the gate pattern is less than or equal to 20nm, and the interval between adjacent auxiliary gates is 60 nm-150 nm.
Specifically, when the semiconductor substrate is subjected to pre-amorphization implantation, the implanted ions include Ge, si or Xe.
As an example, the process conditions for performing the pre-amorphization implantation on the semiconductor substrate include: the implantation energy is 10 KeV-60 KeV, and the dosage is 1x10 13 /cm 2 ～1x10 15 /cm 2 The injection angle is 0-7 degrees, and the injection temperature is-100-25 ℃. In this embodiment, a lower implantation temperature is used to increase the implantation amorphization efficiency.
Specifically, the annealing process includes rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, spike annealing, or furnace tube annealing.
As an example, the annealing temperature includes 600 ℃ to 1100 ℃.
In this embodiment, the semiconductor substrate is recrystallized during annealing of the semiconductor substrate using an annealing process, such that the dislocation structure is formed within the semiconductor substrate (as shown in fig. 5).
Specifically, after the annealing process is performed on the semiconductor substrate, the method further includes forming a plurality of gate structures on a surface of the semiconductor substrate, wherein a pitch between the gate structures is smaller than a pitch between the auxiliary gates, and a position of the dislocation structure is located between the gate structures.
In this embodiment, the gate structure may be a dummy gate, in preparation for the deposition of a subsequent metal gate, thereby forming a high-K metal gate.
Specifically, the size of the gate structure is less than or equal to 22nm, and the interval between the adjacent gate structures comprises 40 nm-100 nm.
Specifically, suitable technology nodes include 22nm and below.
In summary, in the method for forming a dislocation structure of the present invention, before forming a gate structure, a gate pattern is formed by using photoresist, and a larger space is provided between the auxiliary gates in the gate pattern, so that when the gate pattern is used as a mask for ion implantation, the dislocation structure can be introduced in a process of 22nm or less to enhance channel stress, and carrier mobility and device performance are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of forming a dislocation structure, the method comprising:
providing a semiconductor substrate;
forming an auxiliary gate layer on the surface of the semiconductor substrate, and performing patterning etching on the auxiliary gate layer to form a gate pattern;
performing pre-amorphization implantation on the semiconductor substrate by taking the gate pattern as a mask to form an amorphized region in the semiconductor substrate;
removing the auxiliary gate layer forming the gate pattern;
an annealing process is performed on the semiconductor substrate to form dislocation structures within the amorphized regions.
2. The method of claim 1, wherein the material of the auxiliary gate layer comprises photoresist.
3. The method of claim 2, wherein the gate pattern includes auxiliary gates having a size of 20nm or less, and a space between adjacent auxiliary gates includes 60nm to 150nm.
4. The method of claim 1, wherein the implanted ions comprise Ge, si, or Xe when the semiconductor substrate is pre-amorphized.
5. The method of claim 4, wherein the process conditions for pre-amorphizing the semiconductor substrate include: the implantation energy is 10 KeV-60 KeV, and the dosage is 1x10 13 /cm 2 ～1x10 15 /cm 2 The injection angle is 0-7 degrees, and the injection temperature is-100-25 ℃.
6. The method of claim 1, wherein the annealing process comprises rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, spike annealing, or furnace tube annealing.
7. The method of forming a dislocation structure as claimed in claim 6, wherein the annealing temperature comprises 600 ℃ to 1100 ℃.
8. The method of claim 3, further comprising forming a plurality of gate structures on a surface of the semiconductor substrate after the annealing process is performed on the semiconductor substrate, wherein a pitch between the gate structures is smaller than a pitch between the auxiliary gates, and wherein the dislocation structure is located between the gate structures.
9. The method of claim 8, wherein the gate structures have a size of 22nm or less and the spacing between adjacent gate structures comprises 40nm to 100nm.
10. The method of forming dislocation structure as claimed in any one of claims 1 to 9, wherein the applicable technology nodes include 22nm and below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310890175.3A CN116959966A (en) | 2023-07-19 | 2023-07-19 | Method for forming dislocation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310890175.3A CN116959966A (en) | 2023-07-19 | 2023-07-19 | Method for forming dislocation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116959966A true CN116959966A (en) | 2023-10-27 |
Family
ID=88452334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310890175.3A Pending CN116959966A (en) | 2023-07-19 | 2023-07-19 | Method for forming dislocation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116959966A (en) |
-
2023
- 2023-07-19 CN CN202310890175.3A patent/CN116959966A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8021949B2 (en) | Method and structure for forming finFETs with multiple doping regions on a same chip | |
| US7820518B2 (en) | Transistor fabrication methods and structures thereof | |
| US9722083B2 (en) | Source/drain junction formation | |
| KR20090046907A (en) | Method for forming a strained transistor by stress memorization based on a stressed implantation mask | |
| US9246006B2 (en) | Recrystallization of source and drain blocks from above | |
| CN107785313B (en) | Semiconductor structure and forming method thereof | |
| US20130109145A1 (en) | Method of manufacturing semiconductor device | |
| US20080057665A1 (en) | Strained semiconductor device and method of making same | |
| US10177246B2 (en) | Semiconductor structure and fabrication method thereof | |
| US9905673B2 (en) | Stress memorization and defect suppression techniques for NMOS transistor devices | |
| US9406797B2 (en) | Semiconductor integrated circuit with dislocations | |
| US9231079B1 (en) | Stress memorization techniques for transistor devices | |
| US9875939B1 (en) | Methods of forming uniform and pitch independent fin recess | |
| US7510923B2 (en) | Slim spacer implementation to improve drive current | |
| CN107039277B (en) | Stress memorization techniques for transistor devices | |
| CN116959966A (en) | Method for forming dislocation structure | |
| KR20060017525A (en) | Formation of junctions and silicides with reduced thermal budget | |
| US7060547B2 (en) | Method for forming a junction region of a semiconductor device | |
| US9224604B2 (en) | Device and method for forming sharp extension region with controllable junction depth and lateral overlap | |
| EP1697977B1 (en) | Method of manufacturing a semiconductor device | |
| CN104078427B (en) | SRAM (Static Random Access Memory) and preparation method thereof | |
| US10522549B2 (en) | Uniform gate dielectric for DRAM device | |
| CN118073204A (en) | Method for forming semiconductor NMOS device with dislocation structure | |
| KR100639023B1 (en) | Semiconductor device fabricating method | |
| KR100580049B1 (en) | Method for fabricating the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |