CN116936643A - 合并PiN肖特基(MPS)二极管与其制造方法 - Google Patents
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- 238000000034 method Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004088 simulation Methods 0.000 description 22
- 239000004065 semiconductor Substances 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
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- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 230000006399 behavior Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
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- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Abstract
本发明提供一种合并PiN肖特基(MPS)二极管,包括基板、第一导电类型的第一外延层、第二导电类型的数个掺杂区、第一导电类型的第二外延层以及肖特基金属层。第一外延层设置于基板的第一表面。掺杂区设置于第一外延层的表面,其中掺杂区由第一部分和第二部分组成,第一部分是电浮动的,且第二部分电连接至顶部金属。第二外延层设置于第一外延层的表面,其中有沟槽形成于第二外延层中,以暴露出掺杂区的第二部分。肖特基金属层共形沉积于第二外延层以及掺杂区中露出的第二部分上。
Description
技术领域
本发明涉及一种宽带隙半导体整流器件,尤其涉及一种合并PiN肖特基(mergedPiN Schottky,MPS)二极管与其制造方法。
背景技术
一种硅半导体整流器件,包括具有pn结的PiN二极管,以及在半导体层和金属之间的载流子势垒具有功函数差的肖特基势垒二极管(SBD),它可以将输入电流整流为输出整流电流。在SBD中,JBS(Junction Barrier Schottky,结势垒肖特基)二极管设置在半导体层的表面,以缓和施加到半导体层和金属之间的界面的电场。JBS包括具有与半导体层(例如n型)不同导电类型的掺杂区(例如p型)。还有一种MPS(Merged PiN Schottky,合并PiN肖特基)二极管,其中p型区域与JBS的金属之间的接触设置为或接近欧姆连接,并在掺杂区和半导体层之间施加超过内建电位(Vbi)的电压时,通过电导调制注入少数载流子,以降低电阻。
另一方面,碳化硅(SiC)等宽带隙半导体被期待作为下一代功率半导体装置。与Si相比,宽带隙半导体具有带隙宽、高击穿场强与热导率高的优点。利用此宽带隙半导体的特性,可以实现在高温下操作依然具有低损耗功率的半导体器件。
然而,JBS二极管由于所期望的大肖特基接触面积,而具有反向电流泄漏问题,且使正向电压VF特性劣化。
发明内容
本发明提供一种合并PiN肖特基(MPS)二极管,以改善肖特基接触面积和正向电压VF特性来减少漏电流。
本发明还提供一种合并PiN肖特基(MPS)二极管的制造方法,在不增加漏电流下改善肖特基接触面积。
本发明的一种合并PiN肖特基(MPS)二极管,包括基板、第一导电类型的第一外延层、第二导电类型的数个掺杂区、第一导电类型的第二外延层以及肖特基金属层。第一外延层设置于基板的第一表面。掺杂区设置于第一外延层的表面,其中掺杂区由第一部分和第二部分组成,第一部分是电浮动的,且第二部分电连接至顶部金属。第二外延层设置于第一外延层的表面,其中沟槽形成于第二外延层中,以暴露出掺杂区的第二部分。肖特基金属层共形沉积于第二外延层以及掺杂区所露出的第二部分。
在本发明的实施例中,上述第一部分和上述第二部分之间的间距为0.3μm至3μm。
在本发明的实施例中,上述掺杂区的每个上述第二部分的宽度为0.3μm至2μm。
在本发明的实施例中,上述第一导电型为n型,且上述第二导电型为p型。
在本发明的实施例中,上述第一导电型为p型,且上述第二导电型为n型。
在本发明的实施例中,上述基板为具有上述第一导电类型的SiC基板,其掺杂浓度为1E18/cm3至2E20/cm3。
在本发明的实施例中,上述第一外延层的掺杂浓度为2E15/cm3至1E17/cm3。
在本发明的实施例中,上述顶部金属形成于上述肖特基金属层上并填充上述沟槽。
在本发明的实施例中,上述合并PiN肖特基二极管还包括背面金属,设置于上述基板的上述第二表面。
本发明的一种合并PiN肖特基(MPS)二极管的制造方法,包括形成第一导电类型的第一外延层于基板的第一表面;形成第二导电类型的掺杂区于所述第一外延层的表面,其中所述掺杂区由第一部分和第二部分组成;形成所述第一导电类型的第二外延层于所述第一外延层的所述表面;形成数个沟槽于所述第二外延层中,以暴露出所述掺杂区的所述第二部分;以及共形沉积肖特基金属层于所述第二外延层以及所述掺杂区的所述第二部分。所述掺杂区的所述第一部分在所述第一与第二外延层中是电浮动的,且所述掺杂区的所述第二部分电连接至顶部金属。
在本发明的另一实施例中,在共形沉积上述肖特基金属层之后,还包括形成上述顶部金属于上述肖特基金属层上,以填充上述沟槽。
在本发明的另一实施例中,在形成上述顶部金属之后,上述方法还包括形成背面金属,设置于上述基板的上述第二表面,且上述第二表面相对于上述第一表面。
在本发明的另一实施例中,上述第一部分与上述第二部分沿垂直于上述沟槽的延伸方向交替排列。
在本发明的另一实施例中,上述所述第二外延层的掺杂浓度等于或高于上述第一外延层的掺杂浓度。
在本发明的另一实施例中,上述第二外延层的掺杂浓度为上述第一外延层的1.2~3倍。
基于上述,本发明提供环绕偏置掺杂区的浮动掺杂区,并且浮动掺杂区和偏置掺杂区的导电类型相同,因此在增加肖特基接触面积的情况下,浮动掺杂区可以减少漏电流。此外,由于浮动掺杂区的存在,耗尽区不会出现,因为在浮动掺杂区中没有电位差,正向电压VF特性也将获得改善。
为让本发明的上述特征和优点能更明显易懂,下文特举数个实施例,并配合附图作详细说明如下。
附图说明
附图以提供对本发明的进一步理解,且附图被并入并构成本说明书的一部分。附图绘示出本发明的示例性实施例,并与以下的说明一起用于解释本发明的原理。
图1A是依照本发明的一实施例的一种合并PiN肖特基(MPS)二极管的剖面示意图;
图1B是图1A的合并PiN肖特基(MPS)二极管的上视示意图;
图2A-2F是依照本发明的另一实施例的一种合并PiN肖特基二极管的制造方法的步骤所绘示的剖面示意图;
图3是依照模拟例1-2中的PN结面积比的剖面示意图;
图4是依照比较模拟例1-2中的PN结面积比的剖面示意图。
附图标记说明
10:合并PiN肖特基二极管
100:基板
100a:第一表面
100b:第二表面
102:第一外延层
102a:表面
104:掺杂区
106:第二外延层
108:肖特基金属层
1101:第一部分
1102:第二部分
112:沟槽
114:顶部金属
116:背面金属
200:注入阻挡层
202:离子注入
204:蚀刻阻挡层
S:间距
W:宽度
具体实施方式
现将详细地参考本发明的示范性实施例,示范性实施例的实例说明于附图中。只要有可能,相同附图标记在图式和描述中用来表示相同或相似部分。
本发明将通过以下实施例配合图示说明之。然而,本发明可以以许多不同的形式来体现,并不应被解释为限于本文所阐述的实施例。在附图中,为清楚和具体的目的,各层和区域的大小和相对大小可能没有按照准确的比例呈现。
图1A是依照本发明的一实施例的一种合并PiN肖特基二极管的剖面示意图。
请参照图1A,本实施例的合并PiN肖特基二极管10至少包括基板100、第一导电类型的第一外延层102、第二导电类型的数个掺杂区104、第一导电类型的第二外延层106以及肖特基金属层108。在一实施例中,第一导电型为n型,且第二导电型为p型。在另一实施例中,第一导电型为p型,且第二导电型为n型。基板100可为高掺杂宽带半导体基板,如具有第一导电类型的碳化硅(SiC)基板,其掺杂浓度为1E18/cm3至2E20/cm3。第一外延层102设置于基板100的第一表面100a,其中第一外延层102的宽度例如4μm至15μm,且第一外延层102的掺杂浓度例如2E15/cm3至1E17/cm3。
掺杂区104设置于第一外延层102的表面102a,其中掺杂区104由第一部分1101和第二部分1102组成,第一部分1101是电浮动的,且第二部分1102电连接(且偏置)至顶部金属114。所谓“浮动”是指主体的一部分不与主体的另一部分连接,且因此“电浮动”是指该部分不与其他部分、导电层、导线、互连部分等电连接。顶部金属114形成于肖特基金属层108上。浮动的第一部分1101可以防止来自基板100的电场流入第二外延层106。也就是说,第一部分1101可以夹止电场,因此,即使肖特基接触面积变大,也可以通过浮动掺杂区来减少漏电流。此外,由于第一部分1101的位置不存在耗尽区,因此第一部分1101处不存在电位差,所以提高了其电流密度,从而提高了正向电压VF特性。
第二外延层106设置于第一外延层102的表面102a,其中第二外延层106的厚度例如0.3μm至2μm,且第二外延层106的掺杂浓度等于或高于第一外延层102的掺杂浓度。在一实施例中,第二外延层106的掺杂浓度略高于第一外延层102的掺杂浓度,以使下漂移层(即第一外延层102)获得足够高的反向阻断电压,而较高的漂移层(即第二外延层106)可以降低肖特基接触的肖特基势垒高度,从而导致本发明的较低的VF。举例来说,第二外延层106的掺杂浓度为第一外延层102的1.2倍至3倍。第二外延层106的掺杂浓度例例如2.5E15/cm3至2E17/cm3。
在第二外延层106中,形成有数个沟槽112,以暴露出掺杂区104的第二部分1102,且沟槽112基本上彼此平行。视工艺而定,掺杂区104的每一个第二部分1102的宽度W例如0.3μm至2μm,第一部分1101与第二部分1102之间的间距S例如0.3μm至3μm,其为第一外延层102的掺杂浓度的函数。若第一外延层102的掺杂浓度为2E16/cm3,间距S则为0.3μm(对600V器件而言)。若第一外延层102的掺杂浓度为1E15/cm3,间距S则为3μm(对3300V器件而言),以此类推。如图1A所示,第一部分1101与第二部分1102沿垂直于沟槽112的延伸方向交替排列;然而,本发明不限于此。例如,掺杂区104的排列方式可以是两个第二部分1102与一个第一部分1101交替排列,以此类推。
图1B是图1A的合并PiN肖特基(MPS)二极管的上视示意图,其中一些元件在图1B中被省略,以使沟槽112、与掺杂区104的第一部分1101和第二部分1102、与顶部金属114的位置关系更加清楚。显然沟槽112直接位于掺杂区104的第二部分1102上方,且第一部分1101和第二部分1102沿垂直于沟槽112的延伸方向交替排列。
请再次参照图1A,肖特基金属层108共形沉积于第二外延层106以及掺杂区104所的暴露的第二部分1102。具体而言,肖特基金属层108位于第二外延层106的顶部、沟槽112的侧壁以及沟槽112的底部,且肖特基金属层108电连接至掺杂区104的第二部分1102。肖特基金属层108的材料包括耐火金属硅化物或耐火金属,其中耐火金属例如是Ti、Ni、W或Mo;耐火金属硅化物例如是硅化钛、硅化镍、硅化钨或硅化钼。沟槽112填充有顶部金属114,其中顶部金属114的材料例如是铝或金。合并PiN肖特基二极管10还包括设置在基板100的第二表面100b上的背面金属116,其中背面金属116的材料例如是金属硅化物,如硅化镍。
图2A-2F是依照本发明的另一实施例的一种合并PiN肖特基二极管的制造方法的步骤所绘示的剖面示意图,其中使用上述实施例中的附图标记来表示相同或相似的部件。相同部件的描述可以参阅上述实施例,在此不再赘述。
请参照图2A,于基板100的第一表面100a形成第一导电类型的第一外延层102。基板100可为第一导电类型的高掺杂宽带半导体基板,且第一外延层102的厚度和掺杂浓度可以参考上述实施例,在此不再赘述。在第一外延层102的表面102a上形成注入阻挡层200,再将其图案化以供后续注入步骤,其中注入阻挡层200例如是SiO2层或Si3N4层。
然后,请参照图2B,经由第二导电类型的离子注入202,于第一外延层102的表面102a形成第二导电类型的掺杂区104,其中掺杂区104由第一部分1101和第二部分1102组成。在一个实施例中,第一部分1101和第二部分1102彼此平行;然而,本发明不限于此。例如,第一部分1101的形状可以是正方形、圆形或矩形。
之后,请参照图2C,将注入阻挡层200移除,并进行退火处理,以在第一外延层102的表面102a处(在掺杂区104和第一外延层102间)形成PN结。然后在第一外延层102的表面102a上形成第一导电类型的第二外延层106,其中第二外延层106的掺杂浓度等于或高于第一外延层102的掺杂浓度。在一个实施例中,第二外延层106的掺杂浓度是第一外延层102的1.2倍至3倍。
然后,请参照图2D,在第二外延层106上形成蚀刻阻挡层204,然后对其进行图案化以用于后续蚀刻。通过使用蚀刻阻挡层204作为蚀刻掩模,在第二外延层106中形成沟槽112。沟槽112暴露出掺杂区104的第二部分1102,其中第一部分1101和第二部分1102沿垂直于沟槽112的延伸方向交替排列,且第二部分1102被第二外延层106所覆盖。
请参照图2E,肖特基金属层108共形沉积于第二外延层106以及掺杂区104的所述第二部分1102,以同时形成欧姆接触和肖特基接触。第一部分1101是电浮动的,且第二部分1102电连接至顶部金属114。顶部金属114可形成于肖特基金属层108上,以填充沟槽112。
之后,请参照图2F,可在进行背面研磨后,于基板100的第二表面100b上设置背面金属116,其中第二表面100b与第一表面100a相对。
以下为验证本发明功效的模拟实验,但本发明不限于以下描述。
<模拟例1>
模拟软件:Victory process SIMULATOR如同Silvaco软件的器件模拟器,可以对器件级行为的复杂物理现象进行基于物理的器件模拟,以预测和了解器件性能。模拟结果为基于浓度为2E16/cm3的N型磊晶的SiC合并PN结器件,其第一部分1101和第二部分1102之间的间距S假定为0.3μm,第二外延层106的N型磊晶浓度为4E16/cm3,而第二部分1102的宽度W也假设为0.2μm,此处,第二部分1102的宽度W由PN结面积比得出相应的表1。
请参照图3相比,图3中省略了一些元件,以使沟槽112、肖特基金属层108、掺杂区104的第一部分1101和第二部分1102以及顶部金属114之间的位置关系更加清楚。若间距S的总面积为X,且埋入的PN结总面积为Y,则PN结面积比等于100%×Y/(X+Y)。而IR漏电流随PN结面积比变化的模拟结果如下表1所示。
<比较模拟例1>
模拟条件与模拟例1相同,除了如图4所示,其所有掺杂区与肖特基金属层电接触。为了清楚说明掺杂区104、肖特基金属层108和顶部金属114的位置关系,在图4中省略了一些元件。如果掺杂区104之间的间距总面积为X,且掺杂区104的总面积为Y,则PN结面积比等于100%×Y/(X+Y)。
IR漏电流随PN结面积比变化的模拟结果也显示在下表1中。
表1
根据表1,比较模拟例1的IR漏电流显着大于模拟例1的IR漏电流,尤其是当PN结面积比变得更小时。
<模拟例2>
模拟软件与模拟例1相同,电流@VF=1.5V随PN结面积比变化的模拟结果如下表2所示。
<比较模拟例2>
除了第二部分经由互连部分与第一部分电连接到金属线之外,模拟条件与模拟例2相同。
电流@VF=1.5V随PN结面积比变化的模拟结果也请见下表2。
表2
根据表2,比较模拟例2的电流@VF=1.5V时小于模拟例2。
综上所述,由于本发明的合并PiN肖特基二极管在漂移层中具有浮动掺杂区,因此即使肖特基接触面积变大,也可以减少漏电流,并由于浮动掺杂区的存在,正向电压VF特性也可改善。此外,第二外延层的掺杂浓度可以低于第一外延层的掺杂浓度,以对于较高漂移层的低肖特基势垒高度的正向电压VF特性进一步降低。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (18)
1.一种合并PiN肖特基二极管,其特征在于,包括:
基板,具有第一表面与相对所述第一表面的第二表面;
第一导电类型的第一外延层,设置于所述基板的所述第一表面;
第二导电类型的数个掺杂区,设置于所述第一外延层的表面,其中所述掺杂区由数个第一部分和数个第二部分组成,所述数个第一部分是电浮动的,且所述数个第二部分电连接至顶部金属;
所述第一导电类型的第二外延层,设置于所述第一外延层的所述表面,其中所述第二外延层中形成有数个沟槽,以暴露出所述掺杂区的所述数个第二部分;以及
肖特基金属层,共形沉积于所述第二外延层以及所述掺杂区中的暴露的所述数个第二部分。
2.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述数个第一部分与所述数个第二部分沿垂直于所述沟槽的延伸方向交替排列。
3.根据权利要求2所述的合并PiN肖特基二极管,其特征在于,所述第一部分和所述第二部分之间的间距为0.3μm至3μm。
4.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述掺杂区的每个所述第二部分的宽度为0.3μm至2μm。
5.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述第一导电型为n型,且所述第二导电型为p型。
6.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述第一导电型为p型,且所述第二导电型为n型。
7.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述基板为具有所述第一导电类型的SiC基板,其掺杂浓度为1E18/cm3至2E20/cm3。
8.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述第一外延层的掺杂浓度为2E15/cm3至1E17/cm3。
9.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述第二外延层的掺杂浓度等于或高于所述第一外延层的掺杂浓度。
10.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述第二外延层的掺杂浓度为所述第一外延层的1.2~3倍。
11.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,所述顶部金属形成于所述肖特基金属层上并填充所述数个沟槽。
12.根据权利要求1所述的合并PiN肖特基二极管,其特征在于,还包括背面金属,设置于所述基板的所述第二表面。
13.一种合并PiN肖特基二极管的制造方法,其特征在于,包括:
形成第一导电类型的第一外延层于基板的第一表面;
形成第二导电类型的数个掺杂区于所述第一外延层的表面,其中所述掺杂区由数个第一部分和数个第二部分组成;
形成所述第一导电类型的第二外延层于所述第一外延层的所述表面;
形成数个沟槽于所述第二外延层中,以暴露出所述掺杂区的所述数个第二部分;以及
共形沉积肖特基金属层于所述第二外延层以及所述掺杂区的所述数个第二部分,其中所述数个第一部分是电浮动的,且所述数个第二部分电连接至顶部金属。
14.根据权利要求13所述的合并PiN肖特基二极管的制造方法,其特征在于,其中所述数个第一部分与所述数个第二部分沿垂直于所述沟槽的延伸方向交替排列。
15.根据权利要求13所述的合并PiN肖特基二极管的制造方法,其特征在于,其中所述第二外延层的掺杂浓度等于或高于所述第一外延层的掺杂浓度。
16.根据权利要求13所述的合并PiN肖特基二极管的制造方法,其特征在于,其中所述第二外延层的掺杂浓度为所述第一外延层的1.2~3倍。
17.根据权利要求13所述的合并PiN肖特基二极管的制造方法,其特征在于,其中在共形沉积所述肖特基金属层之后,还包括形成所述顶部金属于所述肖特基金属层上,以填充所述数个沟槽。
18.根据权利要求17所述的合并PiN肖特基二极管的制造方法,其特征在于,其中在形成所述顶部金属之后,还包括形成背面金属,设置于所述基板的所述第二表面,且所述第二表面相对于所述第一表面。
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