CN116936620A - 一种碳化硅沟槽栅mosfet的制备方法 - Google Patents
一种碳化硅沟槽栅mosfet的制备方法 Download PDFInfo
- Publication number
- CN116936620A CN116936620A CN202311182072.8A CN202311182072A CN116936620A CN 116936620 A CN116936620 A CN 116936620A CN 202311182072 A CN202311182072 A CN 202311182072A CN 116936620 A CN116936620 A CN 116936620A
- Authority
- CN
- China
- Prior art keywords
- silicon carbide
- mosfet
- well
- gate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000000407 epitaxy Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 21
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 15
- -1 aluminum ions Chemical class 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 16
- 239000007924 injection Substances 0.000 abstract description 16
- 230000005684 electric field Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 206010035148 Plague Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000607479 Yersinia pestis Species 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明属于半导体技术领域,公开了一种碳化硅沟槽栅MOSFET的制备方法。本发明将P型外延作为MOSFET的P阱,省去了传统方法的P阱的高温铝注入,节约高温离子注入产能。P型外延同时作为保护沟槽底部栅氧的深P阱,深P阱的深度由P型外延的厚度决定,突破传统高温高能注入设备的能力的限制。外延的厚度增加使得深P阱的深度增加,有效降低了沟槽底部的电场强度,保护沟槽底部栅氧,提高栅氧可靠性。
Description
技术领域
本发明属于半导体技术领域,更具体的说是涉及一种碳化硅沟槽栅MOSFET的制备方法。
背景技术
基于碳化硅(SiC)的宽带隙半导体因其低导通损耗,优异的耐高温性和高导热特性,越来越受市场的欢迎。另外,碳化硅还拥有高临界场,高体迁移率,高饱和速度等独特的电学性能,特别是高临界场特性,使碳化硅功率器件与相同电压下的常规硅器件相比,能有更高的掺杂浓度和更薄的漂移层厚度,从而实现更低的导通电阻。金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field Effect Transistor,MOSFET)有较低的开关损耗和较高的工作频率,非常贴合电力电子应用需求。
然而,传统的碳化硅沟槽栅MOSFE的制备工艺中,MOSFET的P阱的形成需要进行高温注入P型(铝离子)。同时,为了减小沟槽栅底部的栅级氧化层的电场,在沟槽栅底部以下0.4~1μm形成深P阱,需要进行高能(兆电子伏特)和高温注入P型(铝离子)。这两步工艺步骤对注入设备要求把碳化硅晶圆加热到500℃左右的高温,不仅高温高能注入设备目前只能依赖进口,同时设备产能降低,耗能较高,生产成本较高,阻止了碳化硅器件在电力电子中的进一步推广。同时,在形成深P阱的过程中,由于高能离子注入目前只能达到2-3MeV,深P阱的深度受到离子注入机设备的能量限制。
传统的高温注入P型铝离子的过程中,会在碳化硅晶圆衬底产生各种缺陷,导致碳化硅高压漏电增加,缺陷还会降低MOSFET的沟道电子迁移率。传统的碳化硅MOSFET高温离子注入形成的P阱中,沟道电子迁移率在20cm2/v·s,为体迁移率的2.5%。
因此,如何提供一种碳化硅沟槽栅MOSFET的制备方法,是本领域技术人员亟需解决的问题。
发明内容
为了克服现有技术中的缺点和不足,本发明提供了一种碳化硅沟槽栅MOSFET的制备方法,将P型外延作为MOSFET的P阱,省去了传统方法的P阱的高温铝注入,节约高温离子注入产能;P型外延层没有高温高能注入产生的缺陷,MOSFET漏电小,电子的沟道迁移率大,质量可靠性增加;简化了工艺步骤,节约工艺成本。
为了实现上述目的,本发明采用如下技术方案:
一种碳化硅沟槽栅MOSFET的制备方法,包括如下步骤:
(1)在N型衬底上生长一层N型外延,作为耐压漂移区;在N型外延上生长一层P型外延,作为MOSFET的P阱和深P阱;
(2)光刻,形成有源区;在有源区离子注入N+型,作为N+源极掺杂;
(3)淀积电介质作为掩膜,光刻并刻蚀掩膜;注入铝离子,形成P+,作为P阱的接触掺杂,并且形成体二极管;
(4)薄膜沉积一层介质层,作为沟槽刻蚀掩膜层;光刻介质层,刻蚀碳化硅,形成沟槽;
(5)在沟槽底部多次常温注入氮离子,在沟槽底部形成N型掺杂区域,构成MOSFET的电子通路;
(6)高温退火,激活掺杂离子;
(7)高温生长栅极氧化层,作为MOSFET的栅极介质;
(8)淀积多晶硅栅极,光刻以及刻蚀多晶硅,作为MOSFET的栅极电极;
(9)淀积介质层,作为栅极和源极之间的介质层;
(10)光刻并且刻蚀步骤(9)所述的介质层,作为碳化硅沟槽栅MOSFET的源极金属接触孔;
(11)淀积金属,作为碳化硅沟槽栅MOSFET的源极金属,得到碳化硅沟槽栅MOSFET。
优选的,步骤(1)中所述P型外延的厚度为0.5~2μm,浓度为2×1016 ~ 1×1018 cm-3。
上述技术方案的有益效果是:P型外延作为MOSFET的P阱和保护沟槽底部栅氧的深P阱,形成的P/N 结需要在沟槽底部有一定的距离,使得碳化硅中的强电场在到达沟槽底部之前降为安全值。P型外延厚度过小的话,碳化硅中的电场在沟槽底部过大,降低栅氧的可靠性。通过P型外延的生长,一次性完成MOSFET的P阱和沟槽底部的深P阱,节约工序,尤其是省去对注入设备要求严格的高温高能注入工序。
优选的,步骤(2)中所述N+型的深度为0.2~0.8μm。
上述技术方案的有益效果是:该步骤在有源区内地毯式注入,和有源区AA光刻合并成一步,省去传统工艺中N+型注入的光刻,掩膜淀积,掩膜刻蚀等步骤。
优选的,步骤(5)中所述注入氮离子的次数为3~6次,每次注入的剂量为1×1013~3×1013 cm-3。
上述技术方案的有益效果是:注入氮离子,使P型外延反型为N型,形成和传统的平面MOSFET的JFET区域,形成电子通道。
优选的,步骤(6)中所述高温退火的温度为1600~1850℃。
经由上述的技术方案可知,与现有技术相比,本发明提供了一种碳化硅沟槽栅MOSFET的制备方法,具有以下有益效果:
(1)本发明将P型外延作为MOSFET的P阱,省去了传统方法的P阱的高温铝注入,节约高温离子注入产能。
(2)P型外延同时作为保护沟槽底部栅氧的深P阱,深P阱的深度由P型外延的厚度决定,突破传统高温高能注入设备的能力的限制。外延的厚度增加使得深P阱的深度增加,有效降低了沟槽底部的电场强度,保护沟槽底部栅氧,提高栅氧可靠性。
(3)强电场处于P型外延底部,使得沟槽栅底部屏蔽了强电场,有效解决了困扰MOSFET的栅氧可靠性问题。
(4)P型外延层没有高温高能注入产生的缺陷,金属氧化物半导体场效应晶体管漏电小,质量可靠性增加,沟道电子迁移率增加,导通损耗减小。
(5)简化了MOSFET的生产工艺,省去高温注入形成P阱和高温高能粒子注入形成深P阱两步工艺,以及对应的光刻、抗阻挡掩膜等多部工艺步骤,简化步骤,提高产能,节约成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为本发明经过步骤(1),形成N型漂移区外延和P型外延的示意图。
图2为本发明经过步骤(2),有源区离子注入N+型,形成N+源极掺杂的示意图。
图3为本发明经过步骤(3),光刻后注入P+,作为P阱的接触掺杂,并且形成体二极管的示意图。
图4为本发明经过步骤(4),形成沟槽的示意图。
图5为本发明经过步骤(5),构成MOSFET的电子通路的示意图。
图6为本发明经过步骤(7),在沟槽内生长栅极氧化层的示意图。
图7为本发明经过步骤(8),淀积多晶硅栅极,光刻以及刻蚀多晶硅,作为MOSFET的栅极电极的示意图。
图8为本发明经过步骤(10),光刻并且刻蚀介质层,作为碳化硅沟槽栅MOSFET的源极金属接触孔后的示意图。
图9为本发明经过步骤(11),最终形成碳化硅沟槽栅MOSFET的结构示意图。
图10为实施例1的碳化硅沟槽栅MOSFET的反向耐压曲线。
图11为实施例1的碳化硅沟槽栅MOSFET的正向输出特性曲线。
具体实施方式
下面将对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
实施例1
一种碳化硅沟槽栅MOSFET的制备方法,包括如下步骤:
(1)在N型衬底上生长一层N型外延,作为耐压漂移区;在N型外延上生长一层P型外延,作为MOSFET的P阱和深P阱;
(2)光刻,形成有源区;在有源区离子注入N+型,作为N+源极掺杂;
(3)淀积电介质作为掩膜,光刻并刻蚀掩膜;注入铝离子,形成P+,作为P阱的接触掺杂,并且形成体二极管;
(4)薄膜沉积一层介质层,作为沟槽刻蚀掩膜层;光刻介质层,刻蚀碳化硅,形成沟槽;
(5)在沟槽底部多次常温注入氮离子,在沟槽底部形成N型掺杂区域,构成MOSFET的电子通路;
(6)高温退火,激活掺杂离子;
(7)高温生长栅极氧化层,作为MOSFET的栅极介质;
(8)淀积多晶硅栅极,光刻以及刻蚀多晶硅,作为MOSFET的栅极电极;
(9)淀积介质层,作为栅极和源极之间的介质层;
(10)光刻并且刻蚀步骤(9)所述的介质层,作为碳化硅沟槽栅MOSFET的源极金属接触孔;
(11)淀积金属,作为碳化硅沟槽栅MOSFET的源极金属,得到碳化硅沟槽栅MOSFET。
优选的,步骤(1)中所述P型外延的厚度为1.4μm,浓度为2×1017 cm-3。
优选的,步骤(2)中所述N+型的深度为0.3 μm。
优选的,步骤(5)中所述注入氮离子的次数为6次,每次注入的剂量为1×1013~3×1013 cm-3。
优选的,步骤(6)中所述高温退火的温度为1800℃。
图10为实施例1的碳化硅沟槽栅MOSFET的反向耐压曲线。相对于传统的平面型碳化硅MOSFET,本发明的耐压能到1900V,提高了100V~150V。
图11为实施例1的碳化硅沟槽栅MOSFET的正向输出特性曲线。10平方毫米的器件,正向导通电阻降至16毫欧,相对于传统的平面型碳化硅MOSFET损耗降低了40%。
对于传统工艺的碳化硅沟槽栅MOSFET,一台高温离子注入机产能约为400片/月,是碳化硅平面MOSFET的二分之一。本发明省去了传统的高温铝离子注入形成P阱和深P阱的过程,节约了30%的晶圆加工成本,并且增加了最高达40%的产能。
同时,由于本发明用P型外延取代了高温铝离子的注入形成的P阱,碳化硅沟槽栅MOSFET的沟道电子迁移率理论上能提高30%~200%。
本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。对于实施例公开的方案而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (5)
1.一种碳化硅沟槽栅MOSFET的制备方法,其特征在于,包括如下步骤:
(1)在N型衬底上生长一层N型外延,作为耐压漂移区;在N型外延上生长一层P型外延,作为MOSFET的P阱和深P阱;
(2)光刻,形成有源区;在有源区离子注入N+型,作为N+源极掺杂;
(3)淀积电介质作为掩膜,光刻并刻蚀掩膜;注入铝离子,形成P+,作为P阱的接触掺杂,并且形成体二极管;
(4)薄膜沉积一层介质层,作为沟槽刻蚀掩膜层;光刻介质层,刻蚀碳化硅,形成沟槽;
(5)在沟槽底部多次常温注入氮离子,在沟槽底部形成N型掺杂区域,构成MOSFET的电子通路;
(6)高温退火,激活掺杂离子;
(7)高温生长栅极氧化层,作为MOSFET的栅极介质;
(8)淀积多晶硅栅极,光刻以及刻蚀多晶硅,作为MOSFET的栅极电极;
(9)淀积介质层,作为栅极和源极之间的介质层;
(10)光刻并且刻蚀步骤(9)所述的介质层,作为碳化硅沟槽栅MOSFET的源极金属接触孔;
(11)淀积金属,作为碳化硅沟槽栅MOSFET的源极金属,得到碳化硅沟槽栅MOSFET。
2.根据权利要求1所述的一种碳化硅沟槽栅MOSFET的制备方法,其特征在于,步骤(1)中所述P型外延的厚度为0.5~2μm,浓度为1×1015~1×1018 cm-3。
3.根据权利要求1所述的一种碳化硅沟槽栅MOSFET的制备方法,其特征在于,步骤(2)中所述N+型的深度为0.2~0.8μm。
4.根据权利要求1所述的一种碳化硅沟槽栅MOSFET的制备方法,其特征在于,步骤(5)中所述注入氮离子的次数为3~6次,每次注入的剂量为1×1013~3×1013 cm-3。
5.根据权利要求1所述的一种碳化硅沟槽栅MOSFET的制备方法,其特征在于,步骤(6)中所述高温退火的温度为1600~1850℃。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202311182072.8A CN116936620A (zh) | 2023-09-14 | 2023-09-14 | 一种碳化硅沟槽栅mosfet的制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202311182072.8A CN116936620A (zh) | 2023-09-14 | 2023-09-14 | 一种碳化硅沟槽栅mosfet的制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN116936620A true CN116936620A (zh) | 2023-10-24 |
Family
ID=88388123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202311182072.8A Pending CN116936620A (zh) | 2023-09-14 | 2023-09-14 | 一种碳化硅沟槽栅mosfet的制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN116936620A (zh) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010003367A1 (en) * | 1998-06-12 | 2001-06-14 | Fwu-Iuan Hshieh | Trenched dmos device with low gate charges |
JP2004342863A (ja) * | 2003-05-16 | 2004-12-02 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
US20140217422A1 (en) * | 2012-03-30 | 2014-08-07 | Hitachi, Ltd. | Field effect silicon carbide transistor |
CN105474403A (zh) * | 2013-08-08 | 2016-04-06 | 富士电机株式会社 | 高耐压半导体装置及其制造方法 |
US20180204905A1 (en) * | 2017-01-16 | 2018-07-19 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing the semiconductor device |
US20190027598A1 (en) * | 2016-02-05 | 2019-01-24 | Denso Corporation | Semiconductor device and circuit having the same |
CN113178384A (zh) * | 2021-06-30 | 2021-07-27 | 中芯集成电路制造(绍兴)有限公司 | SiC基欧姆接触结构及其制造方法 |
US20210296447A1 (en) * | 2020-03-19 | 2021-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator |
US20230130726A1 (en) * | 2021-10-25 | 2023-04-27 | Zju-hangzhou Global Scientific And Technological Innovation Center | Silicon Carbide Trench Gate MOSFET and Method for Manufacturing Thereof |
-
2023
- 2023-09-14 CN CN202311182072.8A patent/CN116936620A/zh active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010003367A1 (en) * | 1998-06-12 | 2001-06-14 | Fwu-Iuan Hshieh | Trenched dmos device with low gate charges |
JP2004342863A (ja) * | 2003-05-16 | 2004-12-02 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
US20140217422A1 (en) * | 2012-03-30 | 2014-08-07 | Hitachi, Ltd. | Field effect silicon carbide transistor |
CN105474403A (zh) * | 2013-08-08 | 2016-04-06 | 富士电机株式会社 | 高耐压半导体装置及其制造方法 |
US20190027598A1 (en) * | 2016-02-05 | 2019-01-24 | Denso Corporation | Semiconductor device and circuit having the same |
US20180204905A1 (en) * | 2017-01-16 | 2018-07-19 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing the semiconductor device |
US20210296447A1 (en) * | 2020-03-19 | 2021-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator |
CN113178384A (zh) * | 2021-06-30 | 2021-07-27 | 中芯集成电路制造(绍兴)有限公司 | SiC基欧姆接触结构及其制造方法 |
US20230130726A1 (en) * | 2021-10-25 | 2023-04-27 | Zju-hangzhou Global Scientific And Technological Innovation Center | Silicon Carbide Trench Gate MOSFET and Method for Manufacturing Thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN114122139B (zh) | 具有集成二极管的碳化硅mosfet器件及制造方法 | |
JP6880669B2 (ja) | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 | |
CN109841616B (zh) | 碳化硅半导体装置及碳化硅半导体装置的制造方法 | |
JP2004247545A (ja) | 半導体装置及びその製造方法 | |
CN110600537B (zh) | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 | |
CN110504310B (zh) | 一种具有自偏置pmos的ret igbt及其制作方法 | |
CN106711207B (zh) | 一种纵向沟道的SiC结型栅双极型晶体管及其制备方法 | |
CN109616523B (zh) | 一种4H-SiC MOSFET功率器件及其制造方法 | |
CN114420761B (zh) | 一种耐高压碳化硅器件及其制备方法 | |
CN105140283A (zh) | 一种碳化硅MOSFETs功率器件及其制作方法 | |
WO2023045386A1 (zh) | Igbt器件及其制作方法 | |
CN111048580A (zh) | 一种碳化硅绝缘栅双极晶体管及其制作方法 | |
CN110534559B (zh) | 一种碳化硅半导体器件终端及其制造方法 | |
CN103872108B (zh) | 一种igbt结构及其制备方法 | |
CN115083895B (zh) | 一种背面变掺杂结构的场截止igbt芯片制作方法 | |
US20230047794A1 (en) | Multi-trench Super-Junction IGBT Device | |
CN115513172A (zh) | 半导体结构及其制备方法 | |
CN116936620A (zh) | 一种碳化硅沟槽栅mosfet的制备方法 | |
CN114373680A (zh) | 提高抗辐射mosfet单粒子加固结构的制备方法 | |
CN110010677B (zh) | 一种改善结终端延伸结构三极管可靠性的器件结构及其制造方法 | |
CN110880451B (zh) | 一种用于SiC功率器件芯片的栅氧化层制造方法 | |
CN107452788A (zh) | 功率器件的终端结构、功率器件及其制造方法 | |
JP7415913B2 (ja) | 半導体装置及びその製造方法 | |
CN111564486B (zh) | 具有横向电场夹断结构的功率半导体器件及其制造方法 | |
KR100299912B1 (ko) | 절연 게이트 바이폴라 트랜지스터의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |