CN116827281A - Ultrahigh input impedance neural signal acquisition circuit based on cascade instrumentation amplifier - Google Patents
Ultrahigh input impedance neural signal acquisition circuit based on cascade instrumentation amplifier Download PDFInfo
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Abstract
The invention relates to an ultra-high input impedance neural signal acquisition circuit based on a cascade instrumentation amplifier, which comprises an acquisition electrode, a cascade instrumentation amplifier, a programmable gain amplifier and an analog-to-digital converter which are connected in sequence; the cascade instrumentation amplifier is a two-stage low-noise amplifier and comprises a first-stage low-noise amplifier and a second low-noise amplifier; the acquisition electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier for N times of amplification; and then the data is amplified to the required amplitude by a programmable gain amplifier and then transmitted to an analog-to-digital converter for data conversion. The present invention improves input impedance and saves active area of an intrinsic feedback amplifier integrated circuit by reducing input and feedback capacitance.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an ultrahigh input impedance neural signal acquisition circuit based on a cascade instrumentation amplifier.
Background
The signal quality of the wearable nerve acquisition device directly determines the quality of the acquired data. The original nerve signal has low frequency and small voltage amplitude, and can be subjected to digital signal processing after amplification, filtering and digital processing. Neural signals are an effective method of acquiring brain activity, are widely used in monitoring and diagnosing brain diseases, and have been extended to the field of non-invasive man-machine. The miniaturized portable nerve signal collection system enables out-of-clinic continuous wearable nerve signal collection. Dry electrodes are the first choice for wearable neural signal acquisition, but are limited by the high electrode-tissue contact impedance. In order to increase the Analog Front End (AFE) input impedance of the dry electrode nerve signal acquisition system, the electrode-tissue contact impedance of the dry electrode nerve signal acquisition system must be further reduced. The input signal has weak amplitude and is easy to be interfered by strong common mode, and the input signal comprises external interference sources such as coupling of alternating current power lines and the like and internal interference sources such as myoelectric artifacts induced by muscle movement and electrocardiogram signals and the like. These interfering signals are 80dB higher in amplitude than the target nerve signal and cannot be effectively attenuated by filtering. Common Mode Rejection Ratio (CMRR) is a key indicator of neural AFE design. In a multichannel neural signal system, the overall system level common mode rejection ratio may be affected by other factors, such as input impedance mismatch.
Disclosure of Invention
Accordingly, the present invention is directed to a cascade instrumentation amplifier-based ultra-high input impedance neural signal acquisition circuit, which aims to solve the above-mentioned problems.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the ultra-high input impedance neural signal acquisition circuit based on the cascade instrumentation amplifier comprises an acquisition electrode, a cascade instrumentation amplifier, a programmable gain amplifier and an analog-to-digital converter which are connected in sequence; the cascade instrumentation amplifier is a two-stage low-noise amplifier and comprises a first-stage low-noise amplifier and a second low-noise amplifier; the acquisition electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier for N times of amplification; and then the data is amplified to the required amplitude by a programmable gain amplifier and then transmitted to an analog-to-digital converter for data conversion.
Further, the first stage low noise amplifier and the second low noise amplifier each comprise an input capacitor, an impedance boosting loop, a low noise amplifier, an intrinsic feedback capacitor and a pseudo resistor; one end of the input capacitor is connected with one end of the impedance lifting loop, and the other end of the input capacitor is respectively connected with one end of the low noise amplifier, one end of the intrinsic feedback capacitor and one end of the pseudo resistor; the other end of the low noise amplifier, the other end of the intrinsic feedback capacitor and the other end of the pseudo resistor are respectively connected with the other end of the impedance lifting loop.
Further, the low noise amplifier of the first-stage low noise amplifier is a fully differential amplifier with 20-26.02 dB fixed gain; the low noise amplifier of the second low noise amplifier is a fully differential amplifier with 13.98-20 dB fixed gain.
Furthermore, the intrinsic feedback capacitor adopts a gate-drain parasitic capacitor.
Further, the programmable gain amplifier comprises a pseudo resistor, a fully differential amplifier and a variable feedback capacitor group; the pseudo resistor, the fully differential amplifier and the variable feedback capacitor group are connected in parallel.
Further, the programmable gain amplifier comprises three selectable gains of 0dB/15.5dB/20.8dB, and different gains are obtained by adjusting the variable feedback capacitance.
A method for acquiring ultrahigh input impedance neural signals based on cascade instrumentation amplifier comprises the following steps:
step S1, the collecting electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier;
step S2, the nerve signals are primarily processed and amplified by 10-20 times by the first-stage low-noise amplifier and then are transmitted to the second-stage low-noise amplifier;
step S3, the nerve signals are processed and amplified again by 5-10 times by the second-stage low-noise amplifier and then transmitted to the next-stage programmable gain amplifier;
and S4, amplifying the nerve signal to a required amplitude by a programmable gain amplifier, and transmitting the nerve signal to an analog-to-digital converter for data conversion.
Further, the common mode rejection ratio CMRR of the cascade instrumentation amplifier T While depending on the common mode rejection ratio CMRR of the first stage low noise amplifier 1 Common mode rejection ratio CMRR with second stage low noise amplifier 2 ，CMRR T Is defined as:
further, introducing an input impedance mismatch between the input signal path and the reference path, CMRR E From electrode impedance Z E And alpha Z E Is not identical to the mismatch of the two input nodes Z of the amplifier IN And beta Z IN Input impedance mismatch determination of/N;
where α is the impedance mismatch between the reference potential and the working electrode, β is the input impedance mismatch between the two differential inputs of the amplifier, and N represents the number of channels sharing the same reference potential;
CMRR E is defined as:
by combining the two formulas, CMRR T Is defined as:
compared with the prior art, the invention has the following beneficial effects:
1. the invention reduces the feedback capacitance value required by the closed loop network through the intrinsic feedback structure, improves the input impedance and reduces the capacitance area at the same time;
2. the cascade structure of the CaIA can save 75-80% of capacitance area by a method of distributing gains of all stages, and further improve input impedance; and further improving the input impedance; on the other hand, in order to reduce the parasitic current at the output end, an Impedance Boosting Loop (IBL) is added to the second stage, the equivalent current flowing to the second stage is approximately equal to the current of the IBL at the second stage, and the input impedance of the second stage is kept high enough, so that the first stage does not draw/send additional current from the second stage, which is beneficial to improving the input impedance; on the other hand, the core amplifier adopts a full-self-bias design, does not need external bias, and forms common mode feedback.
Drawings
FIG. 1 is a schematic diagram of an acquisition circuit of the present invention;
FIG. 2 is a circuit diagram of an acquisition circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an acquisition process according to an embodiment of the invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples.
Referring to fig. 1, the invention provides an ultra-high input impedance neural signal acquisition circuit based on a cascade instrumentation amplifier, which comprises an acquisition electrode, a cascade instrumentation amplifier, a programmable gain amplifier and an analog-to-digital converter which are sequentially connected; the cascade instrumentation amplifier is a two-stage low-noise amplifier and comprises a first-stage low-noise amplifier and a second low-noise amplifier; the acquisition electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier for N times of amplification; and then the data is amplified to the required amplitude by a programmable gain amplifier and then transmitted to an analog-to-digital converter for data conversion.
In this embodiment, referring to fig. 2, in this embodiment, the cascade instrumentation amplifier is designed specifically as follows:
current multiplexing core operational amplifier: one path of current passes through the NMOS and PMOS input tubes simultaneously, the effective transconductance (gm) is about twice, and the input tubes are all in a subthreshold region so as to obtain the highest transconductance efficiency (gm/Id); the full-self-bias design does not need external access bias, and common mode feedback is formed at the same time;
intrinsic feedback structure: the parasitic capacitance of the grid drain of the MOS tube is used as a feedback capacitance, so that the feedback capacitance value forming a closed-loop network can be reduced to several to tens of f Farad, the input capacitance value is reduced in the same ratio, and the capacitance area is saved;
low noise amplifier cascade structure: reducing the total input capacitance area by a gain distribution method;
input impedance boost loop: forming a positive feedback loop increases the input impedance.
Specifically, in this embodiment, the first stage low noise amplifier and the second low noise amplifier each include an input capacitor, an impedance boosting circuit, a low noise amplifier, an intrinsic feedback capacitor, and a pseudo resistor; one end of the input capacitor is connected with one end of the impedance lifting loop, and the other end of the input capacitor is respectively connected with one end of the low noise amplifier, one end of the intrinsic feedback capacitor and one end of the pseudo resistor; the other end of the low noise amplifier, the other end of the intrinsic feedback capacitor and the other end of the pseudo resistor are respectively connected with the other end of the impedance lifting loop.
Preferably, the low noise amplifier of the first stage low noise amplifier is a fully differential amplifier with 20-26.02 dB fixed gain; the low noise amplifier of the second low noise amplifier is a fully differential amplifier with 13.98-20 dB fixed gain. The intrinsic feedback capacitance adopts a gate drain parasitic capacitance.
In this embodiment, the programmable gain amplifier includes a pseudo resistor, a fully differential amplifier, and a variable feedback capacitor bank; the pseudo resistor, the fully differential amplifier and the variable feedback capacitor group are connected in parallel. The programmable gain amplifier includes three selectable gains of 0dB/15.5dB/20.8dB, different gains being obtained by adjusting the variable feedback capacitance.
In this embodiment, a method for collecting a neural signal with ultra-high input impedance based on a cascade instrumentation amplifier is also provided, including the following steps:
step S1, an implantable brain-computer interface device is placed in a target body through operation, and a collecting electrode captures nerve signal potential and transmits the nerve signal potential to a cascade instrument amplifier;
step S2, the nerve signal is primarily processed by a first-stage low-noise amplifier, the amplifier forms a closed loop structure through capacitive coupling, and the amplitude of the nerve signal is amplified by 10-20 times (20-26.02 dB) and then is transmitted to a second-stage low-noise amplifier;
step S3, the nerve signal is processed again by a second-stage low-noise amplifier, the amplifier also forms a closed loop structure by capacitive coupling, the nerve signal is amplified again by 5-10 times (13.98-20 dB) and then is transmitted to a next-stage Programmable Gain Amplifier (PGA), and the nerve signal is amplified by 100 times (40 dB) by CaIA;
step S4, the nerve signals are output to a programmable gain amplifier, the PGA is also of a capacitive coupling closed loop structure, and the input capacitance can be controlled by digital signals so as to process the nerve signals with different amplitudes; the PGA amplifies the neural signal to a desired amplitude and transmits it to an analog-to-digital converter (ADC) for data conversion.
In this embodiment, the common mode rejection ratio CMRR of the cascade instrumentation amplifier T While depending on the common mode rejection ratio CMRR of the first stage low noise amplifier 1 Common mode rejection ratio CMRR with second stage low noise amplifier 2 ，CMRR T Is defined as:
in this embodiment, an input impedance mismatch, CMRR, is introduced between the input signal path and the reference path E From electrode impedance Z E And alpha Z E Is not identical to the mismatch of the two input nodes Z of the amplifier IN And beta Z IN Input impedance mismatch determination of/N;
where α is the impedance mismatch between the reference potential and the working electrode, β is the input impedance mismatch between the two differential inputs of the amplifier, and N represents the number of channels sharing the same reference potential;
CMRR E is defined as:
by combining the two formulas, CMRR T Is defined as:
the foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. The ultra-high input impedance neural signal acquisition circuit based on the cascade instrumentation amplifier is characterized by comprising an acquisition electrode, the cascade instrumentation amplifier, a programmable gain amplifier and an analog-to-digital converter which are connected in sequence; the cascade instrumentation amplifier is a two-stage low-noise amplifier and comprises a first-stage low-noise amplifier and a second low-noise amplifier; the acquisition electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier for N times of amplification; and then the data is amplified to the required amplitude by a programmable gain amplifier and then transmitted to an analog-to-digital converter for data conversion.
2. The cascade instrumentation amplifier-based ultrahigh input impedance neural signal acquisition circuit according to claim 1, wherein the first stage low noise amplifier and the second low noise amplifier each comprise an input capacitance, an impedance boosting loop, a low noise amplifier, an intrinsic feedback capacitance and a pseudo resistance; one end of the input capacitor is connected with one end of the impedance lifting loop, and the other end of the input capacitor is respectively connected with one end of the low noise amplifier, one end of the intrinsic feedback capacitor and one end of the pseudo resistor; the other end of the low noise amplifier, the other end of the intrinsic feedback capacitor and the other end of the pseudo resistor are respectively connected with the other end of the impedance lifting loop.
3. The cascade instrumentation amplifier-based ultra-high input impedance neural signal acquisition circuit according to claim 2, wherein the low noise amplifier of the first stage low noise amplifier is a fully differential amplifier with a fixed gain of 20-26.02 dB; the low noise amplifier of the second low noise amplifier is a fully differential amplifier with 13.98-20 dB fixed gain.
4. The ultra-high input impedance neural signal acquisition circuit based on a cascade instrumentation amplifier according to claim 2, wherein the intrinsic feedback capacitance uses a gate-drain parasitic capacitance.
5. The cascade instrumentation amplifier based ultra-high input impedance neural signal acquisition circuit of claim 1, wherein the programmable gain amplifier comprises a pseudo-resistor, a fully differential amplifier, and a variable feedback capacitor bank; the pseudo resistor, the fully differential amplifier and the variable feedback capacitor group are connected in parallel.
6. The cascade instrumentation amplifier based ultra-high input impedance neural signal acquisition circuit of claim 5, wherein the programmable gain amplifier comprises three selectable gains of 0dB/15.5dB/20.8dB, different gains being obtained by adjusting the variable feedback capacitance.
7. A method for acquiring the ultrahigh input impedance neural signal acquisition circuit based on the cascade instrumentation amplifier according to any one of claims 1 to 6, comprising the steps of:
step S1, the collecting electrode captures the nerve signal potential and transmits the nerve signal potential to the cascade instrumentation amplifier;
step S2, the nerve signals are primarily processed and amplified by 10-20 times by the first-stage low-noise amplifier and then are transmitted to the second-stage low-noise amplifier;
step S3, the nerve signals are processed and amplified again by 5-10 times by the second-stage low-noise amplifier and then transmitted to the next-stage programmable gain amplifier;
and S4, amplifying the nerve signal to a required amplitude by a programmable gain amplifier, and transmitting the nerve signal to an analog-to-digital converter for data conversion.
8. The method of claim 7, wherein the common mode rejection ratio CMRR of the cascode instrumentation amplifier T While depending on the common mode rejection ratio CMRR of the first stage low noise amplifier 1 Common mode rejection ratio CMRR with second stage low noise amplifier 2 ，CMRR T Is defined as:
9. the method of claim 8, wherein an input impedance mismatch, CMRR, is introduced between the input signal path and the reference path E From electrode impedance Z E And alpha Z E Is not identical to the mismatch of the two input nodes Z of the amplifier IN And beta Z IN Input impedance mismatch determination of/N;
where α is the impedance mismatch between the reference potential and the working electrode, β is the input impedance mismatch between the two differential inputs of the amplifier, and N represents the number of channels sharing the same reference potential;
CMRR E is defined as:
by combining the two formulas, CMRR T Is defined as:
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| CN117017308A (en) * | 2023-10-09 | 2023-11-10 | 之江实验室 | Slow wave neural signal amplifying circuit |
| CN117017308B (en) * | 2023-10-09 | 2024-01-23 | 之江实验室 | Slow wave neural signal amplifying circuit |
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