CN116784013A

CN116784013A - Carbon Nanotube (CNT) memory cell elements and methods of construction

Info

Publication number: CN116784013A
Application number: CN202180089601.2A
Authority: CN
Inventors: 冷耀俭
Original assignee: Microchip Technology Inc
Current assignee: Microchip Technology Inc
Priority date: 2021-06-09
Filing date: 2021-12-07
Publication date: 2023-09-19

Abstract

The present disclosure provides Carbon Nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements. The CNT memory cell may include, for example, a CNT memory cell element in combination with a transistor. The CNT memory cell element (202) includes a metal/CNT layer/metal (M/CNT/M) structure (220, 222, 224) formed between adjacent metal interconnect layers (Mx, mx+i) or between a silicided active layer (e.g., including MOSFET devices) and the metal interconnect layers. The M/CNT/M structure is formed by a process comprising: a tub opening (213) is formed in the dielectric region (208), a cup-shaped bottom electrode (220) is formed in the tub opening, a cup-shaped CNT layer (222) is formed in an interior opening defined by the cup-shaped bottom electrode, and a top electrode (224) is formed in an interior opening defined by the cup-shaped CNT layer.

Description

Carbon Nanotube (CNT) memory cell elements and methods of construction

Related patent application

The present application claims priority from commonly owned U.S. provisional patent application 63/208,928 filed on 6/9 at 2021, the entire contents of which are hereby incorporated by reference for all purposes.

Technical Field

The present disclosure relates to non-volatile memory (NVM), and more particularly to Carbon Nanotube (CNT) memory cell elements and methods of construction.

Background

Nonvolatile memory (NVM) refers to memory that can hold data without external power supply. NVM is useful for many applications, for example as a microcontroller component. In contrast, a Static Random Access Memory (SRAM), which is typically composed of six transistors, requires external power to hold data. Similarly, dynamic Random Access Memory (DRAM), which typically includes one transistor and one capacitor, also requires external power to hold and refresh data.

Currently, the most common form of NVM is flash memory, which includes floating gate based memory cells. NOR-type flash memory is generally used to store codes, while NAND-type flash memory is generally used to store data. However, flash memory has various limitations and drawbacks. For example, it is difficult to continue to reduce the critical dimensions of flash memory. In addition, flash memory typically requires high voltages (typically about 20V) for programming and erasing. In addition, adding flash memory cells to a typical CMOS process flow as an embedded memory requires several additional photomask layers, e.g., 5 or more mask layers. This adds significantly to the cost of flash memory in embedded applications.

Accordingly, other types of NVM memories have been developed in recent years, including memories employing carbon nanotubes, which are known as Carbon Nanotube (CNT) memories. Carbon Nanotubes (CNTs) are tubes made of carbon atoms with a small diameter (typically 1 to 100 nanometers). For structures that include a network of disordered (e.g., intersecting) CNTs on a planar surface, the nearby CNTs may contact or slightly separate from each other in a direction perpendicular to the substrate, depending on the van der Waals interactions between the various CNTs. For example, when the CNT network is charged in such a manner that the CNTs in the vicinity are in contact with each other, the CNT network may exhibit a low resistance state, for example, about 100kΩ. In contrast, when the CNT network is charged in such a manner that the CNTs in the vicinity are separated from each other, the CNT network may exhibit a high resistance state, for example, about 1mΩ.

CNT memory cells (e.g., nano-RAM (NRAM) cells) exploit the phenomena discussed above, for example, by selectively biasing each cell to switch CNT memory cell elements in the respective CNT memory cell between a low resistance state and a high resistance state. CNT memory cells can be generally constructed with a 1T1C (one transistor, one capacitor) configuration that includes: transistors (e.g., metal-oxide-semiconductor field effect transistors or MOSFETs) and CNT memory cell elements having a capacitor structure but functioning as switching means between a high resistance state and a low resistance state. Thus, CNT memory cell elements are often alternatively referred to as capacitors or switching devices.

Fig. 1A and 1B illustrate the general principle of operation of an exemplary CNT memory cell. Fig. 1A shows a circuit diagram of an exemplary CNT memory cell including a transistor (e.g., MOSFET) and a CNT memory cell element, and fig. 1B shows a structural cross-section of the CNT memory cell element. As shown in FIG. 1B, the CNT memory cell element includes a CNT region (labeled "CNT") formed in contact with a bottom metal layer M _x Bottom electrode (e.g. tungsten) and top metal layer M _x+1 For example, tungsten). To set (program) a CNT memory cell, a voltage (e.g., 3V) is applied to the top electrode of the CNT memory cell element through the Source Line (SL), where the bottom electrode of the CNT memory cell element is held at 0V by applying 0V to the Bit Line (BL) and activating a transistor having a first terminal connected to the BL, a second terminal connected to the bottom electrode, and a gate terminal connected to the word line. This bias causes the CNTs in the CNT region to be pulledThis electrically opens at least some of the set of conductive pathways between the top electrode and the bottom electrode through the CNT region away from the bottom electrode, thereby forming a high resistance state of the CNT memory cell element. To reset (erase) the CNT memory cell, a voltage (e.g., 2.5V) is applied to the BL and the transistor is activated, coupling the BL voltage to the bottom electrode of the CNT memory cell element while maintaining the SL connected to the top electrode of the CNT memory cell element at 0V. This bias pulls the CNT in the CNT region down toward the bottom electrode, closing many groups of conductive paths between the top and bottom electrodes through the CNT region, thereby forming a low resistance state of the CNT memory cell element.

CNT memory cells can provide various advantages such as lower power consumption, greater circuit density, faster operating speed, greater reliability due to the absence of tunneling through oxide, and/or immunity to ionizing radiation as compared to flash memory cells.

However, CNT memory cells generally have various drawbacks or shortcomings. For example, some CNT memory cells require at least one additional masking layer compared to the relevant background IC fabrication process.

As another example, the construction of CNT memory cells can involve stack etching that can be difficult to ash (ash). Both photoresist and CNT are carbon-based. The post etch resist removal process (referred to as the ash process) therefore has a very small process margin. For example, too little ash may leave resist on the wafer, which may form defects and reduce device yield or reliability, while too much ash may damage or destroy CNT structures. During the semiconductor manufacturing process, critical Dimensions (CDs) or stacks may not meet specifications in the patterning step, and it may be necessary to completely remove the photoresist to deposit and pattern a new photoresist layer to bring the CDs and stacks within the manufacturing specifications. This optical rework process may damage CNT structures.

There is a need for CNT memory cells and methods of constructing CNT memory cells that reduce or eliminate any one or more of the drawbacks and challenges discussed above. For example, it is desirable to construct CNT memory cells at lower cost and with improved fabrication processes (e.g., by reducing or eliminating added masking layers).

Disclosure of Invention

The present disclosure provides Carbon Nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements. As discussed herein, a CNT memory cell may include a CNT memory cell element that may be a component thereof (e.g., in combination with a transistor). The CNT memory cell element may include a metal/CNT layer/metal (M/CNT/M) structure formed between adjacent metal interconnect layers or between an active layer (e.g., including a MOSFET device) and a metal interconnect layer (e.g., a metal-1 layer). The M/CNT/M structure of the CNT memory cell element can be formed by a process comprising: a tub opening is formed in the dielectric region, a cup-shaped bottom electrode is formed in the tub opening, a cup-shaped CNT layer is formed in an interior opening defined by the cup-shaped bottom electrode, and a top electrode is formed in an interior opening defined by the cup-shaped CNT layer. In some examples, the cup-shaped bottom electrode may be formed simultaneously with the interconnect via, for example, by depositing tungsten or other conformal metal. In some examples, CNT memory cell elements can be formed without adding any photomask processes to the background integrated circuit fabrication process (e.g., typical CMOS fabrication process).

One aspect provides a method of forming an integrated circuit structure that includes CNT memory cell elements, such as used in CNT memory cells. The method comprises the following steps: a method of forming a semiconductor device includes forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped CNT layer in an interior opening defined by the cup-shaped bottom electrode, forming a top electrode in an interior opening defined by the cup-shaped CNT layer, and forming an upper metal layer over the dielectric region, the upper metal layer including a top electrode contact in contact with the top electrode. The cup-shaped bottom electrode, the cup-shaped CNT layer, and the top electrode define a CNT memory cell element.

In some examples, CNT memory cell elements are formed by a damascene process. Additionally, in some examples, CNT memory cell elements are formed without adding any photomask processes to the background integrated circuit fabrication process.

In some examples, a cup-shaped bottom electrode, a cup-shaped carbon nanotube layer, and a top electrode are formed in a tub opening in a dielectric region.

In some examples, a top surface of the CNT memory cell element is planarized prior to forming the upper metal layer over the dielectric region, and a dielectric barrier layer is deposited to cover the planarized top surface of the CNT memory cell element. In one example, forming the upper metal layer over the dielectric region includes: the upper dielectric layer is etched to form top electrode contact openings for forming top electrode contacts, and the dielectric barrier layer acts as an etch stop during etching.

In some examples, the method includes: a tub opening and a via opening are simultaneously formed in the dielectric region, and a conformal metal is deposited to simultaneously form a cup-shaped bottom electrode in the tub opening and a via in the via opening. In some examples, forming the upper metal layer over the dielectric region includes: while forming a top electrode contact in contact with the top electrode and an upper interconnect element in contact with the via. The conformal metal may comprise tungsten, cobalt, aluminum, or other conformal metals.

In some examples, the top electrode comprises titanium, tungsten, or a combination thereof.

In some examples, the cup-shaped carbon nanotube layer is formed by a multi-pass (multi-pass) coating process.

Another aspect provides an integrated circuit structure comprising: a dielectric region including a tub opening; a CNT memory cell element formed in the tub opening and including a cup-shaped bottom electrode, a cup-shaped CNT layer, and a top electrode; and an upper metal layer over the dielectric region and including a top electrode contact in contact with the top electrode.

In some examples, the dielectric region is formed over a lower metal layer that includes lower interconnect elements, and the CNT memory cell element is conductively connected between the lower interconnect elements in the lower metal layer and the top electrode contacts in the upper metal layer.

In some examples, a dielectric region is formed over a transistor including doped source and drain regions, and a cup-shaped bottom electrode of the resistive CNT cell structure is conductively coupled to a silicide region formed on the doped source or drain regions of the transistor.

In some examples, the upper metal layer includes a metal-1 interconnect layer.

In some examples, the integrated circuit structure includes a via formed in a via opening in the dielectric region, and the upper metal layer includes an interconnect element in contact with the via.

In some examples, the dielectric region is formed over the lower metal interconnect layer, and the upper metal layer includes the upper metal interconnect layer.

In some examples, the cup-shaped carbon nanotube layer is provided inTo->Within a range of (2).

In some examples, the conformal metal comprises tungsten and the top electrode comprises titanium, tungsten, or a combination thereof.

In some examples, the lateral width of the tub opening is greater than the vertical height of the tub opening.

Another aspect provides an integrated circuit structure that includes a carbon nanotube memory cell. The carbon nanotube memory cell includes: a transistor comprising a gate, a doped source region, and a doped drain region; and a carbon nanotube memory cell element electrically coupled to the transistor. The carbon nanotube memory cell element includes: a cup-shaped bottom electrode, a cup-shaped carbon nanotube layer formed in an interior opening defined by the cup-shaped bottom electrode, and a top electrode formed in an interior opening defined by the cup-shaped carbon nanotube layer.

In some embodiments, the cup-shaped bottom electrode is electrically coupled to a silicide region formed on a source region or a drain region of the transistor.

In some embodiments, the carbon nanotube memory cell elements are formed in a common via layer with at least one interconnect via or contact via.

Drawings

Exemplary aspects of the disclosure are described below in conjunction with the following drawings, in which:

FIG. 1A is a circuit diagram of an exemplary CNT memory cell of the prior art, and FIG. 1B shows a structural cross-section of a CNT memory cell element of the CNT memory cell of FIG. 1A;

FIG. 2A illustrates an exemplary integrated circuit structure including an exemplary CNT memory cell element formed between two metal interconnect layers and a nearby interconnect structure, wherein the CNT memory cell element is in an "on" (low resistance) state;

FIG. 2B illustrates the exemplary integrated circuit structure of FIG. 2A with the CNT memory cell element in an "off" (high resistance) state;

FIG. 2C illustrates an exemplary integrated circuit structure including an exemplary CNT memory cell element between two metal interconnect layers;

FIGS. 3A-3G illustrate an exemplary process for forming the integrated circuit structure shown in FIG. 2A, including exemplary CNT memory cell elements and interconnect structures;

FIG. 4 illustrates an exemplary integrated circuit structure including the exemplary CNT memory cells of FIGS. 2A-2B formed on MOSFET transistors, which may define a CNT memory cell or a component of a CNT memory cell; and is also provided with

Fig. 5 is a flow chart of an exemplary method for forming an exemplary CNT memory cell element.

It will be appreciated that the reference numerals of any illustrated element appearing in a plurality of different figures have the same meaning in the plurality of figures, and that any illustrated element mentioned or discussed herein in the context of any particular figure is also applicable to every other figure (if any), where the same illustrated element is shown.

Detailed Description

The present disclosure provides CNT memory cell elements and methods of forming CNT memory cell elements. As discussed herein, a CNT memory cell element can include components of a CNT memory cell (e.g., in combination with one or more transistors). The CNT memory cell element may include a lower metal layer M formed _x And upper metal layer M _x+1 M/CNT/M structure in between. In some examples, the M/CNT/M structures may be formed in a common via layer with interconnect vias or contact vias, for example, by depositing tungsten or other conformal metal into corresponding openings in a common dielectric region. In some examples, CNT memory cell elements can be formed without adding any photomask processes to the background integrated circuit fabrication process (e.g., typical CMOS fabrication process).

As used herein, for example, in the lower metal layer M _x And an upper metal layer M _x+1 In the context of (a), "metal layer" may include any metal layer or metallization layer including:

(a) Metal interconnect layers, e.g. comprising copper, aluminum or other metals formed by damascene processes or deposited by subtractive patterning processes such as deposition, patterning and etching of metal layers, or

(b) A silicided active region comprising a plurality of silicided structures (structures having a metal silicide layer formed thereon), such as a silicided source region, drain region or polysilicon gate of a MOSFET.

For example, CNT memory cell elements can be constructed at any depth in an integrated circuit structure at two adjacent metal interconnect layers M _x And M is as follows _x+1 Between them.

As another example, CNT memory cell elements can be fabricated over silicided active regions, particularly on silicon transistors having a metal silicide layer formed over selected transistor features, and under a first metal interconnect layer (commonly referred to as metal-1); in such an example, the silicided active region defines a lower metal layer M _x Where x=0 (i.e., M ₀ ) And (2) andthe first metal interconnect layer (metal-1) defines an upper metal layer M _x+1 (i.e., M ₁ ). In some examples, the CNT memory cell element and the transistor may collectively define a CNT memory cell, e.g., a 1t1c CNT memory cell, where the CNT memory cell is considered a capacitor.

In some examples, CNT memory cell elements (particularly M/CNT/M structures of CNT memory cell elements) may be formed simultaneously with certain interconnect structures (e.g., interconnect vias separate from CNT memory cell elements). For example, the cup-shaped bottom electrode of the CNT memory cell element may be formed simultaneously with the interconnect via by depositing a conformal metal layer (e.g., tungsten) into the respective openings for the cup-shaped bottom electrode and the interconnect via. For example, fig. 2A-2B, 3A-3G, and 4 illustrate exemplary CNT memory cell elements formed simultaneously with interconnect vias.

In other examples, CNT memory cell elements (particularly M/CNT/M structures of CNT memory cell elements) may be formed in a different manner (not simultaneously) than interconnect structures (e.g., interconnect vias). For example, FIG. 2C shows a CNT memory cell element having an M/CNT/M structure formed differently (not simultaneously) with interconnect vias. The exemplary CNT memory cell element shown in fig. 4 may be similarly formed in a different manner (not simultaneously) with the interconnect structure (e.g., interconnect via).

As discussed below with reference to fig. 3A-3G, in some examples, CNT memory cell elements may be constructed without adding any masking operations to the background integrated circuit fabrication process.

Fig. 2A and 2B illustrate an exemplary integrated circuit structure 200a including an exemplary CNT memory cell element 202 and an interconnect structure 204. As discussed below, fig. 2A illustrates an exemplary CNT memory cell element 202 in an "on" state that exhibits a low total resistance (e.g., 100kΩ), while fig. 2B illustrates a CNT memory cell element 202 in an "off state that exhibits a high total resistance (e.g., 1mΩ). As described above, exemplary CNT memory cell element 202 can define components of a CNT memory cell.

Referring first to fig. 2a, cnt memory cell element 202 includes a lower metal layer M formed thereon _x And upper metal layer M _x+1 Three-dimensional M/CNT/M structure in between. In the examples shown in fig. 2A, 2B and 3A to 3G, the lower metal layer M _x And upper layer M _x+1 Is two adjacent metal interconnect layers such that CNT memory cell element 202 is formed on the two adjacent metal interconnect layers M _x And M is as follows _x+1 Between via layers V _x Is a kind of medium. In other examples, as shown in fig. 4 discussed below, CNT memory cell element 202 is formed in a silicided active region (comprising one or more silicon-based transistors including a silicided structure) M ₀ Interconnect with metal layer M ₁ (commonly referred to as metal-1) via layer V _x Is a kind of medium. Through-hole layer V _x Various conductive structures formed in dielectric region 208 (e.g., oxide region) may be included. Dielectric region 208 may be an inter-metal dielectric (IMD) region and may be referred to as IMD region 208, which is for simplicity and not limitation throughout this document.

Interconnect structure 204 may include: formed on the lower metal layer M _x Lower interconnect element 210 in (e.g., where x=0 for silicided active layers as discussed above); and an upper interconnection element 260 formed on the upper metal layer M _x+1 (e.g., metal-1 layer) and connected to the lower interconnect element 210 through at least one interconnect via 214 formed in via layer V by depositing a conformal metal (e.g., tungsten, cobalt, or aluminum) into the corresponding via opening 215 _x Is a kind of medium. Each of the lower interconnect element 210 and the upper interconnect element 260 may include: wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

CNT memory cell element 202 includes a semiconductor layer formed on via layer V _x metal-CNT-metal (M/CNT/M) structures in the tub opening 213. The M/CNT/M structure of CNT memory cell element 202 includes: cup-shaped bottomA top electrode 220, a cup-shaped CNT layer 222 formed on the cup-shaped bottom electrode 220, and a top electrode 224 formed in an interior opening defined by the cup-shaped CNT layer 222. The cup-shaped bottom electrode 220 includes: (a) A laterally extending bottom electrode base 230 in contact with an underlying metal interconnect element 233, and (b) a plurality of vertically extending bottom electrode sidewalls 232 extending upwardly from the laterally extending bottom electrode base 230. The metal interconnect element 233 may include: wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

As discussed below with reference to fig. 3A and 3B, by depositing a conformal metal (e.g., tungsten, cobalt, or aluminum) to the via layer V _x The cup-shaped bottom electrode 220 may be formed simultaneously with the interconnection via 214 in the tub opening 213 and the via opening 215. In some examples, a glue layer 238 (e.g., comprising titanium nitride (TiN)) is deposited in the tub opening 213 and the via opening 215 prior to the conformal metal to improve adhesion between the conformal metal and the IMD region 208.

In one example, the laterally extending bottom electrode base 230 may have a rectangular perimeter (e.g., having a square or non-square rectangular shape) that defines four sides when viewed from above, with four vertically extending bottom electrode sidewalls 232 extending upward from the four sides of the rectangular perimeter. The cup-shaped bottom electrode 220 may include any other number of vertically extending bottom electrode sidewalls 232 extending upward from a laterally extending bottom electrode base 230.

The laterally extending bottom electrode base 230 and the vertically extending bottom electrode sidewall 232 define an interior opening 236 of the cup-shaped bottom electrode 220. As shown, cup-shaped CNT layer 222 is formed in an interior opening 236 defined by cup-shaped bottom electrode 220 and includes: a laterally extending CNT layer base 240 formed over the bottom electrode base 230, and a plurality of vertically extending CNT layer sidewalls 242 extending upwardly from the laterally extending CNT layer base 240, wherein each vertically extending CNT layer sidewall 242 is formed on a (laterally adjacent) respective vertically extending bottom electrode sidewall 232.

The laterally extending CNT layer base 240 and the vertically extending CNT layer sidewalls 242 define an interior opening 244 defined by the cup-shaped CNT layer 222. The top electrode 224 is formed inside the interior opening 244 defined by the cup-shaped CNT layer 222 and fills the interior opening 244 defined by the cup-shaped CNT layer 222. The top electrode 224 may comprise titanium nitride (TiN), tungsten (W), titanium (Ti), aluminum (Al), titanium Tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or combinations thereof, such as a combination of TiN and W, a combination of TiN and Al, or a combination of TaN, ta, cu.

A dielectric barrier 282 (which may comprise a dielectric material such as SiN or SiC, but is not limited thereto) may be formed over top electrode 224, vertically extending CNT layer sidewalls 242, and vertically extending bottom electrode sidewalls 232, sealing the top side of CNT memory cell element 202. The dielectric barrier 282 may also extend over the interconnect via 214. Can be formed on the upper metal layer M _x+1 A dielectric barrier 282 is previously formed to provide for subsequent M _x+1 An etch stop for trench metal etching (used to form the upper interconnect element 260 and the top electrode contact 258).

Formed on the via layer V _x An upper metal layer (M) over (including interconnect via 214 and CNT memory cell element 202) _x+1 ) Comprising the following steps: a top electrode contact 258 in electrical contact with the top electrode 224, and an upper interconnect element 260 in electrical contact with the interconnect via 214. In some implementations, the top electrode contacts 258 and the upper interconnect elements 260 include damascene elements formed by a damascene process (e.g., using copper, tungsten, or aluminum). For example, top electrode contact 258 and upper interconnect element 260 may comprise a copper damascene element formed over barrier layer 259 (e.g., a TaN/Ta bilayer).

The top electrode contact 258 may include: wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

Thus, according to the exemplary process described above, CNT memory cell element 202 (particularly cup-shaped bottom electrode 220) can be formed simultaneously with interconnect structure 204 (particularly via 214). As described above, in other examples, CNT memory cell element 202 can be formed differently (not simultaneously) with interconnect structure 204 (e.g., other than via 214).

As described above, FIG. 2A shows CNT memory cell element 202 in an "on" state. In this state, a sufficient amount of CNTs within cup-shaped CNT layer 222 are in contact with each other to provide a low overall resistance across cup-shaped CNT layer 222 (and as a result of from top electrode 224 to cup-shaped bottom electrode 220, or vice versa), for example 100kΩ.

In contrast, fig. 2B shows exemplary CNT memory cell element 202 in an "off" state, wherein a sufficient amount of CNTs within cup-shaped CNT layer 222 are spaced apart from one another to provide a high overall resistance across cup-shaped CNT layer 222, such as 1mΩ. However, fig. 2A shows the cup-shaped CNT layer 222 as a solid structure to indicate that CNTs are in contact with each other (providing a low resistance state), and fig. 2B shows the cup-shaped CNT layer 222 with voids to indicate that CNTs are spaced apart from each other (providing a high resistance state).

Fig. 2C illustrates an example integrated circuit structure 200b including an example CNT memory cell element 202 (in an "on" or low resistance state), where the CNT memory cell element 202 is formed differently (not simultaneously) with the interconnect via. The exemplary CNT memory cell element 202 shown in fig. 3A-3G and fig. 4 can be similarly formed differently (not simultaneously) with an interconnect structure (e.g., an interconnect via).

Fig. 3A-3G illustrate an exemplary process for forming the integrated circuit structure 200a (including the exemplary CNT memory cell element 202 and the exemplary interconnect structure 204) shown in fig. 2A and 2B. Those skilled in the art will recognize that the same process (without reference to interconnect structure 204) may be used to form integrated circuit structure 200b shown in fig. 2C by bypassing any steps associated with interconnect structure 204.

First, as shown in fig. 3A, which includes a top view (x-y plane) and a side-view cross-sectional via (x-z plane) of an integrated circuit structure 200a being formed, IMD region 208 (e.g., comprising oxide)Object) is formed on the lower metal layer M including the lower interconnection elements 210 and 233 _x Above. The lower interconnect elements 210 and 233 may include copper elements formed by a damascene process. Lower metal layer M _x The lower interconnect elements 210 and 233 of (a) may include: wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

A photoresist layer 302 may be deposited and patterned to form a photoresist opening and the underlying IMD region 208 etched through the photoresist opening to form a tub opening 213 and one or more via openings 215 in IMD region 208 for forming CNT memory cell element 202. Fig. 3A shows a via opening 215. The via opening 215 may have a square, circular or other suitable shape, as viewed from a top view (x-y plane), e.g., where the width (or diameter or Critical Dimension (CD)) W _{Through hole} In the range of 0.1 μm to 0.35 μm in both the x-direction and the y-direction.

In contrast, the tub opening 213 may have a significantly larger width W in the x-direction than the via opening 215 _{Bucket_x} And width W in y direction _{Bucket_y} . The shape and size of the tub opening 213 may be selected based on various parameters, for example, for efficient fabrication of the CNT memory cell element 202 and/or for desired performance characteristics of the resulting CNT memory cell element 202. In one example, the tub opening 213 may have a square or rectangular shape in the x-y plane. In other examples, the tub opening 213 may have a circular or oval shape in the x-y plane.

As described above, the width (W _{Bucket_x} ) Width in y direction (W _{Bucket_y} ) Or width in both x-direction and y-direction (W _{Bucket_x} And W is _{Bucket_y} ) May be substantially greater than the width W of the via opening 215 in the x-direction _{Through hole} And width W of the via opening 215 in the y direction _{Through hole} Both of which are located in the same plane. For example, in some examples, W of drum opening 213 _{Bucket_x} And W is _{Bucket_y} Is the width W of the via opening 215 _{Through hole} At least twice as many as (a). In a particular example, each width W of tub opening 213 _{Bucket_x} And W is _{Bucket_y} Width W of the via opening 215 _{Through hole} At least five times, at least 10 times, at least 20 times, or at least 50 times. Each width (W of the tub opening 213 _{Bucket_x} And W is _{Bucket_y} ) It may be sufficient to allow for the construction of CNT memory cell element 202 within tub opening 213 by a damascene process, for example, to allow for the construction of cup-shaped bottom electrode 220, cup-shaped CNT layer 222 formed in interior opening 236 of cup-shaped bottom electrode 220, and top electrode 224 formed in interior opening 244 of cup-shaped CNT layer 222. In some examples, W _{Bucket_x} And W is _{Bucket_y} Each in the range of 0.5 μm to 100 μm, for example in the range of 0.5 μm to 10 μm.

In addition, the tub opening 213 may be formed with an aspect ratio in both the x-direction and the y-direction of less than or equal to 1, for example, to allow for efficient filling of the tub opening 213 by the conformal material and CNT coating 320 (as discussed below). For example, the tub openings 213 may be formed with aspect ratios H each less than 1 (e.g., in the range of 0.1 to 1) _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} . In some examples, aspect ratio H _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} Each less than 0.5 (e.g., in the range of 0.1 to 0.5) for effectively filling the tub opening 213 through the associated conformal material (e.g., tungsten, cobalt, or aluminum) and CNT coating 320. In some examples, tub openings 213 may be formed with aspect ratios H each less than 0.2 (e.g., in the range of 0.1 to 0.2) or each less than 0.1 _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} 。

Next, as shown in fig. 3B, photoresist layer 302 is removed and a glue layer 238 (e.g., comprising TiN) is deposited over IMD region 208 and extends down into tub opening 213 and via opening 215. The glue layer 238 may be deposited using a reactive Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. In some examples, the glue layer 238 may be presentTo->Within a range of (2).

A conformal metal layer 312 is then deposited over the glue layer 238 and extends down into the tub opening 213 and into the via opening 215. As shown, the deposited conformal metal layer 312: (a) Filling the interconnect via opening 215 to form the interconnect via 214, and (b) covering the interior surface of the tub opening 213 to form a cup-shaped bottom electrode 220 defining an interior opening 236 of the cup-shaped bottom electrode 220. As discussed above, the cup-shaped bottom electrode 220 includes a plurality (in this example, four) vertically extending bottom electrode sidewalls 232 extending upwardly from a laterally extending bottom electrode cup base 230, which define an interior opening 236 of the cup-shaped bottom electrode 220. In one example, the conformal metal layer 312 comprises deposited with To->Is a tungsten of a thickness of (a). In other examples, the conformal metal layer 312 may comprise cobalt, aluminum, or other conformal metals. The conformal metal layer 312 may be deposited by a conformal Chemical Vapor Deposition (CVD) process or other suitable deposition process. Glue layer 238 may increase or enhance adhesion of conformal metal layer 312 to the interior surfaces of tub opening 213 (including the vertical sidewall surfaces of tub opening 213) to facilitate formation of cup-shaped bottom electrode 220.

Next, as shown in fig. 3C, a CNT coating 320 is deposited or formed over the conformal metal layer 312 and extends down into the interior opening 236 defined by the cup-shaped bottom electrode 220 to define a cup-shaped CNT layer 222 having an interior opening 244. In some examples, CNT coating 320 is provided with a coating onTo->Within a range of (2). In some examples, CNT coating 320 is formed by a multi-pass process, e.g., for +_ on a 200mm wafer>The thick CNT film is +.>Lane/lane 8.

Next, as shown in fig. 3D, a top electrode layer 330 may be deposited over CNT coating 320 and extend down into an interior opening 244 defined by cup-shaped CNT layer 222 to form top electrode 224. The top electrode layer 330 may include titanium nitride (TiN), tungsten (W), titanium (Ti), aluminum (Al), titanium Tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof, for example, a combination of TiN and W, a combination of TiN and Al, or a combination of TaN, ta, cu. The top electrode layer 330 may be deposited by a PVD process with sufficient thickness to fill the interior openings 244 defined by the cup-shaped CNT layer 222.

Next, as shown in fig. 3E, a Chemical Mechanical Planarization (CMP) process may be performed to remove portions of the conformal metal layer 312, CNT coating 320, and top electrode layer 330 outside of the tub opening 213 and interconnect via opening 215, leaving only portions of the cup-shaped bottom electrode 220, cup-shaped CNT layer 222, and top electrode 224 in the tub opening 213. The CMP process effectively planarizes the top surfaces of cup-shaped bottom electrode 220, cup-shaped CNT layer 222, top electrode 224, via 214, and surrounding IMD region 208.

Cup-shaped bottom electrode 220, cup-shaped CNT layer 222, and top electrode 224 collectively define CNT memory cell element 202. According to the above process, CNT memory cell element 202 is thus formed by a damascene process comprising: (a) A conformal metal layer 312, CNT coating 320, and top electrode layer 330 are deposited over IMD region 208 and extend down into tub opening 213, and (b) a CMP process to remove portions of conformal metal layer 312, CNT coating 320, and top electrode layer 330 outside (over) tub opening 213. The CMP process is applicable to CNT coating and to a variety of electrode materials including, but not limited to, W, tiN, ti, al, tiW and Cu, for example.

The formation of CNT memory cell element 202 using such a damascene process (referred to herein as "damascene integration") allows for the formation of CNT memory cell element 202 without any patterning and etching process other than the via layer etching that forms tub opening 213 and via opening 215 (see fig. 3A), which does not add the patterning and etching process to the background integrated fabrication process (which includes the via layer etching for forming the via opening). The disclosed process may be advantageous compared to other processes for forming CNT memory structures that require additional photoresist patterns and etching processes. Because damascene integration does not involve photoresist, ash is not required, which avoids damage to the CNT layer.

Next, as shown in fig. 3F, a dielectric barrier layer 282 may be deposited over the integrated circuit structure 200 a. In some examples, the dielectric barrier 282 may include a layer of silicon oxideTo->Within (e.g. in +.>To->In the range of (c), such as silicon nitride (SiN) or silicon carbide (SiC). Dielectric barrier 282 may encapsulate CNT memory cell element 202. Furthermore, in some examples, the dielectric barrier layer 282 also acts as an etch stop layer for damascene trench etching (e.g., cu trench etching) during formation of the overlying metal structure, as discussed below.

Next, as shown in fig. 3G, the upper metal layer M is formed, for example, by a damascene process _x+1 (including the top electrode contact 258 and the upper interconnect element 260) are formed including the via 214 andover the via layer Vx of CNT memory cell element 202. In one example, an upper metal layer M _x+1 Including copper interconnect layers formed by a copper damascene process.

To form the upper metal layer M _x+1 A dielectric layer 262 is first deposited over the dielectric barrier layer 282. In some examples, dielectric layer 262 may include silicon oxide, FSG (fluorosilicate glass), OSG (organosilicate glass), or porous OSG. Dielectric layer 262 may be patterned and etched to form top electrode contact openings 350 over top electrode 224 and interconnect openings 352 (e.g., trench openings) over vias 214, wherein etching proceeds through electrode contact openings 350 and interconnect openings 352 through dielectric barrier 282. A barrier layer (e.g., a TaN/Ta bilayer) and a copper seed layer indicated at 259 may be deposited over dielectric layer 262 and extend down into etched top electrode contact opening 350 and interconnect opening 352. A copper plating process may then be performed that fills the top electrode contact opening 350 and interconnect opening 352 with copper. A copper anneal may be performed followed by a copper CMP process to remove portions of copper over dielectric layer openings 350 and 352 to define top electrode contact 258 in electrical contact with top electrode 224 and upper interconnect element 260 in electrical contact with via 214.

Forming an upper metal layer M as discussed above _x+1 Thereafter, the process may be continued to build additional interconnect structures, for example, by building additional metal layers separated by respective dielectric layers.

Fig. 4 illustrates an exemplary integrated circuit structure 400 including an exemplary CNT memory cell element 202 and an interconnect structure 404. Unlike the example shown in fig. 2A and 2B (where CNT memory cell element 202 is formed in two adjacent metal interconnect layers M) _x And M is as follows _x+1 Between) in the example shown in fig. 4, CNT memory cell element 202 is formed in (a) a silicided active region M comprising a silicided structure of a metal-oxide-semiconductor field effect transistor (MOSFET) 406 ₀ (i.e., M _x Where x=0) and (b) a first metal interconnect layer M, commonly referred to as metal-1 ₁ (i.e., M _x+1 Where x=0).

In some examples, CNT memory cell element 202 and MOSFET 406 can collectively define a CNT memory cell, e.g., a 1T1C memory cell, where CNT memory cell element 202 is considered a capacitor.

As shown in fig. 4, the active region M is silicided ₀ Including MOSFET 406 formed on a silicon substrate 408. MOSFET 406 may include: a polysilicon gate 410 formed over the silicon substrate 408 and separated from the silicon substrate by a gate oxide layer 412, and doped source and drain regions 414 and 416 formed in the silicon substrate 408. In this example, the polysilicon gate 410 and the doped drain region 416 include a silicidation structure 420. Specifically, a metal silicide layer 424 is formed on the top surface of the polysilicon gate 410, and a metal silicide layer 426 is formed on the top surface of the doped drain region 416. Metal silicide layers 424 and 426 may be included To->Any suitable metal silicide layer, such as titanium silicide (TiSi 2), cobalt silicide (CoSi 2), or nickel silicide (NiSi), of a thickness within the range of (a) or other suitable thickness. For purposes of this disclosure, metal silicide layers 424 and 426 define a metal structure such that active region M is silicided ₀ May be considered a metal layer.

In the example shown in fig. 4, CNT memory cell element 202 is formed on a metal silicide layer 426 on top of doped drain region 416, which is used to provide a conductive connection between CNT memory cell element 202 and doped drain region 416. As discussed above, CNT memory cell element 202 is contacted from above by top electrode contact 258. In addition, vias 214 (also commonly referred to as contact vias) are formed on a metal silicide layer 424 on top of the polysilicon gate 410, which is used to provide a conductive connection between the polysilicon gate 410 and the upper interconnect element 260. Top electrode contact 258 and upper interconnect element 260 include, for example, by damasceneIs formed on the first metal interconnection layer M ₁ Is a metal element of the group (C). The foregoing has been described in the example in which exemplary CNT memory cell element 202 is formed on metal silicide layer 426 on top of doped drain region 416, it being understood that in other examples CNT memory cell element 202 may be formed on top of doped source region 414.

Fig. 5 is a flow chart of an exemplary method 500 for forming the exemplary CNT memory cell element 202 discussed above. At 502, at metal interconnect layer M _x Over (e.g. as shown in fig. 2A-2C) or in siliciding the active region M ₀ A dielectric region (e.g., dielectric region 208) is formed above (e.g., as shown in fig. 4). At 504, a tub opening (and optionally one or more via openings) (e.g., tub opening 213 and optional via opening 215) is formed in the dielectric region of 502.

At 506, a conformal fill metal (e.g., tungsten, cobalt, or aluminum) is deposited in the tub openings of 504, and optionally in the via openings of 504 (e.g., fill metal 312). At 508, a CNT layer is deposited (e.g., using a multi-pass coating process) to form a CNT film having a coating thereonTo->CNT layer of a thickness in the range of (a). The CNT layer may be CNT layer 320. At 510, a top electrode layer (e.g., tungsten, titanium, or a combination thereof) is deposited over the CNT layer of 508 (e.g., top electrode layer 320 is deposited over CNT layer 320).

At 512, a CMP process is performed to remove portions of the conformal metal layer, CNT coating, and top electrode layer outside of the tub opening (and optionally the via opening), wherein the remaining portions of the conformal metal layer, CNT coating, and top electrode layer in the tub opening define CNT memory cell elements. For example, the remainder of conformal metal layer 312 defines cup-shaped bottom electrode 220, the remainder of CNT coating 320 defines cup-shaped CNT layer 222, and the remainder of top electrode layer 330 defines top electrode 224. Further, after the CMP process, the remaining portion of the conformal metal layer 312 in each (optional) via opening 215 defines a respective via 214.

At 514, a dielectric barrier layer (e.g., comprising silicon oxide, FSG, OSG, or porous OSG, such as dielectric barrier layer 282) is deposited over the CNT memory cell element (and optionally over the via). At 516, an upper metal layer M is formed including _x+1 (e.g., copper or aluminum): a top electrode contact (e.g., top electrode contact 258) and optionally an upper interconnect element over each via (e.g., upper interconnect element 260 over each via 214).

Claims

1. A method of forming an integrated circuit structure comprising carbon nanotube memory cell elements, the method comprising:

forming a tub opening in the dielectric region;

forming a cup-shaped bottom electrode in the tub opening;

forming a cup-shaped carbon nanotube layer in an interior opening defined by the cup-shaped bottom electrode;

forming a top electrode in an interior volume defined by the cup-shaped carbon nanotube layer; and

forming an upper metal layer over the dielectric region, the upper metal layer including a top electrode contact in electrical contact with the top electrode;

wherein the cup-shaped bottom electrode, the cup-shaped carbon nanotube layer, and the top electrode define the carbon nanotube memory cell element.

2. The method of claim 1, wherein the carbon nanotube memory cell element is formed by a damascene process.

3. The method of any of claims 1-2, wherein the carbon nanotube memory cell element is formed without adding any photomask process to a background integrated circuit fabrication process.

4. A method according to any one of claims 1 to 3, comprising, prior to forming the upper metal layer over the dielectric region:

planarizing a top surface of the carbon nanotube memory cell element; and

a dielectric barrier layer is deposited to cover the planarized carbon nanotube memory cell element.

5. The method according to claim 4, wherein:

forming the upper metal layer over the dielectric region includes: etching the upper dielectric layer to form a top electrode contact opening for forming the top electrode contact; and is also provided with

The dielectric barrier layer acts as an etch stop during the etching.

6. A method according to any one of claims 1 to 3, the method comprising:

simultaneously forming the tub opening and via opening in the dielectric region; and

A conformal metal is deposited to simultaneously form the cup-shaped bottom electrode in the tub opening and a via in the via opening.

7. The method of claim 6, wherein forming the upper metal layer over the dielectric region comprises: the top electrode contact in electrical contact with the top electrode and the upper interconnect element in contact with the via are formed simultaneously.

8. The method of any of claims 6-7, wherein the conformal metal comprises tungsten.

9. The method of any one of claims 1 to 8, wherein the top electrode comprises titanium, tungsten, or a combination thereof.

10. The method of any one of claims 1 to 9, wherein forming the cup-shaped carbon nanotube layer comprises a plurality of coating processes.

11. An integrated circuit structure, the integrated circuit structure comprising:

a dielectric region comprising a tub opening;

a carbon nanotube memory cell element formed in the tub opening and comprising:

a cup-shaped bottom electrode;

a cup-shaped carbon nanotube layer; and

a top electrode; and

an upper metal layer over the dielectric region and including a top electrode contact in electrical contact with the top electrode.

12. The integrated circuit structure of claim 11, wherein:

the dielectric region includes a tub opening;

the carbon nanotube memory cell element is formed in the tub opening; and is also provided with

The integrated circuit structure also includes an upper metal layer over the dielectric region and includes a top electrode contact in electrical contact with the top electrode.

13. The integrated circuit structure of claim 12, wherein:

the dielectric region is formed over a lower metal layer including a lower interconnect element; and is also provided with

The carbon nanotube memory cell element is conductively connected between the lower interconnect element in the lower metal layer and the top electrode contact in the upper metal layer.

14. The integrated circuit structure of claim 13, wherein the upper metal layer comprises a metal-1 interconnect layer.

15. The integrated circuit structure of any of claims 12-14, comprising a via formed in a via opening in the dielectric region; and is also provided with

Wherein the upper metal layer includes an interconnect element in contact with the via.

16. The integrated circuit structure of any of claims 11-15, wherein:

The dielectric region is formed over the lower metal interconnect layer; and is also provided with

The upper metal layer includes an upper metal interconnect layer.

17. The integrated circuit structure of claim 11, wherein:

the cup-shaped carbon nanotube layer is formed in an interior opening defined by the cup-shaped bottom electrode; and is also provided with

The top electrode is formed in an interior opening defined by the cup-shaped carbon nanotube layer.

18. The integrated circuit structure of any of claims 11-17, wherein the cup-shaped carbon nanotube layer has a surface area betweenTo->Within a range of (2).

19. The integrated circuit structure of any of claims 11-18, wherein:

the cup-shaped bottom electrode comprises tungsten; and is also provided with

The top electrode comprises titanium, tungsten, or a combination of titanium and tungsten.

20. The integrated circuit structure of any of claims 11-19, wherein a lateral width of the tub opening is greater than a vertical height of the tub opening.

21. The integrated circuit structure of claim 20, wherein the carbon nanotube memory cell elements are formed in a common via layer with at least one interconnect via or contact via.

22. The integrated circuit structure of any of claims 11-21, wherein:

The dielectric region is formed over a transistor including a doped source region and a doped drain region;

the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to a silicide region formed on the source region or the drain region of the transistor.

23. An integrated circuit structure formed by any of the methods of claims 1 to 10.