CN116780930B - Switch time sequence optimization design of two parallel converters and carrier modulation method thereof - Google Patents
Switch time sequence optimization design of two parallel converters and carrier modulation method thereof Download PDFInfo
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Abstract
The invention discloses a switch time sequence optimization design for zero sequence circulation suppression and common mode voltage elimination of two parallel converters and a carrier modulation implementation method thereof, which comprises the following steps: 18 optimal switch combinations which simultaneously meet the condition that the circulation change rate is +/-1 and the common mode voltage is 0 are selected, and 72 optimal switch time sequences and carrier modulation implementation schemes thereof, wherein the modulation area covers the whole vector plane, are designed based on the 18 optimal switch combinations; the 72 optimal switch time sequences and carrier modulation schemes thereof can solve the problem of overlarge zero sequence circulation of the existing zero common mode voltage modulation algorithm, and can further optimize single index or comprehensively optimize multiple key indexes on the basis of eliminating common mode voltage and optimizing zero sequence circulation by utilizing redundant time sequences; finally, as an example of a derivative algorithm, two novel pulse width modulation algorithms are derived by utilizing the proposed optimal switching time sequence, and the effectiveness of the two derivative algorithms is verified through experiments.
Description
Technical Field
The invention relates to a switch time sequence optimization design and a carrier modulation implementation method thereof, in particular to a switch time sequence optimization design and a carrier modulation implementation method thereof aiming at zero sequence circulation suppression and common mode voltage elimination of two parallel converters.
Background
With the increasing high-power demands of industrial occasions, the parallel converter is widely applied to various high-power application occasions, such as high-power motor driving, grid-connected wind power generation and uninterruptible power supply. The two parallel power converters are directly connected in parallel, so that the volume and the cost are reduced, the system capacity is doubled, and the two parallel power converters become an excellent current capacity expansion topology. However, a circulation exists between the two converters which are not effectively electrically isolated, so that the safe and efficient operation of the system is affected; meanwhile, an excessive common-mode voltage may cause problems such as electromagnetic interference, equipment insulation damage and potential safety hazards. However, due to the lack of a switch timing design method for simultaneously optimizing zero sequence circulation and eliminating common-mode voltage, 6 switch timings used by the existing zero common-mode voltage modulation algorithm all introduce larger zero sequence circulation, and the existing algorithm cannot simultaneously eliminate common-mode voltage and inhibit zero sequence circulation: when a modulation method for eliminating common-mode voltage is adopted, zero-sequence circulation between two parallel converters is larger. Therefore, in order to improve the operation performance and reliability of the two parallel converters, a switching time sequence optimization design method for simultaneously eliminating the common-mode voltage and optimizing the zero sequence circulation needs to be provided, so as to further inhibit the excessive zero sequence circulation while eliminating the common-mode voltage.
The zero sequence circulation and the common-mode voltage are related to the instant state of each switching tube of the two converters, and in order to optimize the zero sequence circulation and eliminate the common-mode voltage simultaneously, the coupling relation between the two switching states needs to be analyzed to obtain a switching state combination which is favorable for the simultaneous optimization of the two switching states, and further, the switching state combination which is favorable for the optimization of the two switching states is accurately output in each carrier period. Meanwhile, a modulation wave expression corresponding to the optimal switching time sequence and a switching action mode thereof are constructed in a reverse mode, so that the simple on-line generation of the optimal switching time sequence is realized. Therefore, the patent starts from the switch time sequence optimization design, and provides a switch time sequence optimization design method for simultaneously optimizing zero sequence circulation and eliminating common-mode voltage.
Disclosure of Invention
The invention aims to provide a switch time sequence optimization design aiming at zero sequence circulation suppression and common-mode voltage elimination of two parallel converters and a carrier modulation implementation method thereof, which solve the problem that the switch time sequence used by the existing algorithm introduces excessive zero sequence circulation.
The technical solution for realizing the purpose of the invention is as follows:
a switch time sequence optimization design and a carrier modulation implementation method thereof aiming at zero sequence circulation suppression and common mode voltage elimination of two parallel converters comprise the following steps:
step 1, obtaining all possible switch state combinations according to a mathematical model of two parallel converters, and selecting 18 optimal switch combinations which simultaneously meet the circulation change rate of +/-1 and the common mode voltage of 0 from all the switch state combinations based on the mapping relation between the switch state combinations and the zero sequence circulation and the common mode voltage;
step 2, designing 72 optimal switching time sequences of a modulation area covering the whole vector plane based on 18 optimal switching combinations and considering constraint conditions of zero sequence loop current balance and switching times;
and step 3, designing a modulation wave expression and an action mode thereof required by generating the optimal switching time sequence based on 72 optimal switching time sequences to form a carrier modulation implementation scheme.
And 4, based on 72 optimal switch time sequences and carrier modulation implementation schemes, deriving a new pulse width modulation algorithm by using different optimal time sequences at different positions of a vector plane, and realizing further optimal single index or comprehensive optimal multiple key indexes on the basis of optimizing zero sequence circulation and eliminating common-mode voltage. Based on 72 optimal switch time sequences and carrier modulation implementation schemes thereof, a novel modulation algorithm can be designed to simultaneously optimize zero sequence circulation and eliminate common-mode voltage, the defect that the existing zero-common-mode voltage algorithm introduces excessive zero sequence circulation is overcome, meanwhile, other relevant optimal modulation algorithms can be derived by utilizing time sequence redundancy, and single index is further optimized or multiple key indexes are comprehensively optimized on the basis of eliminating common-mode voltage and optimizing zero sequence circulation.
The computer storage medium stores an executable program which is executed by a processor to realize the switch time sequence optimization design and the carrier modulation realization method aiming at zero sequence loop current inhibition and common mode voltage elimination of two parallel converters.
Compared with the prior art, the invention has the beneficial effects that: (1) The patent provides an optimal switch time sequence design method capable of simultaneously optimizing zero sequence circulation and eliminating common-mode voltage, and solves the problem of overlarge zero sequence circulation of the existing switch time sequence; (2) Based on the provided optimal switching time sequence design method, 72 optimal switching time sequences are designed, and compared with 6 switching time sequences of the existing algorithm, the provided optimal switching time sequences have rich time sequence redundancy; therefore, the abundant redundancy of the provided optimal time sequence can be utilized to derive other related optimal modulation algorithms, and on the basis of eliminating common-mode voltage and optimizing zero-sequence loop current, single index is further optimized or multiple key indexes are comprehensively optimized, for example, single optimal zero-sequence loop current, ripple wave compatible optimization, carrier modulation realization scheme simplification, and the number of switching times required by sector switching minimization are realized.
Drawings
Fig. 1 is a topology of two parallel converters.
Fig. 2 is a diagram of the equivalent output voltage vectors of two parallel converters.
Fig. 3 is a zero common mode voltage vector diagram.
FIG. 4 (a) shows the zero sequence loop pattern p corresponding to the sequences 1-4 1 -p 2 A schematic diagram; FIG. 4 (b) shows the zero sequence loop pattern p corresponding to the sequences 5-8 3 -p 4 A schematic diagram; FIG. 4 (c) shows the zero sequence loop pattern p corresponding to the sequences 9-12 5 -p 6 Schematic diagram.
Fig. 5 is a diagram of six switching operation modes.
Fig. 6 (a) is a switching timing diagram of the sequence SQ1 under the staggered carrier frame, and fig. 6 (b) is a switching timing diagram of the sequence SQ2 under the staggered carrier frame.
Fig. 7 is a zmv 2 sector division diagram proposed in this patent.
Fig. 8 is a simplified diagram of a zmv 2 sector proposed by the present patent.
Fig. 9 is a zmv 2 flow chart of the present patent.
Fig. 10 (a) is a graph of parallel current experimental results of the existing zero common mode voltage modulation algorithm, fig. 10 (b) is a graph of zero sequence loop experimental results of the existing zero common mode voltage modulation algorithm, and fig. 10 (c) is a graph of common mode voltage experimental results of the existing zero common mode voltage modulation algorithm.
Fig. 11 (a) is a zmv 1 parallel current experimental result diagram, fig. 11 (b) is a zmv 1 zero sequence loop experimental result diagram, and fig. 11 (c) is a zmv 1 common mode voltage experimental result diagram.
Fig. 12 (a) is a zmv 2 parallel current experimental result diagram, fig. 12 (b) is a zmv 2 zero sequence loop experimental result diagram, and fig. 12 (c) is a zmv 2 common mode voltage experimental result diagram.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Because of the lack of a switch time sequence optimization design method, the switch time sequence of the existing zero common-mode voltage modulation algorithm introduces excessive zero sequence circulation, and therefore, the patent provides an optimal switch time sequence design method capable of simultaneously optimizing zero sequence circulation and eliminating common-mode voltage, and the problem of excessive zero sequence circulation of the existing switch time sequence is solved. The switch time sequence optimization design emphasizes that the switch time sequence which is favorable for optimizing the key index is directionally designed based on the mapping relation between the key index and the switch combination, and the modulation wave corresponding to the optimal switch time sequence and the switch action mode thereof are constructed in a reverse mode, so that the simple on-line generation of the optimal switch time sequence is realized. The patent firstly analyzes the mapping relation between the switch state combination and the zero sequence circulation and the common-mode voltage, and selects 18 optimal switch combinations from all the switch state combinations from the angles of simultaneously eliminating the common-mode voltage and optimizing the zero sequence circulation. Secondly, the patent designs 72 optimal switching time sequences of the whole vector plane from the angles of zero sequence circulation optimization and total switching times optimization based on 18 optimal switching combinations. Meanwhile, for on-line simple output, the invention designs six different switch action modes and deduces the modulation wave expression corresponding to each optimal time sequence. It should be noted that, 72 kinds of optimal time sequences and carrier modulation implementation methods thereof provided by the patent not only can solve the problem of overlarge zero sequence circulation of the existing zero common mode voltage algorithm, but also can utilize the abundant redundancy of the optimal switching time sequences to derive other relevant novel modulation algorithms, and further optimize single index or comprehensively optimize multiple key indexes on the basis of eliminating common mode voltage and optimizing zero sequence circulation.
A switch time sequence optimization design and a carrier modulation implementation method thereof aiming at zero sequence circulation suppression and common mode voltage elimination of two parallel converters comprise the following steps:
(1) According to the mathematical model of the two parallel converters, all possible switch state combinations are obtained, the mapping relation between the switch state combinations and zero sequence circulation and common mode voltage is analyzed, 18 optimal switch combinations which simultaneously meet the circulation change rate of +/-1 and the common mode voltage of 0 are selected from all the switch state combinations, and the method specifically comprises the following steps:
the topology of the two parallel converters is shown in figure 1. Wherein i is a 、i b And i c Representing parallel three-phase current; i.e a1 、i b1 And i c1 Representing three-phase current of the first converter; i.e a2 、i b2 And i c2 Representing the three-phase current of the second converter; e, e a 、e b And e c Representing the three-phase voltage on the net side; l represents a network side filter inductance; l (L) 1 Representing a first converter filter inductance; l (L) 2 Represents the filter inductance of the second converter, meets L 2 ＝L 1 ；V DC Representing the dc bus voltage.
For two parallel converters, the output voltage satisfies on two-phase stationary coordinates:
wherein u is α And u β Indicating that the two phases are stationaryOutput voltage at the coordinates; s is S a1 ，S b1 And S is c1 Respectively representing the switching states of three-phase switching tubes of the first converter; s is S a2 ，S b2 And S is c2 The switching states of the three-phase switching tubes of the second converter are respectively indicated. When S is a1 =1, indicating the switching tube S 11 Conduction and switch tube S 14 Turning off; when S is a1 =0, representing the switching tube S 14 Conduction and switch tube S 11 And (5) switching off. As can be seen from the formula (1), the output voltages of the two parallel converters are any combination of the individual outputs, and since 8 voltage states (V 100 ～V 101 ) Two parallel converters have 8×8=64 combined outputs. All switch combinations were brought into equation (1) to give all output combinations for the two parallel converters as shown in table 1. For example, when the output vector of the first converter is V 100 The output vector of the second converter is V 011 As can be seen from Table 1, the equivalent output voltage vector is V 0 . Meanwhile, since 64 combinations output only 19 basic vectors, as in fig. 2. The 19 base vectors shown in fig. 2 have a large redundancy.
Table 1 output vector of two parallel converters
According to the two parallel converter models, the key performance index zero sequence circulation i cir And common mode voltage u CMV The following respectively satisfy:
equation (2) and equation (3) show that both zero sequence circulating current and common mode voltage are directly related to a single switch state combination. For this purpose, the switching states of all switching tubes are substituted into the formulas (2) and (3) to obtain the zero sequence circulation current under 64 state combinationsThe slope of the change and the quality of the common mode voltage are shown in table 1. Table 1 not only marks the mapping relation between the single switch state combination and the equivalent output voltage, but also clarifies the mapping relation between the single switch state combination and the zero sequence circulation and the common mode voltage: the first digit in brackets indicates the zero sequence loop current change rate of the switch combination, which is expressed in V DC Carrying out per unit processing by taking (2L) as a basic value; the second number in brackets indicates the common mode voltage magnitude of the switch combination. For example, when the output vector of the first converter is V 100 The output vector of the second converter is V 011 As can be seen from Table 1, the equivalent output voltage vector is V 0 (-1, 0); meanwhile, "-" means zero sequence circulation flows from the second station to the first station; the second number in brackets represents the common mode voltage output under the switch combination.
To optimize zero sequence loop current, a switch combination with a small zero sequence loop current change rate must be used, while to ensure common mode voltage cancellation, only a switch combination with zero common mode voltage is used. All combinations of table 1 were screened based on this principle to obtain preferred vectors and their switch state combinations that simultaneously met the above conditions, as shown in table 2.
TABLE 2 zero common mode voltage vector combinations and circulation rate of change
For ease of description, table 2 describes the output vectors and their switch state combinations in another convenient manner, for example,representing the equivalent output voltage vector as V 0 Wherein the voltage vector of the first converter is V 100 The voltage vector of the second converter is V 011 ，V i Representing the i-th equivalent output voltage vector. Notably, due to the requirement of co-optimization of zero sequence circulation and common mode voltage, the mode length of 2V is eliminated DC Vector of/3 (V 1 ,V 2 ,V 3 ,V 4 ,V 5 ,V 6 ). Thus, when the preferred vector synthesized reference voltage is used, the modulation range is as in fig. 3. Definition of modulation m= 2|U r |/V DC Wherein, |U r I represents the modulo length of the output voltage vector, where M ε [0,1 ]]。
(2) Based on 18 optimal switch combinations, considering constraint conditions of zero sequence circulation balance and switching times, designing 72 optimal switch time sequences of a modulation area covering the whole vector plane, and specifically comprising:
when the preferred switch combination is determined, the preferred switch combination needs to be further utilized for the switch timing optimization design. In order to ensure circulation balance, redundant vectors and vectors with opposite circulation change rates are needed to be used in each switching period, the acting time of the redundant vectors is equally divided, and meanwhile, the total switching times of the switching time sequence are less than or equal to 12 times in consideration of switching loss. Based on the two principles, the switch timing design is performed by using the proposed optimized switch combination. The vector plane is divided into 6 large sectors: -30 DEG is sector I, 30-90 DEG is sector II, 90-150 DEG is sector III, 150-210 DEG is sector IV, 210-270 DEG is sector V and 270-330 DEG is sector VI. Taking sector I as an example, three basic vectors V of the synthesized reference voltage are selected 0 、V 7 And V 12 Corresponds to the 10 optimal switch combinations in table 2. At the same time by V 0 For the start vector to illustrate the method of timing design, 12 alternative switch timings were designed, as shown in Table 3.
TABLE 3V 0 Alternative switch timing as a start vector
SQ 1-SQ 12 represent the switching sequence numbers, and it should be noted that since the preferred switching combinations are all zero common mode voltage combinations, table 3 no longer labels the common mode voltage output by each vector in the sequence, only labels the zero sequence loop slope of each vector. For example, V 0 (+1) represents an equivalent output voltage vector of V 0 The circulation change rate was +1.
Taking sequence SQ1 in table 3 as an example, according to the zero sequence loop expression defined by equation (2), the zero sequence loop of sequence SQ1 appears as a time domain piecewise function within a single switching cycle:
wherein d 0 Representing the start vector V 0 Duty cycle, T of s Representing the switching period. From equation (4), the peak of the loop current of the sequence SQ1 appears at t= (2-d) 0 )T s At time/4, corresponding to peak i cirpeak ＝(2－d 0 )V DC T s /(8L)。
By analyzing the zero sequence loop conditions of 12 switch timings in table 3 by the same method, it can be found that the zero sequence loop of the 12 timings can be classified into 6 patterns p 1 ～p 6 As shown in fig. 4 (a), 4 (b) and 4 (c):
wherein V is x 、V y 、V z Representing three base vectors corresponding to different sectors.
In fig. 4 (a), 4 (b) and 4 (c), d X 、d Y And d Z Respectively represent the first vector V X A second vector V Y Third vector V Z Duty cycle of (2); taking sequence SQ1 as an example, sequence SQ 1V X 、V Y And V Z Respectively corresponding to the vector V 0 、V 12 And V 7 . The correspondence of the sequences in table 3 to the loop pattern of fig. 4 is: sequence 1 and sequence 2 correspond to pattern p 1 Sequence 3 and sequence 4 correspond to pattern p 2 The method comprises the steps of carrying out a first treatment on the surface of the Sequence 5 and sequence 6 correspond to pattern p 3 Sequence 7 and sequence 8 correspond to pattern p 4 The method comprises the steps of carrying out a first treatment on the surface of the Sequence 9 and sequence 10 correspond to pattern p 5 Sequence 11 and sequence 12 correspond to pattern p 6 。
According to the magnitudes of the circulation peaks in FIGS. 4 (a) - (c), six circulation patterns (p 1 -p 6 ) Two further categories can be generalized:
i cirpeak_1 ＝d 0 +2d 7 +2d 12 (6)
i cirpeak_2 ＝max(d 0 +2d 12 ,d 0 +2d 7 )(7)
wherein d 7 Representing vector V 7 Duty cycle, d 12 Representing vector V 12 Duty cycle, i cirpeak_1 The peak value, i, of the loop current, which represents SQ1 to SQ8 cirpeak_2 The peak value of the loop current from SQ9 to SQ12 is shown. Notably, d 0 +2d 12 +2d 7 ≥d 0 +2d 12 At the same time, d 0 +2d 12 +2d 7 ≥d 0 +2d 7 Therefore, as can be seen from formulas (6) and (7), the peak value of the circulating currents of SQ9 to SQ12 is not larger than the peak value (i) of the circulating currents of SQ1 to SQ8 cirpeak_1 ≥i cirpeak_2 ). For this purpose, V is used within-30 DEG to 30 DEG from the zero sequence circulation performance optimization angle 0 The switching sequences of SQ9 to SQ12 are optimal switching sequences for the start vector. Similarly, V is used in the range of-30 DEG to 30 DEG 7 As a starting vector, there are 4 sets of switching sequences for loop optimization; in V form 12 For the start vector, there are 4 sets of switching sequences for loop optimization. For this purpose, in sector I, based on the preferred switch combinations in the preferred vectors and from the point of view of zero sequence loop optimization, the present patent designs 12 sets of optimal switch timings, constituting the optimal switch timings, as shown in table 4. The 12 groups of optimal switch time sequences meet the circulation change rate mode p 5 And p 6 。
Note that, in table 4, only 12 optimum switching timings in the sector of-30 ° to 30 ° are given, and the construction method of the optimum timings in table 4 is adopted, so that the optimum 12 switching timings in the remaining 5 sectors can be further constructed, and 5×12=60 optimum switching timings can be obtained, as in tables 5 to 9. The total of 72 groups of optimal switching time sequences on the whole vector plane are uniformly distributed in each large sector, and each large sector comprises 12 groups of optimal switching time sequences.
TABLE 4 optimal switching timing within sector I
In the table, SQ I-1 ～SQ I-12 Indicating the switching sequences 1-12, V in sector I i () represents equivalent output voltage vector V i The symbol represents circulation change rate, which is +1 or-1;
TABLE 5 optimal switching timing within sector II
TABLE 6 optimal switching timing within sector III
TABLE 7 optimal switching timing in fan IV
Table 8 optimum switching timing in sector V
Table 9 optimum switching timing within sector VI
(3) Based on 72 kinds of optimal switching time sequences, a modulation wave expression and an action mode thereof required by generating the optimal switching time sequences are designed to form a carrier modulation scheme, and the method specifically comprises the following steps:
based on the volt-second balance principle, taking 12 groups of optimal switching time sequences in the sector I (-30 degrees) as an example, the duty ratios of three basic vectors of the optimal switching time sequences can be obtained by a reference voltage synthesis equation:
wherein u is a ,u b And u c A, B and C-phase voltages, respectively, representing reference voltages; u (u) α And u β Representing the components of the reference voltage in a two-phase stationary coordinate system; v (V) 7α And V 7β Representing the basis vector V 7 A component in a two-phase stationary coordinate system; v (V) 12 Alpha and V 12 Beta represents a base vector V 12 A component in a two-phase stationary coordinate system; d, d 7 ,d 12 And d 0 Representing the basis vector V 7 ,V 12 And V 0 A corresponding duty cycle.
Solving to obtain the duty ratio expression of three basic vectors:
wherein u is a ,u* b And u is c Expressed in V DC The three-phase voltage per unit value is the reference.
The time of action of all the sequence basis vectors in Table 4 can be obtained according to equation (9). To generate each optimal switching sequence in table 4, a switching sequence carrier modulation implementation scheme needs to be studied to avoid complex on-line optimization. For the optimal switching time sequence in table 4, the present patent also proposes 6 corresponding switching action modes, as shown in fig. 5.
Two modulated waves (u) are determined according to the selected optimal switching timing mx1 And u mx2 ) And the size logic judgment is carried out with an inverted triangle carrier (carrier), the corresponding logic level is set according to the switch action mode, and the simple on-line generation of the optimal switch time sequence is realized.
To generate the proposed 72 optimal switching sequences, the present patent devised 6 switching patterns:
action A: two modulated waves u for each phase mx1 And u mx2 Satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 The carrier wave is not more than, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube; when the carrier wave is in the rising stage, no high-low level switching is performed, and the low level is maintained;
action B: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 The carrier wave is not more than, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube; when the carrier wave is in the rising stage, no high-low level switching is performed, and the high level is maintained;
action C: the two modulated waves of each phase satisfy 0 < u mx1 ＜1，0＜u mx2 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 The carrier wave is not less than the first threshold value, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube; when the carrier wave is in the rising phase, if the modulation wave u mx2 The carrier wave is not less than the first threshold value, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube;
action D: the two modulated waves of each phase satisfy 0 < u mx1 ＜1，0＜u mx2 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 The carrier wave is not less than the preset value, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube; when the carrier wave is in the rising phase, if the modulation wave u mx2 The carrier wave is not less than the preset value, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube;
action E: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, no high or low is madeLevel switching, maintaining a low level; when the carrier wave is in the rising phase, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 The carrier wave is not more than, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube;
action F: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, no high-low level switching is performed, and the high level is maintained; when the carrier wave is in the rising phase, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 And the carrier wave is not more than, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube.
Thus, to generate the optimal switching sequences in table 4, it is necessary to derive the relevant modulated wave expressions and their corresponding operation patterns.
With SQ in sector I in Table 4 I-1 And SQ I-2 For example, both modulated wave expressions and their modes of action are derived. FIGS. 6 (a) and 6 (b) show SQ I-1 And SQ I-2 As can be seen from fig. 6 and equation (9), SQ is a modulated wave and its operation mode in the staggered carrier frame I-1 And SQ I-2 The modulation wave and the action mode of the modulation wave are as follows:
wherein u is ma1 And u ma2 Two modulated waves representing phase a; u (u) mb1 And u mb2 Two modulated waves representing phase b; u (u) mc1 And u mc2 Two modulated waves representing phase C, action C and Action D represent Action modes.
Based on the same approach, we further derive the modulation wave expressions and their operation modes for the remaining 10 switch timings in table 4:
wherein u is ma1 And u ma2 Two modulated waves representing phase a; u (u) mb1 And u mb2 Two modulated waves representing phase b; u (u) mc1 And u mc2 Two modulated waves representing phase c; u is a 、u* b And u is c Respectively expressed as V DC The three-phase voltage per unit value is the standard; the actions A to F represent 6 switch Action modes;
Similarly, the modulation wave expressions of 10 switch timings in sector II and their operation modes are derived from table 5:
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according to the modulated waves and their operation modes (10) to (15) in table 4 and the modulated waves and their operation modes (16) to (21) in table 5, the modulated waves and their operation modes of 72 optimal timings in the entire vector plane are sorted to obtain:
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wherein u is max1 And u max2 Two modulated waves representing the maximum phase of the three-phase voltage; u (u) mid1 And u mid2 Two modulated waves representing the intermediate phases of the three-phase voltages; u (u) min1 And u min2 Two modulated waves representing the minimum phase of the three-phase voltage; u is max 、u* mid And u is min Respectively expressed as V DC The unit value of the maximum phase, the intermediate phase and the minimum phase of the three-phase voltage is used as a reference; x is I, III or V, which corresponds to sector I, sector III or sector V in FIG. 3; y is II, IV or VI, which corresponds to the sector II, the sector IV or the sector VI in the figure 3; z=1 to 12, representing 12 sets of optimal switching timings within each sector; when x=i, if u b >u* c Modulated wave expression of group Z timing in sector I and SQ for switching operation mode I-ZA Representing otherwise, using SQ I-ZB A representation; when x=iii, if u c >u* a Modulated wave expression of group Z time sequence in sector III and SQ for switch operation mode III-ZA Representing otherwise, using SQ III-ZB A representation; when x=v, if u a >u* b Modulated wave expression of group Z time sequence in sector V and SQ for switch operation mode V-ZA Representing otherwise, using SQ V-ZB A representation; when y=ii, if u b >u* a Modulated wave expression of group Z time sequence in sector II and SQ for switch operation mode II-ZA Representing otherwise, using SQ II-ZB A representation; when y=iv, if u c >u* b Modulated wave expression of group Z time sequence in sector IV and SQ for switch operation mode IV-ZA Representing otherwise, using SQ IV-ZB A representation; when y=vi, if u a >u* c Modulated wave expression of group Z time sequence in sector VI and SQ for switch operation mode VI-ZA Representing otherwise, using SQ VI-ZB And (3) representing.
As can be seen from comparison between the formulas (22) and (45), the modulation wave expressions and the switching operation modes of the 12 groups of optimal switching sequences in the same sector are different, which provides a certain switching sequence redundancy for the subsequent relevant pulse width modulation algorithm. It should be noted that, from the reference voltage forming angle, 12 switch time sequences in any sector have redundancy, and any switch time sequence can synthesize the output reference voltage, and 12 switch time sequence modulation areas in the same sector are completely overlapped. From the point of view of minimum loop current change rate and zero common mode voltage output, the 12 switching timings all have the optimal switching timings. However, as can be seen from equation (7) and tables 4 to 9, for the same reference voltage, different switching sequences have different duty cycle allocations, which provides a huge optimization space for further optimizing other integral indexes, and further optimizes other parameters under the condition of simultaneously optimizing zero sequence circulation and eliminating common mode voltage, such as considering ac ripple optimization, or realizing single optimum of zero sequence circulation. In addition, the redundant switching sequences in tables 4-9 have different carrier expressions, and the redundancy also provides space for simplifying the implementation scheme of the modulation algorithm, and simultaneously provides an optimized space for minimizing the switching times required by sector switching.
Therefore, 72 optimal time sequences and carrier modulation realization methods thereof provided by the patent not only can solve the problem of overlarge zero sequence circulation of the existing zero common mode voltage algorithm, but also can utilize redundancy of abundant optimal switch time sequences to derive other related novel modulation algorithms, and further optimize single index or comprehensively optimize multiple key indexes on the basis of eliminating common mode voltage and optimizing zero sequence circulation. For example, single optimization of zero sequence circulation is realized, ripple is optimized, carrier modulation implementation scheme is simplified, the switching times required by sector switching are minimized, and the like.
Aiming at the targets of further optimizing the switching loss and the zero sequence circulation, the patent activates different optimal time sequences in different sectors to derive two different modulation algorithms which are named ZCMV1 and ZCMV2.
Example 1
This embodiment provides a modulation strategy ZCMV1 that further optimizes switching losses: firstly, in order to ensure that no extra switching loss is added in the same sector, only 1 group of switching time sequences need to be selected in each sector in fig. 3; meanwhile, in order to reduce switching loss at the time of sector switching, it is necessary to ensure as few switching times as possible between different switching timings. Based on the above principle, the switching sequence SQ is selected among the 72 sets of optimal switching sequences in tables 4 to 9 I-2 、SQ II-8 、SQ III-2 、SQ IV-8 、SQ V-2 And SQ VI-8 And corresponds to sectors I through VI, as shown in table 10.
Table 10 vector planar switch timing
SQ is obtained from the switching sequences of the formulas (22) to (45) and Table 10 x-2 And SQ Y-8 Is described as a modulation wave expression and its mode of action:
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wherein, X takes I, III or V, corresponding to sector I, sector III or sector V in fig. 3; y is II, IV or VI, corresponding to sector II, sector IV or sector VI in FIG. 3.
When u is mid <When 0, the reference vector is positioned in the sector I, III or V, and the activation process of the switch time sequence is as follows;
a) When u is a ＝u* max When the reference vector is located in sector I, if u b >u* c Select SQ I-2A Activate timing 2, otherwiseSelect SQ I-2B Activating the time sequence 2;
b) When u is b ＝u* max When the reference vector is in sector III, if u c >u* a Select SQ III-2A Activate timing 2, otherwise select SQ III-2B Activating the time sequence 2;
c) When u is c ＝u* max When the reference vector is located in the sector V, if u a >u* b Select SQ V-2A Activate timing 2, otherwise select SQ V-2B Activating the time sequence 2;
when u is mid >When 0, the reference vector is positioned in the sector II, the sector IV or the sector VI, and the activation process of the switch time sequence is as follows;
a) When u is a ＝u* min When the reference vector is in sector IV, if u c >u* b Select SQ IV-8A Activate sequence 8, otherwise select SQ IV-8B Activating the time sequence 8;
b) When u is b ＝u* min When the reference vector is in sector VI, if u a >u* c Select SQ VI-8A Activate sequence 8, otherwise select SQ VI-8B Activating the time sequence 8;
c) When u is c ＝u* min When the reference vector is in sector II, if u b >u* a Select SQ II-8A Activate sequence 8, otherwise select SQ II-8B Activating the time sequence 8;
according to the optimal switching sequence SQ in each sector I-2 、SQ II-8 、SQ III-2 、SQ IV-8 、SQ V-2 And SQ VI-8 The corresponding modulation wave and the action mode formulas (46) and (47) activate the corresponding switching time sequence, so that a corresponding novel pulse width modulation algorithm can be generated, and the switching loss is further optimized on the basis of eliminating the common-mode voltage and optimizing the zero sequence circulation.
Therefore, according to the switching sequence, the modulation wave expressions (46) to (47) and the sector judgment conditions in table 10, the corresponding modulation wave and the operation mode thereof are selected, and the selected switching sequence is activated, thereby realizing the proposed derivative modulation strategy ZCMV1.
Fig. 10 (a) to 11 (c) are experimental results of a conventional zero common mode voltage modulation strategy (zmv) and a zmv 1 modulation strategy proposed in the present patent, which are obtained at a modulation degree of 0.4. Experimental results show that the ZCMV1 provided by the patent realizes common-mode voltage optimization, and meanwhile, compared with the existing zero common-mode voltage modulation strategy, the ZCMV1 realizes circulation optimization.
Example 2
This embodiment provides a modulation strategy ZCMV2 that is further optimized for zero sequence loop current. Taking sector I and sector II as an example, each sector is divided into 4 sub-sectors (sector 1 to sector 4), as shown in fig. 7. The activation sequences of ZCMV2 in sector I and sector II are shown in Table 11.
Table 11 ZCMV2 switching sequences at-30 to 90 degrees
Sequence SQ I-1 Acting on sector I-1 in FIG. 7, the three-phase voltages satisfy u a >0>u c >u b SQ in the corresponding modulated wave expression and operation mode expression (22) X-1B The method comprises the steps of carrying out a first treatment on the surface of the Sequence SQ I-2 Acting on sector I-2 in FIG. 7, the three-phase voltages satisfy u a >0>u b >u c SQ in the corresponding modulated wave expression and operation mode expression (23) X-2A . The modulation expressions and the action modes corresponding to the two can be unified as follows:
similarly, sequence SQ I-3 Acting on sector I-3 in FIG. 7, the three-phase voltages satisfy u a >0>u c >u b SQ in the corresponding modulated wave expression and operation mode expression (24) X-3B The method comprises the steps of carrying out a first treatment on the surface of the Sequence SQ I-5 Acting on sector I-4 in FIG. 7, the three-phase voltages satisfy u a >0>u b >u c SQ in the corresponding modulated wave expression and operation mode expression (26) X-5A . The modulation expressions and the action modes corresponding to the two can be unified as follows:
similarly, sequence SQ II-7 Acting on sector II-1 in FIG. 7, the three-phase voltages satisfy u a >u b >0>u c SQ in the corresponding modulated wave expression and operation mode expression (40) Y-7B The method comprises the steps of carrying out a first treatment on the surface of the Sequence SQ II-8 Acting on sector II-2 in FIG. 7, the three-phase voltages satisfy u b >u a >0>u c SQ in the corresponding modulated wave expression and operation mode expression (41) Y-8A . The modulation expressions and the action modes corresponding to the two can be unified as follows:
similarly, sequence SQ II-10 Acting on sector II-3 in FIG. 7, the three-phase voltages satisfy u a >u b >0>u c SQ in the corresponding modulated wave expression and operation mode expression (43) Y-10B The method comprises the steps of carrying out a first treatment on the surface of the Sequence SQ II-12 Acting on sector II-4 in FIG. 7, the three-phase voltages satisfy u b >u a >0>u c SQ in the corresponding modulated wave expression and operation mode expression (45) Y-12A . The modulation expressions and the action modes corresponding to the two can be unified as follows:
from the above analysis, the region of the same modulation wave expression and operation mode can be regarded as 1 sub-sector. Therefore, sub-sector 1 and sub-sector 2 in each sector are combined into sub-sector s, and sub-sector 3 and sub-sector 4 are combined into sub-sector r. Finally, each large sector is divided into two sub-sectors (sub-sector s and sub-sector r) and generalized to the entire vector plane as in fig. 8.
From fig. 8, the expression (48) to (51) are combined to obtain a unified expression of the modulation wave and the operation mode of ZCMV2, as shown in table 12.
Table 12 unified expression of modulation wave and operation mode of ZCMV2
To implement ZCMV2, it is necessary to further analyze the boundaries of different sectors.
As can be seen from fig. 8, the boundary expression of the sector I and the sector II is:
as can be seen from fig. 8, the boundary expression of the sub-sector Is and the sub-sector Ir of the sector I Is:
as can be seen from fig. 8, the boundary expression of the sub-sector IIs and the sub-sector IIr of the sector II is:
As can be seen from the equation (53) and the equation (54), the boundary between the sub-sector s and the sub-sector r in each large sector can be unified as:
also, as can be seen from fig. 8, the boundary between sector II and sector III satisfies:
as can be seen from fig. 8, the boundary between the sub-sector IIIs and the sub-sector IIIr in the sector III satisfies:
as known from equation (57), the boundary between sub-sector s and sub-sector r in sector III can be unified as:
from equation (52) and equation (56), the demarcation line for each large sector can be unified as:
also, as can be seen from equation (55) and equation (58), the boundaries of the sub-sectors s and r in the vector plane can be unified as:
to sum up, for the zmv 2 modulation scheme, the activation process of the switching sequence is:
(1) When u is mid <At 0, the vector is located in sector I, III or V (x= I, III or V): at this time, if u max －u* min >1/2, the reference vector is located in the sub-sector r, the select (49) activates the switch sequence SQ X-3 And SQ X-5 The method comprises the steps of carrying out a first treatment on the surface of the Conversely, the reference vector is located in the sub-sector s, and the selective (48) activates the switch sequence SQ X-1 And SQ X-2 ；
(2) When u is mid >At 0, the vector is in sector II, IV or VI (y=ii, IV or VI): at this time, if u max －u* min >1/2, the reference vector is located in the sub-sector r, the select (51) activates the switch sequence SQ Y-10 And SQ X-12 The method comprises the steps of carrying out a first treatment on the surface of the Conversely, the reference vector is located in the sub-sector s, and the selective (50) activates the switch sequence SQ Y-7 And SQ Y-8 。
Based on the optimal switching sequence SQ selected in each sector X-1 、SQ X-2 、SQ X-3 、SQ X-5 、SQ Y-7 、SQ Y-8 、SQ Y-10 SQ (SQ) Y-12 Corresponding modulation wave and action mode thereof, generating corresponding novel pulse width modulation algorithm, and realizing further optimization of zero sequence loop current on the basis of eliminating common-mode voltage and optimizing zero sequence loop current.
Thus, corresponding to the zmv 2 modulation strategy, the implementation flowchart is as in fig. 9, comprising: input three-phase voltage per unit value, solve for V DC Maximum phase per unit value u of three-phase voltage as reference max Intermediate phase per unit value u mid Minimum phase per unit value u min The sector is determined by the sector determination process, and the modulation wave and its operation mode are determined according to table 12, so as to activate the corresponding optimal switching time sequence.
The experimental conditions are that the voltage of a direct current bus is 400V, the switching frequency is 5kHz, the load resistance is 10 omega, and the filter inductance of the converter is 5mH.
Fig. 10 (a) to 10 (c) and fig. 12 (a) to 12 (c) show experimental results of a conventional zero common mode voltage modulation scheme and a zmv 2 modulation scheme according to the present patent, which are obtained at a modulation degree of 0.4. Experimental results show that the ZCMV2 of the patent realizes common-mode voltage optimization, and meanwhile, compared with the existing zero common-mode voltage modulation strategy, the ZCMV2 realizes circulation optimization. The loop optimization under the optimum common mode voltage can be realized by combining different switch time sequences in tables 4 to 9. Therefore, the zero sequence circulation is optimized while the common-mode voltage is eliminated based on two modulation strategies derived from the optimal switching time sequence. The optimal switch time sequence and the carrier modulation implementation scheme thereof provided by the patent are the basis of the design of the zero common-mode voltage elimination and circulation optimization related modulation algorithm, and have important significance. The 72 optimal time sequences and the carrier modulation realization method thereof provide greater flexibility and optimization potential, not only can design a novel modulation algorithm to simultaneously optimize zero sequence circulation and eliminate common-mode voltage and solve the problem of overlarge zero sequence circulation of the existing zero common-mode voltage algorithm, but also can utilize the redundant time sequences in the provided optimal time sequences to derive other related optimal modulation algorithms, and further optimize single index or comprehensively optimize multiple key indexes on the basis of eliminating the common-mode voltage and optimizing the zero sequence circulation.
Claims (10)
1. A switch time sequence optimization design and a carrier modulation implementation method thereof for zero sequence circulation suppression and common mode voltage elimination of two parallel converters are characterized by comprising the following steps:
step 1, obtaining all possible switch state combinations according to a mathematical model of two parallel converters, and selecting 18 optimal switch combinations which simultaneously meet the circulation change rate of +/-1 and the common mode voltage of 0 from all the switch state combinations based on the mapping relation between the switch state combinations and the zero sequence circulation and the common mode voltage;
step 2, designing 72 optimal switching time sequences of a modulation area covering the whole vector plane based on 18 optimal switching combinations and considering constraint conditions of zero sequence loop current balance and switching times;
step 3, designing a modulation wave expression and an action mode thereof required by generating the optimal switching time sequence based on 72 optimal switching time sequences to form a carrier modulation implementation scheme;
and 4, based on 72 optimal switch time sequences and carrier modulation implementation schemes, deriving a new pulse width modulation algorithm by using different optimal time sequences at different positions of a vector plane, and realizing optimal single index or comprehensive optimization of multiple key indexes on the basis of optimizing zero sequence circulation and eliminating common-mode voltage.
2. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage elimination of two parallel converters according to claim 1, wherein the 18 optimal switch combinations are:
in the table, the bracket in the switch combination indicates the equivalent output voltage vector, and the two parameters in the bracket respectively indicate the voltage vectors of the corresponding first converter and the corresponding second converter, V i Representing an i-th equivalent output voltage vector; zero sequence circulation change rate is set as V DC Carrying out per unit by taking/(2L) as a basic value, and defining the zero sequence circulation positive direction as the firstOne flow to the second.
3. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage elimination of two parallel converters according to claim 2, wherein the design modulation area covers 72 optimal switch timings of the whole vector plane in consideration of constraint conditions of zero sequence loop current balance and switching times, and specifically comprises: dividing the whole vector plane into 6 sectors, wherein 10 optimal switch combinations exist in each divided sector, the constraint condition that the total switch times of zero sequence circulation balance and switch time sequences are less than or equal to 12 times is considered, the switch time sequences are designed pertinently based on the 10 optimal switch combinations, and finally 12 optimal switch time sequences in each sector are obtained;
The 6 sectors are: -30 DEG is sector I, 30-90 DEG is sector II, 90-150 DEG is sector III, 150-210 DEG is sector IV, 210-270 DEG is sector V, 270-330 DEG is sector VI; the method for determining the 12 optimal switching time sequences of the sector I comprises the following steps:
three basic vectors of the synthetic reference voltage in sector I are V 0 、V 7 And V 12 Corresponding to 10 switch combinations in the optimal switch combinations; when the switch time sequence is V 0 As an initial vector, 12 alternative switching time sequences are designed and obtained under the constraint conditions of zero sequence loop current balance and switching times;
the zero sequence circulation of 12 alternative switch time sequences is a time domain piecewise function and is classified into 6 circulation modes p 1 ～p 6 The method comprises the steps of carrying out a first treatment on the surface of the The 6 circulation patterns are further classified into two categories according to the magnitude of the circulation peak:
i cirpeak-1 ＝d 0 +2d 7 +2d 12 (1)
i cirpeak_2 ＝max(d 0 +2d 12 ，d 0 +2d 7 ) (2)
wherein d 0 Representing vector V 0 Duty cycle, d 7 Representing vector V 7 Duty cycle, d 12 Representing vector V 12 Duty cycle, i cirpeak_1 A loop peak value, i representing the time sequence of 8 alternative switches cirpeak_2 A peak value of the circulation current representing the time sequence of 4 alternative switches; according to i cirpeak_1 ≥i cirpeak_2 4 circulation optimized switch time sequences are obtained through screening, and the corresponding circulation mode is p 5 Or p 6 ；
Based on the above classification, in V 7 For the initial vector, 4 switching time sequences with optimized circulation are obtained, and the corresponding circulation mode is p 5 Or p 6 The method comprises the steps of carrying out a first treatment on the surface of the In V form 12 For the initial vector, 4 switching time sequences with optimized circulation are obtained, and the corresponding circulation mode is p 5 Or p 6 ；
Thus, 12 optimal switching sequences are obtained in sector I, the loop current mode of which is p 5 Or p 6 The method comprises the steps of carrying out a first treatment on the surface of the Similarly, the optimal 12 switching time sequences in other 5 sectors are obtained, and all the switching time sequences meet the circulating current mode p 5 Or p 6 ：
1) The three base vectors for sector II are V 0 、V 7 And V 8 Corresponding to 10 switch combinations, selecting different combination column writing sequences to obtain 12 optimal switch time sequences;
2) The three base vectors of sector III are V 0 、V 8 And V 9 Corresponding to 10 switch combinations, selecting different combination column writing sequences to obtain 12 optimal switch time sequences;
3) The three base vectors of sector IV are V 0 、V 9 And V 10 Corresponding to 10 switch combinations, selecting different combination column writing sequences to obtain 12 optimal switch time sequences;
4) The three basic vectors of sector V are V 0 、V 10 And V 11 Corresponding to 10 switch combinations, selecting different combination column writing sequences to obtain 12 optimal switch time sequences;
5) The three base vectors for sector VI are V 0 、V 11 And V 12 Corresponding to 10 switch combinations, selecting different combination column writing sequences to obtain 12 optimal switch time sequences;
finally, 72 optimal switching sequences are obtained on the whole vector plane.
4. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage cancellation of two parallel converters according to claim 3, wherein the 6 loop current patterns p 1 ～p 6 The method comprises the following steps:
wherein V is x 、V y 、V z Representing three base vectors corresponding to different sectors.
5. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage cancellation of two parallel converters according to claim 3, wherein the 72 optimal switch timings are:
12 optimal switching sequences SQ in the sector I I-1 ～SQ I-12 The method comprises the following steps:
in the table, SQ I-1 ～SQ I-12 Indicating the switching sequences 1-12, V in sector I i () represents equivalent output voltage vector V i The symbol represents circulation change rate, which is +1 or-1;
12 optimal switching sequences SQ in the sector II II-1 ～SQ II-12 The method comprises the following steps:
12 optimal switching sequences SQ within the sector III III-1 ～SQ III-12 The method comprises the following steps:
12 optimal switching sequences SQ within the sector IV IV-1 ～SQ IV-12 The method comprises the following steps:
12 optimal switching sequences SQ in the sector V V-1 ～SQ V-12 The method comprises the following steps:
12 optimal switching sequences SQ within the sector VI VI-1 ～SQ VI-12 The method comprises the following steps:
6. the method for implementing the optimal design of the switch time sequence and the carrier modulation thereof for the zero sequence loop current suppression and the common mode voltage elimination of the two parallel converters according to claim 5, wherein the designing the modulation wave expression and the action mode thereof required for generating the optimal switch time sequence based on 72 optimal switch time sequences specifically comprises:
Based on the volt-second balance principle, three basic vectors of each optimal switching time sequence are used for determining a reference voltage synthesis equation:
wherein u is a ,u b And u c A, B and C-phase voltages, respectively, representing reference voltages; u (u) α And u β Representing the components of the reference voltage in a two-phase stationary coordinate system; v (V) Xα And V Xβ Representing the basis vector V X A component in a two-phase stationary coordinate system; v (V) Yα And V Yβ Representing the basis vector V Y A component in a two-phase stationary coordinate system; v (V) Zα And V Zβ Representing the basis vector V Z A component in a two-phase stationary coordinate system; d, d X ,d Y And d Z Representing the basis vector V X ,V Y And V Z A corresponding duty cycle;
obtaining the duty ratio expression of three basic vectors according to the reference voltage synthesis equation, wherein the duty ratio of the three basic vectors uses the three-phase voltage per unit value u a ,u* b And u is c Represented by u a ,u* b And u is c Expressed as DC bus voltage V DC The three-phase voltage per unit value is the standard;
according to the optimal switching time sequences and the duty ratio of the basic vector, obtaining the modulation wave expressions and the action modes of all the switching time sequences:
wherein u is max1 And u max2 Two modulated waves representing the maximum phase of the three-phase voltage; u (u) mid1 And u mid2 Two modulated waves representing the intermediate phases of the three-phase voltages; u (u) min1 And u min2 Two modulated waves representing the minimum phase of the three-phase voltage; u is max 、u* mid And u is min Respectively expressed as V DC The unit value of the maximum phase, the intermediate phase and the minimum phase of the three-phase voltage is used as a reference; x is I, III or V, which corresponds to the sector I, the sector III or the sector V; y is II, IV or VI, and corresponds to the sector II, the sector IV or the sector VI; z=1 to 12, representing 12 sets of optimal switching timings within each sector; when x=i, if u b >u* c Modulated wave expression of group Z timing in sector I and SQ for switching operation mode I-ZA Representing otherwise, using SQ I-ZB A representation; when x=iii, if u c >u* a Modulated wave expression of group Z time sequence in sector III and SQ for switch operation mode III-ZA Representing otherwise, using SQ III-ZB A representation; when x=v, if u a >u* b Modulated wave expression of group Z time sequence in sector V and SQ for switch operation mode V-ZA Representing otherwise, using SQ V-ZB A representation; when y=ii, if u b >u* a Modulated wave expression of group Z time sequence in sector II and SQ for switch operation mode II-ZA Representing otherwise, using SQ II-ZB A representation; when y=iv, if u c >u* b Modulated wave expression of group Z time sequence in sector IV and SQ for switch operation mode IV-ZA Representing otherwise, using SQ IV-ZB A representation; when y=vi, if u a >u* c Modulated wave expression of group Z time sequence in sector VI and SQ for switch operation mode VI-ZA Representing otherwise, using SQ VI-ZB And (3) representing.
7. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage elimination of two parallel converters according to claim 6, wherein the 6 switch action modes are specifically designed as follows:
action A: two modulated waves u for each phase mx1 And u mx2 Satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 Carrier wave is not more than and high in outputThe level is used for switching on the corresponding switching tube, otherwise, the low level is output to switch off the corresponding switching tube; when the carrier wave is in the rising stage, no high-low level switching is performed, and the low level is maintained;
action B: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 The carrier wave is not more than, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube; when the carrier wave is in the rising stage, no high-low level switching is performed, and the high level is maintained;
action C: the two modulated waves of each phase satisfy 0 < u mx1 ＜1，0＜u mx2 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 The carrier wave is not less than the first threshold value, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube; when the carrier wave is in the rising phase, if the modulation wave u mx2 The carrier wave is not less than the first threshold value, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube;
action D: the two modulated waves of each phase satisfy 0 < u mx1 ＜1，0＜u mx2 < 1; when the carrier wave is in the descending stage, if the modulation wave u mx1 The carrier wave is not less than the preset value, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube; when the carrier wave is in the rising phase, if the modulation wave u mx2 The carrier wave is not less than the preset value, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube;
action E: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, no high-low level switching is performed, and the low level is maintained; when the carrier wave is in the rising phase, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 The carrier wave is not more than, the high level is output to turn on the corresponding switching tube, otherwise, the low level is output to turn off the corresponding switching tube;
action F: the two modulated waves of each phase satisfy 0 < u mx2 ＜u mx1 < 1; when the carrier wave is in the descending stage, no high-low level switching is performed, and the high level is maintained; when the carrier wave is in the rising phase, if the modulation wave u mx1 Not less than carrier wave and modulating wave u mx2 And the carrier wave is not more than, the low level is output to turn off the corresponding switching tube, otherwise, the high level is output to turn on the corresponding switching tube.
8. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage cancellation of two parallel converters according to claim 7, wherein the new pulse width modulation algorithm specifically comprises:
based on the six sectors, only 1 group of switch time sequences is selected in each sector, meanwhile, the switching times among different switch time sequences are as few as possible, and the switch time sequences SQ are selected in 72 groups of optimal switch time sequences I-2 、SQ II-8 、SQ III-2 、SQ IV-8 、SQ V-2 And SQ VI-8 ；
The modulation wave expression of the switch time sequence and the action mode thereof are designed as follows:
wherein X is I, III or V, which corresponds to the sector I, the sector III or the sector V; y is II, IV or VI, and corresponds to the sector II, the sector IV or the sector VI;
when u is mid <When 0, the reference vector is positioned in the sector I, III or V, and the activation process of the switch time sequence is as follows;
a) When u is a ＝u* max When the reference vector is located in sector I, if u b >u* c Select SQ I-2A Activate timing 2, otherwise select SQ I-2B Activating the time sequence 2;
b) When u is b ＝u* max When the reference vector is in sector III, if u c >u* a Select SQ III -2A activation sequence 2, otherwise, select SQ III-2B Activating the time sequence 2;
c) When u is c ＝u* max When the reference vector is located in the sector V, if u a >u* b Select SQ V-2A Activate timing 2, otherwise select SQ V-2B Activating the time sequence 2;
when u is mid >When 0, the reference vector is positioned in the sector II, the sector IV or the sector VI, and the activation process of the switch time sequence is as follows;
a) When u is a ＝u* min When the reference vector is in sector IV, if u c >u* b Select SQ IV-8A Activate sequence 8, otherwise select SQ IV-8B Activating the time sequence 8;
b) When u is b ＝u* min When the reference vector is in sector VI, if u a >u* c Select SQ VI-8A Activate sequence 8, otherwise select SQ VI-8B Activating the time sequence 8;
c) When u is c ＝u* min When the reference vector is in sector II, if u b >u* a Select SQ II-8A Activate sequence 8, otherwise select SQ II-8B Timing 8 is activated.
9. The switch timing optimization design and carrier modulation implementation method for zero sequence loop current suppression and common mode voltage cancellation of two parallel converters according to claim 7, wherein the new pulse width modulation algorithm specifically comprises:
the 6 sectors are further divided into 4 sub-sectors, which are named as sub-sector 1-sub-sector 4; selecting 1 group of optimal switching sequences in 12 groups of optimal switching sequences in each sub-sector: the optimal switching sequence for sector X is SQ X-1 、SQ X-2 、SQ X-3 SQ (SQ) X-5 X is I, III or V; the optimal switching sequence of sector Y is SQ Y-7 、SQ Y-8 、SQ Y-10 SQ (SQ) Y-12 Y is II, IV or VI；
Synthesizing the switching time sequences in all sectors, and designing the time sequence SQ according to the modulation wave expression and the switching action mode X-1 、SQ X-2 、SQ X-3 、SQ X-5 、SQ Y-7 、SQ Y-8 、SQ Y-10 SQ (SQ) Y-12 The unified expression of the modulation wave and the action mode thereof is:
as can be seen from the above equation, the regions with the same modulation wave expression and operation mode can be regarded as 1 sub-sector, and sub-sector 1 and sub-sector 2 are combined into sector s; the sub-sector 3 and the sub-sector 4 are combined into a sub-sector r; thus, the activation process of the switching sequence is:
when u is mid <At 0, the vector is located in sector I, III or V: at this time, if u max －u* min >1/2, the reference vector is located in the sub-sector r, the select (32) activates the switch sequence SQ X-3 And SQ X-5 The method comprises the steps of carrying out a first treatment on the surface of the Conversely, the reference vector is located in the sub-sector s, and the selective (31) activates the switch sequence SQ X-1 And SQ X-2 ；
When u is mid >At 0, the vector is located in sector II, IV or VI: at this time, if u max －u* min >1/2, the reference vector is located in the sub-sector r, the select (34) activates the switch sequence SQ Y-10 And SQ X-12 The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, the reference vector is located in the sub-fanZone s, selective (33) activation switch sequence SQ Y-7 And SQ Y-8 。
10. A computer storage medium, characterized in that the computer storage medium stores an executable program, and the executable program is executed by a processor to implement the switch timing optimization design for zero sequence loop current suppression and common mode voltage cancellation of two parallel converters and the carrier modulation implementation method thereof according to any one of claims 1 to 9.
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