CN116741740A

CN116741740A - Package structure and method for manufacturing the same

Info

Publication number: CN116741740A
Application number: CN202310885112.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2023-07-18
Filing date: 2023-07-18
Publication date: 2023-09-12

Abstract

The embodiment of the disclosure provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a circuit substrate and a semiconductor structure arranged on the circuit substrate, and the circuit substrate comprises: the semiconductor device comprises an insulating structure, a conductive circuit, a first conductive pad and a first dummy pad structure. The conductive circuit is embedded in the insulating structure; the first conductive connecting pad is arranged on one side of the insulating structure and is electrically connected to the conductive circuit; the first dummy pad structure is arranged on one side of the insulating structure and extends into the insulating structure, and the semiconductor structure is connected to the first conductive pad and the first dummy pad structure of the circuit substrate through conductive connectors and dummy connectors.

Description

Package structure and method for manufacturing the same

Technical Field

Embodiments of the present disclosure relate to a package structure and a method of manufacturing the same.

Background

In the semiconductor packaging technology, various semiconductor members may be bonded to a wiring substrate through a connector such as a solder ball; the connecting piece is arranged between the semiconductor component and the circuit substrate and can be connected to the connecting pad on the circuit substrate. The connector and its associated bond pads (e.g., during mounting of heat sinks, reliability testing, etc.) may be subject to stresses from the semiconductor component and/or the circuit substrate that, if the bond strength of the bond pad to an adjacent material layer in the circuit substrate is low, may cause cracking at the contact interface of the bond pad and the material layer, thereby affecting the reliability of the device.

Disclosure of Invention

According to at least one embodiment of the present disclosure, there is provided a package structure including a wiring substrate and a semiconductor structure disposed on the wiring substrate, wherein the wiring substrate includes: an insulating structure; a conductive line embedded in the insulating structure; the first conductive connecting pad is arranged on one side of the insulating structure and is electrically connected to the conductive circuit; and a first dummy pad structure disposed on the one side of the insulating structure and extending into the insulating structure, the semiconductor structure being bonded to the first conductive pad and the first dummy pad structure of the circuit substrate through conductive connectors and dummy connectors.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the first dummy pad structure and the dummy connection member are electrically floating and electrically isolated from the conductive trace.

In the package structure provided according to at least one embodiment of the present disclosure, the conductive connection member and the dummy connection member are disposed side by side in a horizontal direction parallel to the main surface of the circuit substrate, and the dummy connection member is closer to a corner of the semiconductor structure than the conductive connection member.

In a package structure provided according to at least one embodiment of the present disclosure, the first dummy pad structure includes: the first dummy connection pad is arranged on the surface of one side, close to the semiconductor structure, of the insulating structure; and a first dummy reinforcing member embedded in the insulating structure, surrounded by the insulating structure, and connected with the first dummy pad.

In accordance with at least one embodiment of the present disclosure, a package structure is provided in which at least a portion of the first dummy bonding pad is integrally formed with at least a portion of the first dummy reinforcing member.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the first dummy reinforcement member includes a dummy via connected to the first dummy pad and extending from the first dummy pad into the insulating structure in a direction perpendicular to the main surface of the circuit substrate and away from the conductive connection.

In the package structure provided according to at least one embodiment of the present disclosure, the first dummy reinforcing means further includes: and a dummy line embedded in the insulating structure, and the dummy via is located between the first dummy pad and the dummy line in a first direction perpendicular to the main surface of the circuit substrate.

In the package structure provided according to at least one embodiment of the present disclosure, a width of the dummy line is greater than a width of the dummy via, and the width of the dummy line and the width of the dummy via are widths in a second direction parallel to the main surface of the wiring substrate.

In the package structure provided according to at least one embodiment of the present disclosure, the conductive line includes a first conductive line and a second conductive line embedded in different insulation layers of the insulation structure, and the first conductive line and the second conductive line are electrically connected to each other through a conductive via; the dummy line is arranged on the same layer as the first conductive line, and the overlapping area of the dummy line and the second conductive line in the first direction is smaller than the overlapping area of the first conductive line and the second conductive line in the first direction.

In the package structure provided according to at least one embodiment of the present disclosure, the circuit substrate further includes: a first protective layer is located on a side of the insulating structure adjacent to the semiconductor structure and on sides of the conductive pad and the first dummy pad structure in a direction parallel to a major surface of the circuit substrate, spaced apart from the conductive pad, and spaced apart from at least a portion of a sidewall of the first dummy pad structure.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the first protection layer has an opening, at least a portion of the first dummy pad structure is located in the opening, and the dummy connector covers a surface of the first dummy pad structure remote from the insulating structure and extends into the opening to cover a sidewall of the at least a portion of the first dummy pad structure.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the first protection layer has an opening, at least a portion of the first dummy pad structure is located in the opening, the first dummy pad structure has a first sidewall and a second sidewall, the first protection layer covers a first portion of a surface of the first dummy pad structure remote from the insulating structure and the first sidewall, and the dummy connection covers a second portion of the surface of the first dummy pad structure and the second sidewall.

In the package structure provided according to at least one embodiment of the present disclosure, the semiconductor structure further includes: the second dummy pad structure at least comprises a second dummy pad, the second conductive pad and the second dummy pad are positioned on one side of the semiconductor structure, which is close to the circuit substrate, the second conductive pad is electrically connected with the conductive connecting piece, and the second dummy pad structure is connected with the dummy connecting piece and is electrically floating.

In the package structure provided according to at least one embodiment of the present disclosure, the semiconductor structure further includes: the second protection layer is positioned on one side of the semiconductor structure close to the circuit substrate and covers the side walls of the second conductive pads and the second dummy pads and part of the surfaces of the side walls of the second conductive pads and the second dummy pads close to the circuit substrate.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the semiconductor structure further includes a dielectric structure, the second dummy bonding pad structure further includes a second dummy reinforcing member, the second dummy bonding pad is located on a surface of the dielectric structure, which is close to the circuit substrate, and the second dummy reinforcing member is embedded in the dielectric structure and is connected to the second dummy bonding pad.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: the heat dissipation component is arranged on one side of the semiconductor structure far away from the circuit substrate and is attached to the semiconductor structure.

In a package structure provided according to at least one embodiment of the present disclosure, the semiconductor structure includes: and (3) a chip: and a package substrate electrically connected to the chip and located between the chip and the circuit substrate, the conductive connection member and the dummy connection member being disposed on a side of the package substrate away from the chip.

At least one embodiment of the present disclosure provides a method for manufacturing a package structure, including: forming a circuit substrate, comprising: forming an insulating structure and a conductive line, wherein the conductive line is embedded in the insulating structure; forming a first conductive pad on one side of the insulating structure, the first conductive pad being electrically connected to the conductive trace through a conductive via; and forming a first dummy pad structure disposed on the one side of the insulating structure and extending into the insulating structure; and providing a semiconductor structure and bonding the semiconductor structure to the circuit substrate, wherein the semiconductor structure has a conductive connection and a dummy connection, and bonding the semiconductor structure to the circuit substrate includes bonding the conductive connection and the dummy connection to the first conductive pad and the first dummy pad structure of the circuit substrate, respectively.

In a method for manufacturing a package structure according to at least one embodiment of the present disclosure, forming the first dummy pad structure includes: forming a first dummy reinforcement member in the insulating structure; and forming a first dummy bonding pad on a side of the first dummy reinforcement member and the insulating structure near the semiconductor structure, and the first dummy bonding pad and the first dummy reinforcement member being connected to each other.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the first dummy reinforcement member includes a dummy via, and forming the first dummy pad structure includes: forming an opening in the insulating structure; and forming a metal material in the opening of the insulating structure and on a surface of the insulating structure on a side thereof close to the semiconductor structure, wherein a part of the metal material located in the opening forms the dummy via and a part of the metal material located on the surface of the insulating structure forms the first dummy pad.

In the package structure provided in accordance with at least one embodiment of the present disclosure, forming the first dummy pad structure further includes: before the opening is formed, a dummy line embedded in the insulating structure is formed, and the opening is formed to expose the dummy line so that the dummy via hole subsequently formed in the opening is connected with the dummy line, wherein the dummy line and the dummy via hole together constitute the first dummy reinforcing member.

In the package structure provided in accordance with at least one embodiment of the present disclosure, at least a portion of the first dummy reinforcing member and the conductive via include the same material and are formed by the same patterning process.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure; fig. 1B illustrates a schematic top view of a partial region of a circuit substrate of a package structure in which a dummy pad is located, according to some embodiments of the present disclosure; fig. 1C illustrates a schematic top view of a partial region of a circuit substrate of a package structure in which conductive pads are located, according to some embodiments of the present disclosure.

Fig. 2A illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure; fig. 2B illustrates a schematic top view of a package structure according to some embodiments of the present disclosure.

Fig. 3 shows a schematic cross-sectional view of a package structure according to further embodiments of the present disclosure.

Fig. 4A to 4P show schematic cross-sectional views of structures of various steps in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Fig. 5 shows a schematic cross-sectional view of a package structure according to further embodiments of the present disclosure.

Fig. 6 illustrates a schematic cross-sectional view of a package structure according to further embodiments of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Referring to fig. 1A, in some embodiments, a package structure 50 includes a wiring substrate 10 and a semiconductor structure S1. The semiconductor structure S1 has a conductive connection member 12 and a dummy connection member 13, and may be bonded to the wiring substrate 10 through the conductive connection member 12 and the dummy connection member 13. For example, the wiring substrate 10 may be a printed circuit board (printed circuit board; PCB), and the semiconductor structure S1 may include the substrate 20 and the chip 30; the chip 30 is flip-chip arranged on the substrate 20 and is electrically connected with the substrate 20; in some embodiments, a heat sink 40 may also be provided on the chip 30 to facilitate heat dissipation from the chip 30. However, the disclosure is not limited thereto.

The conductive connection member 12 and the dummy connection member 13 may be disposed between the wiring substrate 10 and the semiconductor structure S1 in a direction perpendicular to the main surface of the wiring substrate 10; for example, the semiconductor structure S1 is electrically connected to the wiring substrate 10 through a plurality of conductive connection pieces 12; the dummy connection 13 may be located at the periphery of the conductive connection 12 near the edge (e.g., corner) of the semiconductor structure S1 and electrically floating. The conductive connection member 12 and the dummy connection member 13 may include the same or different materials, and for example, may be solder balls (solder balls); for example, the conductive connector 12 and the dummy connector 13 may be BGA connectors.

Referring to fig. 1A to 1C, for example, a circuit substrate 10 includes an insulating structure 6 and conductive traces, such as conductive lines and/or conductive vias, embedded in the insulating structure. The insulating structure may include a plurality of insulating layers arranged in a stacked manner. The wiring substrate 10 further includes a conductive pad 9a and a dummy pad 9b disposed on the insulating structure 6, the conductive pad 9a being electrically connectable to a conductive wiring embedded in the insulating structure. For example, as shown in fig. 1A and 1C, the conductive pad 9a may be connected to the conductive wire 7 through the conductive via 8; alternatively, the conductive pads 9a may extend directly into the openings of the insulating structure to electrically connect with the conductive lines 7. The dummy pad 9b and the conductive pad 9a may be disposed side by side and spaced apart from each other, the dummy pad 9b being electrically isolated from the conductive pad 9a and other conductive traces; for example, as shown in fig. 1A and 1B, no conductive member may be provided under the dummy pad 9B.

The conductive connection member 12 is bonded with the conductive pad 9a to provide an electrical connection between the semiconductor structure S1 and the wiring substrate 10; the dummy connectors 13 are bonded with the dummy pads 9b to connect and fix the dummy connectors 13 to the wiring substrate 10. The solder resist layer 11 may be disposed on the insulating structure 6, and may be located at a side of the conductive pads 9a and the dummy pads 9b in a direction parallel to the main surface of the wiring substrate 10, and may be spaced apart from the conductive pads 9a and the dummy pads 9 b.

In the package structure 50, the dummy connectors 13 may serve as a supporting structure to provide support for the semiconductor structure S1 and may protect the conductive connectors 12 located inside thereof. The support performance of the semiconductor structure S1 and the structural strength of the package structure can be improved by providing the dummy connectors 13. Generally, since the dummy connectors 13 and the dummy pads 9b are electrically floating and are not electrically connected to the conductive traces in the wiring substrate 10, the dummy pads 9b are typically disposed only on the surface of the insulating structure 6 on the side close to the semiconductor structure S1.

However, in some embodiments, the dummy connectors 13 and the dummy pads 9b may be subjected to a larger stress, for example, in a large-sized package structure, the dummy connectors 13 near the corners of the semiconductor structure S1 may be subjected to a larger stress from the semiconductor structure S1 and/or the wiring substrate 10; for example, the stress may include tensile stress, shearing force, etc., and may be generated during the process of installing the heat sink 40, performing reliability test such as temperature cycle, etc., but the disclosure is not limited thereto. In the case where the dummy connectors 13 are subjected to stress, the stress is also transmitted to the dummy pads 9b bonded to the dummy connectors 13. In the circuit substrate 10 of this embodiment, since the dummy pad 9b is disposed only on the surface of the insulating structure 6, the bonding strength between the dummy pad 9b and the structure below (e.g., insulating structure) is low, and thus when the dummy connector 13 and the dummy pad 9b are subjected to a large stress, cracks may be generated between the dummy pad 9b and the structure below (e.g., at the contact interface between the dummy pad 9b and the insulating structure 6), which may affect the structural stability and the device reliability of the package structure.

In view of the above technical problems, embodiments of the present disclosure provide a package structure and a method for manufacturing the same, where the package structure includes a circuit substrate and a semiconductor structure. The circuit substrate comprises an insulating structure, a conductive circuit, a first conductive connecting pad and a first dummy connecting pad structure; the conductive circuit is embedded in the insulating structure, and the first conductive connecting pad is arranged on one side of the insulating structure and is electrically connected to the conductive circuit; the first dummy pad structure is disposed on the one side of the insulating structure and extends into the insulating structure. The semiconductor structure is disposed on the circuit substrate and is bondable to the conductive pads and the first dummy pad structure of the circuit substrate through conductive connectors and dummy connectors.

In the embodiment of the disclosure, by arranging the first dummy pad structure and the dummy connection member, the supporting strength of the semiconductor structure can be improved, and the conductive connection member can be protected, so that the structural strength and the device reliability of the whole packaging structure are improved. Also, the first dummy pad structure is formed to extend into the insulating structure of the circuit substrate, the bonding strength of the first dummy pad structure and the circuit substrate may be improved, so that cracks may be prevented from occurring between the first dummy pad structure and an adjacent layer (e.g., insulating structure) when the dummy connection and the first dummy pad structure are subjected to a large stress, and thus the structural strength of the package structure and the device reliability may be further improved.

Fig. 2A illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure, and fig. 2B illustrates a schematic top view of a package structure according to some embodiments of the present disclosure.

Referring to fig. 2A, in some embodiments, a package structure 500a includes a wiring substrate 150 and a semiconductor structure S1. The semiconductor structure S1 is disposed on the circuit substrate 150 and is bonded to the circuit substrate 150. For example, the wiring substrate 150 may be a printed circuit board, such as a high density interconnect (high density interconnector; HDI) board. For example, the circuit substrate 150 may include an insulating structure 120, a conductive line embedded in the insulating structure 120, and a conductive pad P1 and a dummy pad structure 124 disposed on a side of the insulating structure 120 near the semiconductor structure S1; the conductive pad P1 is electrically connected to the conductive line; the dummy pad structure 124 is disposed on a side of the insulating structure 120 near the semiconductor structure S1, and extends into the insulating structure 120 to be electrically isolated from the conductive line. The semiconductor structure S1 may be bonded to the conductive pads 212 and the dummy pad structures 124 of the wiring substrate 150 through the conductive connectors 212 and the dummy connectors 213. In some embodiments, the conductive pad 212 and the dummy pad structure 124 may also be referred to as a first conductive pad and a first dummy pad structure, respectively. Herein, a "dummy" member means that the member is electrically floating, i.e., electrically isolated from other conductive lines/electronics, etc.

For example, the conductive connection member 212 and the dummy connection member 213 may be located between the wiring substrate 150 and the semiconductor structure S1 in a direction (e.g., direction D1) perpendicular to the main surface of the wiring substrate 150; the conductive connection 212 may provide an electrical connection between the semiconductor structure S1 and the circuit substrate 150; the dummy connectors 213 and the dummy pad structures 124 are electrically floating, i.e., electrically isolated from the circuit substrate 150 and conductive traces and/or devices in the semiconductor structure S1. The dummy connectors 213 may serve as support structures providing support for the semiconductor structure S1. In addition, the dummy connection 213 may be disposed outside the conductive connection 212, i.e., on a side of the conductive connection 212 near an edge (e.g., corner) of the semiconductor structure S1, so that protection of the conductive connection 212 may be also provided.

For example, as shown in fig. 2B, the semiconductor structure S1 may have a square planar shape in a top view, which may be square or rectangular. For example, the semiconductor structure S1 has sides a1, a2, b1, b2; the side edges a1 and a2 extend parallel to each other along the direction D2 and are opposite to each other in the direction D3; the side edges b1 and b2 extend parallel to each other along the direction D3 and are opposite to each other in the direction D2; the directions D2 and D3 are both directions parallel to the main surface of the wiring substrate 150, and may intersect each other, for example, substantially perpendicular to each other. Directions D2 and D3 may be referred to as horizontal directions; for example, direction D2 may be referred to as a first horizontal direction and direction D3 may be referred to as a second horizontal direction. The semiconductor structure S1 has a plurality of corners (corners) C, each corner C being an internal angle formed by the intersection of adjacent sides of the plurality of sides a1, a2, b1, b2 of the semiconductor structure S1.

In some embodiments, the plurality of conductive connectors 212 and the dummy connectors 213 are disposed side by side in a horizontal direction parallel to the wiring substrate 150, for example, may be arranged in an array including a plurality of rows and a plurality of columns along the directions D1 and D2. It should be understood that the plurality of small square areas in fig. 2B each represent an area where the plurality of conductive connectors 212 and the plurality of dummy connectors 213 are located, and the plurality of small square areas are shown adjacent to and in contact with each other for the sake of simplicity of the drawing, but do not represent that the plurality of conductive connectors and the plurality of dummy connectors are in contact with each other; in fact, a plurality of conductive connectors and dummy connectors may be located in respective checkered areas, but spaced apart from each other in the horizontal direction (as shown in fig. 2A). The planar shape of the conductive connection member and the dummy connection member in the top view may be circular, elliptical or the like, and the present disclosure is not limited thereto.

In some embodiments, the dummy connectors 213 are closer to the corners of the semiconductor structure S1 than the conductive connectors 212. For example, the dummy connectors 213 are disposed in regions near the plurality of corners C of the semiconductor structure S1, i.e., the plurality of dummy connectors 213 are each located at one side of the plurality of conductive connectors 212 near the plurality of corners C. For example, one or more dummy connectors 213 are disposed in a region near each corner C, and for each corner C, the distance from any one of the conductive connectors 212 is smaller than the distance from the corresponding dummy connector 213 in the same horizontal direction parallel to the main surface of the circuit substrate 150.

For example, the plurality of conductive connectors 212 and the dummy connectors 213 may be arranged in a plurality of connector rows and a plurality of connector columns, each connector row including the plurality of conductive connectors 212 and/or the dummy connectors 213 arranged along the direction D2; each connector column includes a plurality of conductive connectors 212 and/or dummy connectors 213 arranged along direction D3. Directions D2 and D3 may be referred to as the row and column directions of the connector, respectively. The plurality of connector rows may include one or more end connector rows proximate to a side or edge of the semiconductor structure S1 and the plurality of connector columns may include one or more end connector columns proximate to a side or edge of the semiconductor structure S1. The dummy connectors may be disposed at positions near corners of the semiconductor structure in the end connector rows and the end connector columns; for example, the connectors at the opposite ends in the direction D2 in each end connector row are dummy connectors, and the connectors at the opposite ends in the direction D3 in each end connector column are dummy connectors. Only conductive connectors may be included in the connector rows and connector columns that are distal from respective sides or edges of the semiconductor structure (i.e., distal from corners of the semiconductor structure) and no dummy connectors are provided.

For example, the plurality of connector rows includes one or more connector rows r1 proximate to a side a1 of the semiconductor structure S1 extending in the row direction (e.g., direction D2), one or more connector rows r1 proximate to a side a2 extending in the row direction, and one or more connector rows r2 distal to sides a1 and a2 (i.e., located in a middle region of the semiconductor structure); the plurality of connector columns includes one or more connector columns c1 proximate to a side b1 of the semiconductor structure S2 extending in a column direction (e.g., direction D3), one or more connector columns c1 proximate to a side b2 extending in the column direction, and one or more connector columns c2 distal from sides b1 and b 2. The connector row r1 and the connector column c1 are an end connector row and an end connector column. Each of the end connector rows r1 includes therein (e.g., two) dummy connectors 213 disposed at opposite ends of the row in the direction D2 and conductive connectors 212 disposed between the dummy connectors 213 in the direction D2. Each of the end connector columns c1 includes therein (for example, two) dummy connectors 213 disposed at opposite ends of the column in the direction D3 and conductive connectors 212 disposed between the dummy connectors 213 in the direction D3.

During the formation, operation and testing of the package structure (e.g., during the mounting of a heat sink or the performance of reliability tests such as temperature cycling), the stress experienced by the connection between the semiconductor structure S1 and the circuit substrate 150 (e.g., from the semiconductor structure S1 and/or the circuit substrate 150) is typically greater in the connection near the corner C region of the semiconductor structure S1. The stress may include tensile stress, shear stress, and the like. For example, the dummy connection 213 near the corner C of the semiconductor structure S1 may have a greater stress than the conductive connection 212 far from the corner of the semiconductor structure S1. In the embodiment of the present disclosure, the dummy connectors 213 are disposed at positions close to the corners of the semiconductor structure, so that the conductive connectors 212 may be disposed at positions far from the corners, thereby protecting the conductive connectors 212 from being affected in their electrical characteristics and the like due to the large stress applied at the corners while ensuring the supporting strength of the semiconductor structure S1. That is, disposing the dummy connectors 213 in the regions near the corner C and disposing the conductive connectors 212 in the regions far from the corner is beneficial to improving the supporting strength of the semiconductor structure S1 and improving the structural strength and stability of the whole package structure, and meanwhile, the conductive connectors are prevented from being subjected to larger stress to adversely affect the electrical properties and other performances, thereby improving the reliability of the device of the package structure in terms of electrical property.

In some embodiments, one or more dummy connectors 213 may be disposed proximate at least one corner (e.g., each corner) of the plurality of corners C, such as two dummy connectors 213 disposed corresponding to one corner C. For example, the centers of the two dummy connectors 213 may be offset from the diagonal line of the corner C, which is close to the center, and the other corner C, and at least portions of the two dummy connectors 213 may be disposed at opposite sides of the diagonal line. In some embodiments, disposing a plurality of (e.g., two) dummy connectors 213 in a region near a corner C and/or offsetting the diagonal lines of the plurality of dummy connectors 213 from the corner C may be advantageous to distribute stress near the corner region, such that the stress experienced by a single dummy connector 213 is relatively small, thereby further improving the overall support performance of the dummy connector and improving the device reliability of the package structure. However, the disclosure is not limited thereto. The positions, the number, etc. of the dummy connectors 213 disposed near each corner may be set and adjusted accordingly according to actual product needs.

Referring to fig. 2A, in some embodiments, the conductive pad P1 of the circuit substrate 150 may be electrically connected with the conductive via V1 or V2, and thus electrically connected with the conductive trace in the circuit substrate 150 through the conductive via. Herein, the conductive via may be or include a blind via (blind via) located on a surface layer of the circuit substrate and not penetrating through the entire circuit substrate, a through via (through via) penetrating through the entire circuit substrate, or a buried via (buried via) located on an inner layer of the circuit substrate and not penetrating through the entire circuit substrate. For example, the conductive via V1 may be a blind via, and the conductive via V2 may be a through via.

In some embodiments, the dummy pad structure 124 includes a dummy pad DP and a dummy reinforcement member RC connected to each other. The dummy pad DP is disposed on a surface of the insulating structure 120 near the semiconductor structure S1; the dummy reinforcing member RC is embedded in the insulating structure 120 and surrounded by the insulating structure 120. The dummy pad DP and the dummy reinforcing member RC may also be referred to as a first dummy pad and a first dummy reinforcing member. The dummy bonding pad DP is bonded to and directly contacts the dummy connection 213, and the dummy reinforcement member RC is connected to the dummy bonding pad DP and configured to increase the structural strength of the dummy bonding pad structure 124 and the bonding strength thereof before the adjacent material layer. In some embodiments, the dummy pad structure 124 may comprise a metal material and may be the same or different material as the conductive pad P1, the conductive vias V1, V2. In some embodiments, at least a portion of the dummy bonding pad DP and at least a portion of the dummy reinforcement member RC are integrally formed and may not have a clearly visible interface therebetween, but the disclosure is not limited thereto. The contact area of the dummy connection pad structure and the insulating structure can be increased by arranging the dummy reinforcing member, and the dummy reinforcing member is embedded in the insulating structure and surrounded by the insulating structure, so that the integral bonding strength of the dummy connection pad structure and the insulating structure can be increased.

For example, the dummy reinforcement member RC may include a dummy via DV connected to the dummy pad DP, and may be located on a side of the dummy pad DP away from the dummy connector 213, extending from a surface of the dummy pad DP on the side away from the dummy connector 213 into the insulating structure 120 within the wiring substrate 150. For example, the dummy via DV may be a blind via, but the disclosure is not limited thereto. In some embodiments, the dummy pads DP and the dummy vias DV may comprise similar, but may be the same or different materials, e.g., may comprise the same or different metallic materials. For example, at least part of the dummy pads DP may be integrally formed with the dummy vias DV, or the dummy pads DP and the dummy vias DV may be each separately formed and connected to each other and directly contacted. The dummy via DV may comprise the same material as one or more of the conductive vias V1, V2, and may be formed by the same patterning process, for example. The width of the dummy via RC in a direction (e.g., direction D2) parallel to the main surface of the wiring substrate 150 is smaller than the width of the dummy pad DP in the direction.

In some embodiments, the circuit substrate 150 further includes a protection layer 125 and a protection layer 127 disposed on opposite sides of the insulating structure 120 in the direction D1; for example, the protection layer 125 is disposed on a side of the insulating structure 120 near the semiconductor structure S1, and the protection layer 127 is disposed on a side of the insulating structure 120 far from the semiconductor structure S1. The insulating structure 120 may be a single-layer or multi-layer structure; for example, the insulating structure 120 is a multi-layer structure and may include insulating layers 100, 105, 107, 115, 117. The insulating layer 100 may be located at or near a central region of the wiring substrate 150 in a direction D1 perpendicular to the main surface of the wiring substrate 150. Insulating layers 105 and 107 are on opposite sides of insulating layer 100 in direction D1, and insulating layers 115 and 117 are on sides of insulating layers 105 and 107, respectively, away from insulating layer 100 in direction D1. It should be understood that the number of insulating layers included in the insulating structure 120 shown in the drawings is merely illustrative, and the disclosure is not limited thereto. In some embodiments, insulating layers 115 and 117 are insulating layers of insulating structure 120 that are located on the outermost layer of wiring substrate 150, i.e., the insulating layer closest to protective layer 125 or in direct contact with protective layer 125.

In some embodiments, the conductive lines of the wiring substrate 150 may include conductive lines and conductive vias connected to each other; for example, the wire trace may include multiple layers of conductive wires M1a, M1b, M2a, M2b and one or more conductive vias V0; the conductive lines M1a and M1b may be located on opposite surfaces of the insulating layer 100 in the direction D1 and covered by insulating layers 105 and 107, respectively; the conductive lines M2a and M2b are located on the surfaces of the insulating layers 105 and 107 on the side away from the insulating layer 100 in the direction D1, respectively, and are covered with insulating layers 115 and 117, respectively. In some embodiments, the insulating layer 100 and the conductive lines on both sides thereof may be referred to as core layers (core layers) of the wiring substrate 150.

The conductive via V0 may be a buried via embedded in the insulating structure 120, for example, extending through the insulating layers 105, 100, and 107, and may be electrically connected with the multi-layered conductive lines M1a, M1b, M2a, M2b such that the multi-layered conductive lines M1a, M1b, M2a, M2b may be electrically connected with each other through one or more conductive vias V0. In some embodiments, the conductive via V0 may include a via body 110 and a conductive liner 111 surrounding the via body 110; the via body 110 may include a non-conductive material (e.g., an insulating material), for example, the via body 110 may include a resin material, but the disclosure is not limited thereto. In other embodiments, the via body 110 may also include a conductive material. The conductive liner 111 surrounds the sidewalls of the via body 110 and is connected to the conductive lines M1a, M1b, M2a, M2 b.

In some embodiments, conductive vias V1, V2 each connect conductive pad P1 to a respective conductive line and/or conductive via V0; for example, the conductive via V1 is embedded in the insulating layer 115 and extends through the insulating layer 115 to connect the conductive pad P1 to the conductive line M2a; the conductive via V2 may extend through the entire circuit substrate 150, for example, through all of the insulating layers 100, 105, 107, 115, 117 of the insulating structure 120, and may extend through one or more of the plurality of layers of conductive lines M1a, M1b, M2a, M2b to electrically connect with the conductive lines; that is, the conductive pad P1 may be electrically connected with one or more of the conductive lines M1a, M1b, M2a, M2b through the conductive via V2. In some embodiments, the dummy vias DV are located at the sides of the conductive vias V1, V2 in a direction parallel to the main surface of the wiring substrate 150 and are spaced apart from the conductive vias V1, V2 by a distance. The dummy via DV is electrically floating, i.e. electrically isolated from the conductive trace in the circuit substrate.

In some embodiments, protective layers 125 and 127 cover the surface of insulating structure 120 and/or conductive lines; for example, the protective layers 125 and 127 may include solder masks (solder masks). The protection layer 125 is located on one side of an outermost insulating layer (e.g., insulating layer 115) in the insulating structure 120, which is close to the semiconductor structure S1, and the protection layer 127 is located on one side of an outermost insulating layer (e.g., insulating layer 117) on the other side of the insulating structure 120, which is far from the semiconductor structure S1.

For example, on the side of the circuit substrate 150 near the semiconductor structure S1, the conductive pad P1 and the dummy pad DP are located on the surface of the insulating layer 115 near the semiconductor structure S1, and protrude toward the semiconductor structure S1 in the direction D1 from the surface of the insulating layer 115. The protection layer 125 may be located at a side of the conductive pad P1 and the dummy pad structure 124 (e.g., the dummy pad DP thereof) in a direction parallel to the main surface of the wiring substrate 150 (e.g., a horizontal direction including D2), and may be spaced apart from the conductive pad P1 and from at least a portion of the sidewall of the dummy pad structure 124; for example, the protective layer 125 may be completely spaced apart from the dummy pad structure 124 without contacting sidewalls of the dummy pad structure 124 (e.g., sidewalls of the dummy pad). For example, the protection layer 125 has a plurality of openings, at least portions of the conductive pad P1 and the dummy pad structure 124 (e.g., the dummy pad DP) are each located in a corresponding opening of the protection layer 125, and each dimension (e.g., width, area, etc. in the horizontal direction) of the conductive pad P1 and the dummy pad DP is smaller than the dimension of the corresponding opening, such that the conductive pad P1 and the dummy pad DP are spaced apart from the protection layer 125.

In some embodiments, the conductive connection 212 covers at least a surface of the conductive pad P1 near the semiconductor structure S1; the dummy connection 213 covers at least the surface of the dummy contact pad DP on the side close to the semiconductor structure S1. In this embodiment, since the conductive pads P1 and the dummy pads DP are disposed in the openings of the protection layer 125 and spaced apart from the protection layer 125, respectively, the bonding of the conductive connectors 212 and 213 with the corresponding pads can be facilitated. For example, the conductive connection 212 may further extend into the opening of the protection layer 125 to cover and contact the sidewall of the conductive pad P1; the dummy connectors 213 may further extend into openings of the protection layer 125 to cover and contact sidewalls of at least a portion of the dummy pad structure 124 (e.g., the dummy pad DP), such as may completely cover sidewalls of the dummy pad DP. However, the disclosure is not limited thereto.

In some embodiments, in the dummy pad structure 124, the dummy pad DP is located on a surface of the insulating layer 115 near the semiconductor structure S1 side and protrudes from the surface of the insulating layer 115; the dummy reinforcing structure RC (e.g., the dummy via RC) may be embedded in one or more insulating layers of the insulating structure 120, and a sidewall of the dummy reinforcing structure RC and/or a surface of a side remote from the dummy pad DP may be covered by the insulating structure 120 and directly contact with the insulating structure 120. For example, the dummy via RC may be embedded in the outermost insulating layer 115 of the insulating structure 120 near the semiconductor structure S1, but the disclosure is not limited thereto.

In some embodiments, for the dummy via RC and the conductive via V1 both embedded in the insulating layer 115, a height h1 of the dummy via RC in a direction D1 perpendicular to the main surface of the circuit substrate 150 may be greater than a height h2 of the conductive via V1 in the direction D1. For example, the dummy via RC may extend from the surface of the insulating layer 115 on the side close to the semiconductor structure S1 to the surface of the insulating layer 105 on the side close to the insulating layer 115 in the direction D1, and the height h1 of the dummy via RC may be substantially equal to the thickness of the insulating layer 115; the conductive via V1 extends in the direction D1 from the surface of the insulating layer 115 on the side close to the semiconductor structure S1 to the surface of the conductive line M2a on the side away from the insulating layer 105, and the height h2 of the conductive via V1 is smaller than the thickness of the insulating layer 115.

It should be understood that the heights of the dummy vias RC shown in the figures are merely illustrative, and the disclosure is not limited thereto. For example, in other embodiments, the height h1 of the dummy via RC may also be smaller than the thickness of the insulating layer 115 or greater than the thickness of the insulating layer 115; for example, the dummy via RC may further extend into one or more of the other insulating layers 105, 100, 107, 117 of the insulating structure 120. In some examples, the dummy via RC may extend throughout the entire insulating structure 120, i.e., through all insulating layers, from a first surface of the insulating structure 120 near the semiconductor structure S1 to a second surface of the insulating structure 120 remote from the semiconductor structure S2, the first and second surfaces being opposite to each other in the direction D1, and being, for example, a surface of the insulating layer 115 near the semiconductor structure S2 side and a surface of the insulating layer 117 near the semiconductor structure S2 side, respectively; in this example, the surface of the dummy via RC on the side away from the dummy pad DP may be covered by the protective layer 127 or may be exposed by the protective layer 127.

With continued reference to fig. 2A, in some embodiments, the wiring substrate 150 may also have one or more conductive pads on a side remote from the semiconductor structure S1, which may be electrically connected to corresponding conductive lines through conductive vias, blind vias, and the like. The conductive pad P3 is schematically shown on the side of the circuit substrate 150 away from the semiconductor structure S1 and electrically connected to the conductive via V2, but the disclosure is not limited thereto. In some embodiments, the conductive pad (e.g., the conductive pad P3) on the side of the circuit substrate 150 away from the semiconductor structure S1 may be exposed in the opening of the protection layer 127, and may be used for electrical connection with other electronic devices, or may be used as an electrical test point for electrical testing of the circuit substrate and the package structure, but the disclosure is not limited thereto. In other examples, the conductive pad P3 may be completely covered by the protection layer 127 without being exposed.

In some embodiments, the semiconductor structure S1 may be or include any type of semiconductor device, such as a chip, a semiconductor package structure, or the like. For example, the semiconductor structure S1 may be a flip chip ball grid array (flip chip ball grid array; FCBGA) package structure, and may include a package substrate 200, a chip 300, a conductive connector 212, and a dummy connector 213. The chip 300 may be flip-chip mounted on the package substrate 200 and electrically connected to the package substrate 200. The package substrate 200 may be located between the chip 300 and the circuit substrate 150 in the direction D1; the conductive connection 212 and the dummy connection 213 may be disposed at a side of the package substrate 200 remote from the chip 300, wherein the conductive connection 212 may be electrically connected to the chip 300 through the package substrate 200. For example, the conductive connector 212 and the dummy connector 213 may be BGA connectors, but the disclosure is not limited thereto. In this embodiment, the conductive connection member 212 and the dummy connection member 213 may be a part included in the semiconductor structure S1, and are connected to the circuit substrate 150 as external connection points of the semiconductor structure S1 and disposed between the circuit substrate 150 and the package substrate 200 of the semiconductor structure S1, but the disclosure is not limited thereto.

For example, the chip 300 may be an integrated circuit chip, such as a System On Chip (SOC) or any other type of chip. The type of chip 300 may be selected according to actual product requirements and is not limited by the present disclosure. For example, chip 300 may include a substrate, a device layer, and conductive bumps 301; the substrate may be or include a semiconductor substrate such as a silicon substrate; the device layer is disposed on one side of the substrate and may include active devices (e.g., transistors), passive devices (e.g., capacitors), or combinations thereof, and an interconnect structure through which the devices may be connected to each other; conductive bump 301 is located on a side of the device layer away from the substrate and may be electrically connected to various devices on the substrate through an interconnect structure; the conductive bump 301 may serve as an external connection point for the chip 300. For example, the chip 300 is flip-chip disposed on the package substrate 200 such that a side thereof having the conductive bump 301 faces the package substrate 200 and may be electrically connected with the package substrate 200 through the conductive bump 301.

The package substrate 200 may include conductive traces (e.g., conductive lines and/or conductive vias, etc.) and pads disposed on opposite sides thereof in a direction D1 perpendicular to the major surface of the circuit substrate. For example, the conductive bumps 301 of the chip 300 may be bonded and electrically connected to conductive pads (not shown) on the side of the package substrate 200 near the chip and electrically connected to conductive traces in the package substrate 200 through the conductive pads.

The package substrate 200 may include a plurality of conductive pads 201 and dummy pad structures 204 on a side away from the chip 300 and near the circuit substrate 150. The dummy pad structure 204 may include a dummy pad 202. The conductive connection piece 212 is disposed on the conductive pad 201 and electrically connected to the conductive pad 201, so as to be electrically connected to the conductive circuit in the package substrate 200 and further electrically connected to the chip 300 through the conductive pad 201; the dummy connectors 213 are disposed on the dummy pads 202, and the dummy pads 202 are electrically floating, i.e. electrically isolated from other conductive pads 201 and conductive traces in the package substrate 200. That is, the dummy pads 202, the dummy connectors 213, and the dummy pad structures 124 are all electrically floating and electrically isolated from the semiconductor structure S1 and conductive traces and devices in the circuit substrate 150. In some embodiments, the dummy pad structure 124 of the circuit substrate 150 and the dummy pad structure 204 of the semiconductor structure S1 may be referred to as a first dummy pad structure and a second dummy pad structure, respectively.

For example, the conductive pads 201 of the semiconductor structure S1 and the conductive pads P1 of the circuit substrate 150 are disposed opposite to each other and corresponding (e.g., one-to-one) to each other, and are electrically connected by the conductive connection 212 therebetween; the dummy pad structures 204 (e.g., the dummy pads 202) of the semiconductor structure S1 and the dummy pad structures 124 of the circuit substrate 150 are disposed opposite to each other and in correspondence (e.g., one-to-one correspondence) and are connected to each other by the dummy connectors 213 therebetween.

In some embodiments, the package substrate 200 further includes a protective layer 205 disposed on a surface of the package substrate 200 near the circuit substrate 150; the protection layer 205 may cover part of the surfaces of the conductive pad 201 and the dummy pad 202, for example, may cover the sidewalls of the conductive pad 201 and the dummy pad 202 and part of the surfaces thereof on the side far away from the chip 300 and close to the circuit substrate 150, and expose the other part of the surfaces of the conductive pad 201 and the dummy pad 202 on the side far away from the chip 300. For example, the protection layer 205 has a plurality of openings, each of which exposes a portion of a surface of one of the plurality of conductive pads 201 and the dummy pads 202 on a side away from the chip 300, and a size (e.g., width, area, etc. in a horizontal direction) of each opening may be smaller than a size of the corresponding pad; conductive connection 212 and dummy connection 213 fill in the openings to connect to corresponding pads. For example, the respective edge portions of the conductive pads 201 and the dummy pads 202 are covered with the protective layer 205, and the center portions are connected with the corresponding connection members. In some embodiments, the protection layer 125 of the circuit substrate 150 and the protection layer 205 of the semiconductor structure S1 may be referred to as a first protection layer and a second protection layer, respectively.

In this embodiment, the dummy reinforcing member 204 may include only the dummy pad 202, and the corner of the semiconductor structure S1 corresponds to the corner of the package substrate 200, and in the case of a larger stress near the corner of the package substrate 200, since the edge portion of the dummy pad 202 is covered by the protection layer 205, the occurrence of cracks at the dummy pad 202 (e.g., between the dummy pad 202 and the material layer on the side thereof near the chip) may be avoided.

In some embodiments, the semiconductor structure S1 may further include an underfill layer (unrerfill layer) 302. An underfill layer 302 is disposed between the chip 300 and the package substrate 200 to fill the space therebetween and surround the protective conductive bump 301.

In some embodiments, the heat dissipation member 400 is disposed on a side of the semiconductor structure S1 away from the circuit substrate 150, and is attached to the semiconductor structure S1. For example, the heat dissipation member 400 may be disposed on the chip 300 to facilitate heat dissipation of the chip 300. For example, the heat dissipation member 400 may be mounted on the package substrate 200 or the circuit substrate 150, and attached to a surface of the chip 300 on a side away from the package substrate 200.

It should be understood that the present embodiment is illustrated by taking the semiconductor structure S1 as an FCBGA package, but the disclosure is not limited thereto. In other embodiments, the semiconductor structure S1 may be other types of package structures, such as a chip-on-wafer-on-substrate (CoWoS) package. The conductive connector 212 may also be other types of connectors besides BGA connectors, and the present disclosure is not limited to the type of semiconductor structure S1 and its connectors.

Fig. 3 shows a schematic cross-sectional view of a package structure 500b according to further embodiments of the present disclosure. The package structure 500b is similar to the package structure 500a, except that in the package structure 500b, the dummy reinforcing member RC further includes a dummy line DL. The differences between the two will be described in detail below, and other features of the package structure 500b that are the same as those of the package structure 500a will not be described again.

Referring to fig. 3, in some embodiments, the dummy pad structure 124 includes a dummy pad DP and a dummy reinforcement member RC, the dummy pad DP is located on a surface of the insulating structure 120 near the semiconductor structure S1 side, and the dummy reinforcement member RC may include a dummy via DV and a dummy line DL embedded in the insulating structure 120. For example, the dummy via DV is connected to the dummy line DL and the dummy pad DP, and is located between the dummy pad DP and the dummy line DL in the direction D1 perpendicular to the main surface of the wiring substrate 150. The dummy line DL may be disposed in the same layer as any one of the conductive lines of the circuit substrate 150, for example, may be disposed in the same layer as the conductive line M2a, and may be spaced apart from and electrically isolated from the conductive line M2 a. In this context, two members are "co-layer disposed" means that the two members are formed from the same conductive material layer by the same patterning process, or that the two members are embedded in the same insulating layer, or are located on the same surface of the same insulating layer. The dummy line DL is also electrically floating, i.e., electrically isolated from other conductive lines, etc., in the wiring substrate 150.

In some embodiments, the width of the dummy line DL may be greater than the width of the dummy via DV, the width of the dummy pad DP may be greater than the width of the dummy via DV, and the width of the dummy line DL may be greater than, less than, or substantially equal to the width of the dummy pad DP. Here, the widths of the dummy lines DL, the dummy vias DV, and the dummy pads DP all refer to widths thereof in a direction (e.g., direction D2) parallel to the main surface of the wiring substrate 150. In this embodiment, by making the dummy reinforcing member RC further include the dummy line DL, the contact area between the dummy pad structure 124 and the insulating structure 120 can be further increased, and the width of the dummy line DL is set to be larger than the width of the dummy via DV, so that a portion of the surface of the dummy line DL on the side close to the dummy connection member 213 can be covered with the insulating structure, so that the structural strength of the dummy pad structure 124 and the bonding strength of the dummy pad structure 124 and the insulating structure of the circuit substrate can be further improved, thereby avoiding occurrence of cracks between the dummy connection member 124 (e.g., the dummy pad DP thereof) and other material layers (e.g., the insulating structure 120) of the circuit substrate when the dummy connection member 213 is subjected to a large stress, and further improving the device reliability.

Referring to fig. 2A and 3, in some embodiments, the dummy pads DP and/or the dummy reinforcing members RC (e.g., dummy vias DV and/or dummy lines DL) of the dummy pad structure 124 may not overlap other conductive traces in the wiring substrate 150 in a direction D1 perpendicular to the major surface of the wiring substrate 150, or the overlapping area between the dummy reinforcing members 124 and the conductive traces of an adjacent layer may be smaller than the overlapping area between the conductive traces/vias of the same layer as the dummy lines DL and the conductive traces of an adjacent layer. For example, the dummy via DV and/or the dummy line DL may not overlap with the conductive line and/or the conductive via in the wiring substrate in the direction D1, or the dummy via DV and/or the dummy line DL may overlap with the conductive line and/or the conductive via in the wiring substrate in the direction D1, but the overlapping area is small.

For example, the conductive lines M1a and M2a are located in different (e.g., adjacent) insulating layers, and when the dummy line DL is in the same layer as the conductive line M2a, the overlapping area between the dummy line DL and the conductive line M1a is smaller than the overlapping area between the conductive line M2a and the conductive line M1a in the direction D1; for example, the overlapping area between the dummy line DL and the conductive line M1a may be zero, i.e., the dummy line DL may not overlap the conductive line M1 a. In some embodiments, by setting the overlap area between the dummy pad structure 124 and an adjacent conductive line to be small or zero, the possibility of parasitic capacitance between the dummy pad structure 124 and an adjacent conductive line may be avoided or reduced, thereby improving device reliability. Note that, herein, overlapping of two members (e.g., a first member and a second member) in a direction perpendicular to a main surface of a wiring substrate (e.g., a direction D1) means that orthographic projections of the two members on the main surface of the wiring substrate overlap each other, and an overlapping area of the two members in the direction means an area of a portion where orthographic projections of the first member and the second member on the main surface of the wiring substrate (e.g., a surface extending in a horizontal direction) overlap each other; if the two are not overlapped, the overlapped area is zero.

The embodiment of the disclosure provides a manufacturing method of a packaging structure, which comprises the following steps of: forming an insulating structure and a conductive line, wherein the conductive line is embedded in the insulating structure; forming a first conductive pad on one side of the insulating structure, the first conductive pad being electrically connected to the conductive trace through a conductive via; and forming a first dummy pad structure disposed on the one side of the insulating structure and extending into the insulating structure; the manufacturing method further comprises the steps of: providing a semiconductor structure and bonding the semiconductor structure to the circuit substrate, wherein the semiconductor structure has a conductive connection and a dummy connection, and bonding the semiconductor structure to the circuit substrate includes bonding the conductive connection and the dummy connection to the first conductive pad and the first dummy pad structure, respectively, of the circuit substrate.

In some embodiments, forming the first dummy pad structure includes: forming a first dummy reinforcement member in the insulating structure; and forming a first dummy bonding pad on a side of the first dummy reinforcement member and the insulating structure near the semiconductor structure, and the first dummy bonding pad and the first dummy reinforcement member being connected to each other. In some embodiments, at least a portion of the first dummy reinforcing member may comprise the same material and be formed by the same patterning process as the conductive via.

For example, fig. 4A to 4P illustrate schematic cross-sectional views of structures of various process steps in a method of manufacturing a package structure according to some embodiments of the present disclosure, wherein fig. 4A to 4O illustrate process steps of a method of manufacturing a circuit substrate according to some embodiments of the present disclosure.

Referring to fig. 4A, in some embodiments, the conductive layer 101 and the conductive layer 102 are formed on opposite sides of the insulating layer 100, and the insulating layer 100 may include an insulating material such as fiberglass, resin, FR4, and the like, and the conductive layers 101 and 102 may include a conductive material, for example, may include a metallic material such as copper, for example, a copper foil layer. For example, the conductive layer 101, the insulating layer 100, and the conductive layer 102 may be laminated together by a lamination (lamination) process. For example, the insulating layer 100 and the conductive layers 101, 102 may be copper clad laminates (Copper Clad Laminates) and may be used to form a core layer of a circuit substrate.

Referring to fig. 4A and 4B, the conductive layers 101 and 102 are subjected to a patterning process, and the patterned conductive layers 101 and 102 form conductive lines M1a and M1B; the patterning process may include photolithography and etching processes. For example, patterned photoresist may be formed on the sides of the conductive layers 101 and 102 away from the insulating layer 100, respectively, after which the conductive layers 101 and 102 are subjected to an etching process using the patterned photoresist as an etching mask to remove portions of the conductive layers 101 and 102, and remaining portions of the conductive layers 101 and 102 form the conductive lines M1a and M1b.

Referring to fig. 4B and 4C, in some embodiments, an insulating layer 105 and a conductive layer 106, and an insulating layer 107 and a conductive layer 108 are formed on opposite sides of the insulating layer 100, respectively. For example, the insulating layer 105 is formed on one side of the insulating layer 100 and covers the sidewall of the conductive line M1a and the surface thereof on the side away from the insulating layer 100; the conductive layer 106 is formed on the side of the insulating layer 105 remote from the insulating layer 100. An insulating layer 107 is formed on the opposite side of the insulating layer 100 from the insulating layer 105, and covers the sidewall of the conductive line M1b and the surface thereof on the side away from the insulating layer 100; the conductive layer 108 is located on the side of the insulating layer 107 remote from the insulating layer 100. In some embodiments, insulating layers 105 and 107 may comprise insulating materials such as resins, including, for example, prepregs (prepregs); the conductive layers 106 and 108 may comprise a conductive material, such as a metallic material including copper, for example, a copper foil layer. For example, the insulating layers 105 and 107 and the conductive layers 106 and 108 may be formed using a lamination process such as lamination.

Referring to fig. 4C and 4D, the structure shown in fig. 4C is subjected to a drilling process to form one or more openings 109, which may also be referred to as vias, in the structure. In some embodiments, the opening 109 extends through the structure shown in fig. 4C, i.e., from the surface of the conductive layer 106 on the side away from the insulating layer 105, through the conductive layer 106, the insulating layers 105, 100, 107, and the conductive layer 108, and to the surface of the conductive layer 108 on the side away from the insulating layer 107. In some embodiments, the opening 109 also extends through the conductive lines M1a and/or M1b such that sidewalls of the conductive lines M1a and/or M1b are exposed in the opening 109.

Referring to fig. 4E, a conductive layer 111 is formed on the conductive layers 106, 108 and in the opening 109. For example, the conductive layer 111 may form a side of the conductive layer 106 away from the insulating layer 105, a side of the conductive layer 108 away from the insulating layer 107, and line a surface of the opening 109 to cover the insulating layers 105, 100, 107 and the sidewalls of the conductive lines M1a, M1b exposed to the opening 109 and may be electrically connected to the conductive lines M1a, M1 b. In some embodiments, the conductive layer 111 may include a conductive material, for example, may include a metallic material such as copper, and may be formed by a plating process such as electroplating. For example, the conductive layer 106 may act as a seed layer in an electroplating (e.g., copper plating) process that forms the conductive layer 111. In some embodiments, before forming the conductive layer 111, forming a seed layer (not shown) on the sidewall surface of the opening 109 may be further included, and the seed layer may be formed by a plating process such as electroless plating.

For example, prior to forming the conductive layer 111, pre-treatment of the opening 109 and the surface of the conductive layer 106/108 to be plated may be further included, such as processes including deburring, cleaning processes (e.g., double water washing), microetching chemical roughening, colloidal palladium activation treatment, photoresist treatment, copper deposition, pickling, and baking, etc., wherein the copper deposition may be a formation of a seed layer on the sidewall surface of the opening 109 that is subsequently used for the electroplating process.

Referring to fig. 4F, an insulating material 110 'is filled in the opening 109 such that the insulating material 110' fills the space of the opening 109 not filled with the conductive layer 111. In some embodiments, the insulating material 110' may include a resin material; for example, the opening 109 may be plugged with resin by a resin plugging process and then pressed; thereafter, the resin material is subjected to a curing process, which may include, for example, converting the resin material from a two-dimensional linear structure into a three-dimensional insoluble infusible network structure under light, heat, or the like.

Referring to fig. 4F to 4G, a polishing process is performed to remove the excess insulating material (e.g., resin material) 110'. For example, a nonwoven plate grinder or a belt grinder may be used to remove excess resin material (e.g., resin material located outside the openings) from the plate surface, and portions of the resin material protruding from the conductive layer 111 may be removed. In some embodiments, the surface roughness of the conductive layer 111 is ensured during the polishing process, so as to avoid the occurrence of scratches, and the like. In some embodiments, after the polishing process is performed, opposing surfaces of the insulating material 110' in a vertical direction (e.g., a direction perpendicular to the main surface of the insulating layer 100) may be respectively flush with opposing surfaces of the conductive layer 111 in a vertical direction away from the plurality of insulating layers in a horizontal direction.

Referring to fig. 4G and 4H, in some embodiments, the conductive layer 111 may be thinned to adjust the thickness of the conductive layer. In examples where conductive layer 111 includes copper, the thinning process may also be referred to as a copper reduction process. For example, the thinning treatment may include acid washing, deionized water washing, alkali washing, and the like of the conductive layer. After the thinning process, the insulating material 110' may protrude from the surface of the conductive layer 111 in the vertical direction.

Referring to fig. 4H to 4I, portions of the insulating material 110' protruding from the conductive layer 111 are removed, and the remaining insulating material serves as an insulating body 110 for subsequently forming a via hole; for example, the insulating material 110' includes a resin material, and a portion protruding from the conductive layer 111 may also be referred to as flash, i.e., flash is removed in this step. For example, removing the flash may include performing microetching, washing, drying, expanding, removing the flash, neutralizing, drying, and the like, but the disclosure is not limited thereto.

Referring to fig. 4I to 4J, the conductive layers 111 and 106 are subjected to a patterning process to remove portions of the conductive layers 106 and 111 on the side of the insulating layer 105 remote from the insulating layer 100 and portions of the conductive layers 108 and 111 on the side of the insulating layer 107 remote from the insulating layer 100. As shown in fig. 4J, after the patterning process, the conductive layer 106 and the conductive layer 111 remaining on the side of the insulating layer 105 away from the insulating layer 100 constitute a conductive line M2a; the conductive layer 108 and the conductive layer 111 remaining on the side of the insulating layer 107 away from the insulating layer 100 constitute a conductive line M2b; and the insulating body 110 and the portion of the conductive layer 111 surrounding the insulating body 110 constitute a conductive via V0. In some embodiments, the conductive via V0 further includes a seed layer (not shown) between the conductive layer 111 and the insulating body 110. In this way, the conductive lines M1a, M1b, M2a, M2b located in different layers can be electrically connected through the conductive via V0.

Referring to fig. 4J to 4K, an insulating layer 115 and a conductive layer 121 are formed on a side of the insulating layer 115 away from the insulating layer 105, and an insulating layer 117 and a conductive layer 122 are formed on a side of the insulating layer 107 away from the insulating layer 100. The insulating layers 115 and 117 may include insulating materials such as resin, including prepreg, for example; the conductive layers 121 and 122 may include a conductive material, for example, a metal material including copper, for example, a copper foil layer. In some embodiments, the insulating layers 115, 117 and the conductive layers 121, 122 may be formed by lamination, but the disclosure is not limited thereto. In some embodiments, the insulating layers 100, 105, 107, 115, 117 comprise an insulating structure 120.

Referring to fig. 4K and 4L, in some embodiments, an opening process is performed on the structure shown in fig. 4K to form a plurality of openings in the structure. The opening process removes one or more of the plurality of conductive layers and one or more of the plurality of insulating layers to form openings in the respective layers. For example, the opening process may include forming one or more openings 80a and one or more openings 80b. The opening 80a extends through the conductive layer 121 and the insulating layer 115 to expose a portion of the surface of the conductive line M2 a; the opening 80b extends through at least portions of the conductive layer 121 and the insulating layer 115, but does not expose the conductive line M2a or other conductive member. The opening 80b is for subsequent formation of a dummy via therein, and may also be referred to as a dummy opening 80b. The depth of the opening 80b may be set according to actual product requirements. For example, in this example, opening 80b extends through the entire insulating layer 115 and exposes a surface of insulating layer 105; in other embodiments, opening 80b may extend into insulating layer 115, but not through insulating layer 115; or opening 80b may also continue to extend through one or more of the other insulating layers in insulating structure 120, or may extend through conductive layer 121, the entire insulating structure 120, and conductive layer 122. The present disclosure is not limited to the depth of opening 80b.

In some embodiments, the opening process further includes forming one or more openings 80c, the openings 80c extending through the conductive layer 121, the insulating structure 120, and the conductive layer 122, and may also extend through one or more of the conductive lines M1a, M1b, M2a, M2b such that sidewalls of the conductive lines are exposed in the openings 80 c. In some embodiments, the openings 80a, 80b, 80c may also be referred to as vias.

In this embodiment, most of the openings are formed on the side of the conductive layer 121, but the disclosure is not limited thereto. In other embodiments, one or more openings may also be formed from the side of conductive layer 122, for example, an opening (not shown) may be formed in the side that extends through conductive layer 122 and insulating layer 117 and exposes a portion of the surface of conductive line M2 b. It should be understood that the locations and numbers of openings shown in the drawings are illustrative only and the disclosure is not limited thereto. The positions and the number of the openings can be correspondingly set and adjusted according to the actual product requirements. In some embodiments, the above-described opening process may include one or more of an etching process, a laser drilling process, a mechanical drilling process.

Referring to fig. 4M, a conductive layer 123 is formed, the conductive layer 123 is filled in the plurality of openings 80a, 80b, 80c, and is formed on a surface of the conductive layer 121 on a side away from the insulating layer 115 and on a surface of the conductive layer 122 on a side away from the insulating layer 117. The conductive layer 123 may include a conductive material, for example, a metal material including copper, and may be formed through a plating process such as electroplating, wherein the conductive layer 121 may serve as a seed layer in the electroplating process. In some embodiments, forming the conductive layer 123 prior to electroplating further includes forming a metal seed layer (not shown) on sidewall surfaces of each opening.

Referring to fig. 4M and 4N, the conductive layer 123 and the conductive layer 121/122 are subjected to a patterning process to remove a portion of the conductive layer 123 located on a side of the insulating layer 115 away from the insulating layer 105 and a portion of the conductive layer 121 located between the portion of the conductive layer 123 and the insulating layer 115, and to remove a portion of the conductive layer 123 located on a side of the insulating layer 117 away from the insulating layer 107 and a portion of the conductive layer 122 located between the portion of the conductive layer 123 and the insulating layer 117.

Referring to fig. 4N, after the patterning process, the conductive layers located in the openings 80a, 80b, and 80c constitute conductive vias V1, dummy vias DV, and conductive vias V2, respectively; that is, the conductive via V1, the dummy via DV, and the conductive via V2 may each include a portion of the conductive layer 123 located in the corresponding opening, or may further include a seed layer located between the portion of the conductive layer 123 and an adjacent material layer (insulating layer, conductive line, etc.); the portions of the conductive layer 123 and the conductive layer 121 located on the side of the insulating layer 115 away from the insulating layer 105 and connected to the conductive via V1 or the conductive via V2 constitute a conductive pad P1. The portions of the conductive layer 123 and the conductive layer 121 located on the side of the insulating layer 115 away from the insulating layer 105 and connected to the dummy via DV constitute a dummy pad DP; the dummy pad DP and the dummy via DV together constitute a dummy pad structure 124. The portions of the conductive layer 123 and the conductive layer 122 on the side of the insulating layer 117 away from the insulating layer 107 and connected to the conductive via V2 constitute a conductive pad P3. In this embodiment, the dummy pads 123 and the dummy vias DV of the dummy pad structure 124 may be formed at the same time (i.e., in the same patterning process) as the conductive pads P1 and the conductive vias V1, V2, such that no additional process steps may be added due to the provision of the dummy reinforcing member (e.g., the dummy vias DV); therefore, the process can be simplified and the cost can be saved.

In each of the conductive pad P1 and the dummy pad DP, a portion of the conductive layer 123 covers a surface of the conductive layer 121 on a side away from the insulating layer 115, the conductive layer 121 is located between the portion of the conductive layer 123 and the insulating layer 115 in a vertical direction (e.g., direction D1), and surrounds a sidewall of another portion of the conductive layer 123 in a horizontal direction (e.g., direction D2); in the conductive pad P3, a portion of the conductive layer 123 covers a surface of the conductive layer 122 on a side away from the insulating layer 117, the conductive layer 122 is located between the portion of the conductive layer 123 and the insulating layer 117 in a vertical direction (e.g., the direction D1), and surrounds a sidewall of another portion of the conductive layer 123 in a horizontal direction (e.g., the direction D2).

As shown in fig. 4M to 4N, when forming the conductive layer 123, the conductive layer 123 may fill the openings 80a-80c, such that the formed conductive vias V1, V2 and the dummy via DV each include the entire metal pillar, but the disclosure is not limited thereto. In other embodiments, the conductive vias V1, V2 and dummy via DV may also be formed using a similar process as the conductive via V0, such that each of the vias includes an insulating body and a conductive liner surrounding the insulating body.

Referring to fig. 4O, a protective layer 125 is formed on a side of the insulating layer 115 away from the insulating layer 105, and a protective layer 127 is formed on a side of the insulating layer 117 away from the insulating layer 107, and the protective layers 125 and 127 may be or include solder resists. The protective layers 125 and 127 may be formed by a printing process such as screen printing, for example. In some embodiments, the protection layer 125 has a plurality of openings to expose the conductive pad P1 and the dummy pad DP, and the protection layer 125 may be spaced apart from the conductive pad P1 and the dummy pad DP, thereby facilitating the bonding of the conductive pad and the dummy pad with the connection member of the semiconductor structure in a subsequent process. In some embodiments, the protection layer 127 may also have one or more openings to expose the conductive pad P3, and the conductive pad P3 may be used for further connection with other electronic devices and/or may be used as an electrical test point, but the disclosure is not limited thereto. In other embodiments, the protection layer 127 may also completely cover the conductive pad P3. The opening positions of the protection layers 125 and 127 may be set according to actual product requirements. In some embodiments, a wiring substrate 150 is formed so far.

Referring to fig. 4O to 4P, a semiconductor structure S1 is provided; a bonding process is performed to bond the semiconductor structure S1 to the wiring substrate 150. For example, the semiconductor structure S1 may include the package substrate 200, the chip 300, the conductive connection 212, and the dummy connection 213. Bonding the semiconductor structure S1 to the wiring substrate 150 may include bonding the conductive connection 212 and the dummy connection 213 of the semiconductor structure S1 to the conductive pad P1 and the dummy pad DP of the wiring substrate 150, respectively. In some embodiments, during the bonding process, the bonding window may be enlarged to facilitate bonding of the connector to the adjacent pad, since the opening size of the protective layer 125 is larger than the size of the corresponding pad; after the bonding process, the conductive connection 212 and the dummy connection 213 may cover the surfaces of the corresponding conductive pad P1 and the dummy pad DP, respectively, on the side close to the semiconductor structure S1, and may also cover the sidewalls of the corresponding pad, so that the bonding strength between the connection and the corresponding pad may be improved. For example, the bonding process may include a welding process. The relevant features of the semiconductor structure S1 may be referred to the above description about fig. 2A and 2B, and will not be repeated here.

In some embodiments, after the semiconductor structure S1 is bonded to the circuit substrate 150, the heat dissipation device 400 may be mounted on the semiconductor structure S1 to facilitate heat dissipation of the chip 300 and form the package structure 500a. For example, the heat sink 400 may be mounted on the package substrate 200 and attached to a surface of the chip 300 on a side remote from the package substrate 200. In other embodiments, the heat sink 400 may also be mounted on the circuit substrate 200 and attached to the surface of the chip 300. In some embodiments, during the process of mounting the heat sink 400, the conductive connection 212 and the dummy connection 213 may be subjected to stress from upper components (e.g., the package substrate 200, the chip 300, the heat sink 400), while the dummy pad structure located near the corner is subjected to relatively greater stress. In the embodiment of the disclosure, since the dummy pad structure 124 includes the dummy pad and further includes the dummy reinforcing member embedded in the insulating structure, the contact area between the dummy pad structure 124 and the insulating structure can be increased, and the dummy reinforcing member is buried in the insulating structure, so that the dummy pad structure 124 has higher structural strength, and defects such as cracks generated between other material layers when the dummy pad structure is subjected to larger stress can be avoided, thereby improving the overall structural stability of the package structure and further improving the reliability of the device.

In some embodiments, after forming the package structure, a reliability test, such as a temperature cycle test, may be performed on the package structure; since the dummy pad structure 124 of the present disclosure has a high structural strength by providing the dummy reinforcing member, cracks between the dummy pad structure and an adjacent insulating structure in a reliability test can be avoided.

Fig. 4A to 4P illustrate a method for manufacturing the package structure according to the embodiment of the present disclosure, taking the package structure 500a as an example. It should be appreciated that the method of forming the package structure 500b is similar to the package structure 500a, except that in the patterning process of fig. 4J to form the conductive line M2a, the dummy line RC is also formed; that is, the dummy line RC may be formed simultaneously with the conductive line M2a in the same patterning process, and may include portions of the conductive layer 106 and the conductive layer 111; subsequently, when the opening 80b is formed, the opening 80b extends through the conductive layer 121 and the insulating layer 115 to expose a portion of the surface of the dummy line RC, so that a dummy via hole subsequently formed in the opening 80b is connected to the dummy line RC. However, the disclosure is not limited thereto. In other embodiments, the dummy line in the dummy pad structure may also be formed simultaneously with any one or more of the conductive lines M1a, M1b, M2b, and the dummy via is correspondingly connected to the dummy line.

Fig. 5 and 6 illustrate methods of manufacturing a package structure according to further embodiments of the present disclosure.

Referring to fig. 5, in some embodiments, in the package structure 500c, the dummy pad structure 204 of the semiconductor structure S1 may include a dummy pad 204 and a dummy reinforcement member (or may be referred to as a second dummy reinforcement member), and the dummy reinforcement member may include at least the dummy via 92, or may further include the dummy line 94. The dummy pad 202 is connected to the dummy reinforcing member to further improve the bonding strength between the dummy pad structure 204 and adjacent material layers (e.g., dielectric structure 90) in the package substrate 200 and to avoid cracking of the dummy pad 202 between the adjacent material layers when subjected to a large stress. That is, by providing the dummy reinforcing member including at least the dummy via 92 also in the semiconductor structure S1 (e.g., the package substrate 200 thereof), the bonding strength between the dummy connectors 213 and the dummy pad structures 204 connected thereto and the package substrate 200 of the semiconductor structure S1 can be further enhanced, thereby improving the device reliability.

For example, the package substrate 200 may further include a dielectric structure 90, a conductive via 91 embedded in the dielectric structure 90, a dummy via 92, and a conductive line 93; the conductive pads 201 may be disposed on a surface of the dielectric structure 90 near the circuit substrate 150 and electrically connected to the conductive wires 93 through the conductive vias 91. The dummy pads 202 may be disposed on a surface of the dielectric structure 90 near the circuit substrate 150, and the dummy reinforcing member may be embedded in the dielectric structure 90 and connected to the dummy pads 202. For example, the dummy via 92 is connected to the dummy pad 202 as at least part of the dummy reinforcing member. The dummy via 92 and the dummy pad 202 may be integrally formed and may be formed simultaneously with the conductive via 91 and the conductive pad 201, for example, by the same patterning process. In some embodiments, the dummy reinforcement member in the semiconductor structure S1 may further include a dummy line 94 embedded in the dielectric structure 90, and the dummy line 94 may be located at a side of the dummy via 92 remote from the dummy pad 202 and connected with the dummy via 92. The dummy via 92 and the dummy line 94 may each include a metal material such as copper, but the disclosure is not limited thereto. It should be understood that the dummy lines 94 may also be omitted, i.e., the dummy reinforcing member may include only dummy vias and not dummy lines. The dummy line 94 may be disposed on the same layer as the conductive line 93, but the disclosure is not limited thereto. The pads and vias and/or lines directly connected to the pads on the side of the package structure 200 near the circuit substrate are shown in fig. 5, while other conductive traces and pads may be further included on the side of the conductive line 93 near the chip 300, and are not specifically shown for the sake of brevity.

In the above embodiment, in the dummy pad structure 124, the dummy reinforcing members are all located on the side of the dummy pad DP away from the semiconductor structure S1 and embedded in the insulating structure 120, but the disclosure is not limited thereto. In other embodiments, the dummy reinforcement member may further include an additional portion on a side of the insulating structure 120 adjacent to the semiconductor structure. For example, the additional portion may cover a portion of the surface of the dummy pad DP near the side of the semiconductor structure S1 and a portion of the sidewall thereof.

For example, referring to fig. 6, in the package structure 500D, the protection layer 125 has an opening in which at least a portion of the dummy pad structure 124 is located, the dummy pad structure 124 has a first sidewall and a second sidewall (e.g., opposite to each other in the direction D2), the protection layer 125 covers a first portion of a surface of the dummy pad structure 124 remote from the insulating structure 120 and the first sidewall, and the dummy connection 213 covers a second portion of the surface of the dummy pad structure 124 and the second sidewall.

For example, the protection layer 125 may extend to cover a portion of the surface of the dummy pad DP near the semiconductor structure S1 and a portion of the sidewall thereof. For example, the dummy pad DP has opposite sidewalls in a horizontal direction, the protection layer 125 may cover one of the opposite sidewalls of the dummy pad DP, and the other sidewall of the dummy pad DP is located in the opening of the protection layer 125 to be laterally spaced apart from the protection layer 125; the dummy connection 213 extends into the opening of the protection layer 125 and may cover the other sidewall of the dummy pad DP. In this example, the portion of the protection layer 125 covering the dummy pad DP may serve as an additional portion of the dummy reinforcing member, further improving the structural strength of the dummy pad structure 214, so that in the case where the dummy connectors 213 and the dummy pad structure 124 are subjected to a larger stress (e.g., tensile stress or shear stress), cracks between the dummy pad DP and the insulating structure 120 are better avoided, i.e., the bonding strength between the dummy connectors 213 and the dummy pad structure 124 connected thereto and the circuit substrate 150 is further improved, thereby improving the device reliability. On the other hand, the protection layer 125 covers only a portion of the sidewalls of the dummy pad DP, and another portion of the sidewalls of the dummy pad DP is covered by the dummy connection member 213, thereby ensuring sufficient bonding strength between the dummy connection member 213 and the dummy pad DP.

In some embodiments, the bond strength between the connection element and/or the connection pad and the circuit substrate in the package structure may be tested by a ball-in-ball (ball-in) test, for example, the bond strength between the connection pad connected to the connection element and the insulating structure may be tested. For example, the bonding strength between the dummy connectors 13 and the dummy pads 9b and the wiring substrate 10 (e.g., the insulating structure 6) in the package structure 50 shown in fig. 1A was tested by a ball pushing experiment; and the bonding strength between the dummy connectors 213 and the dummy pad structures 124 and the circuit substrate 150 (e.g., the insulating structure 120) in the package structure 500a shown in fig. 2A was tested. In some examples, the results of performing the above-described tests on package structures 50 and 500a show that: the shear strength of the dummy connectors 213 and the dummy pad structures 124 in the package structure 500a may be increased by 56% compared to the shear strength of the dummy connectors 13 and the dummy pads 9b in the package structure 50; that is, if the shear strength of the dummy connectors 13 and the dummy pads 9b in the package structure 50 is 100%, the shear strength of the dummy connectors 213 and the dummy pad structures 124 in the package structure 500 may reach 156%. That is, in the embodiments of the present disclosure, by including the dummy pad structure and the dummy reinforcing member, the structural strength of the dummy pad structure and the dummy connectors bonded thereto and the bonding strength with the circuit substrate can be greatly improved, thereby improving the device reliability.

The following points need to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A packaging structure comprises a circuit substrate and a semiconductor structure arranged on the circuit substrate, wherein

The circuit substrate includes:

an insulating structure;

a conductive line embedded in the insulating structure;

the first conductive connecting pad is arranged on one side of the insulating structure and is electrically connected to the conductive circuit; and

a first dummy pad structure disposed on the one side of the insulating structure and extending into the insulating structure,

the semiconductor structure is bonded to the first conductive pad and the first dummy pad structure of the wiring substrate by conductive connectors and dummy connectors.

2. The package structure of claim 1, wherein the first dummy pad structure and the dummy connection feature are electrically floating and electrically isolated from the conductive trace.

3. The package structure according to claim 1, wherein the conductive connection member and the dummy connection member are arranged side by side in a horizontal direction parallel to a main surface of the wiring substrate, and the dummy connection member is closer to a corner of the semiconductor structure than the conductive connection member.

4. The package structure of claim 1, wherein the first dummy pad structure comprises:

the first dummy connection pad is arranged on the surface of one side, close to the semiconductor structure, of the insulating structure; and

the first dummy reinforcing member is embedded in the insulating structure, surrounded by the insulating structure and connected with the first dummy bonding pad.

5. The package structure of claim 4, wherein at least a portion of the first dummy bond pad is integrally formed with at least a portion of the first dummy reinforcement member.

6. The package structure of claim 4, wherein the first dummy reinforcement member includes a dummy via connected with the first dummy pad and extending from the first dummy pad into the insulating structure in a direction perpendicular to the main surface of the circuit substrate and away from the conductive connection.

7. The package structure of claim 6, wherein the first dummy reinforcement member further comprises:

and a dummy line embedded in the insulating structure, and the dummy via is located between the first dummy pad and the dummy line in a first direction perpendicular to the main surface of the circuit substrate.

8. The package structure of claim 7, wherein a width of the dummy line is greater than a width of the dummy via, and the width of the dummy line and the width of the dummy via are widths in a second direction parallel to the main surface of the circuit substrate.

9. The package structure of claim 7, wherein the conductive line comprises a first conductive line and a second conductive line embedded in different insulating layers of the insulating structure, the first conductive line and the second conductive line being electrically connected to each other by a conductive via;

the dummy line is arranged on the same layer as the first conductive line, and the overlapping area of the dummy line and the second conductive line in the first direction is smaller than the overlapping area of the first conductive line and the second conductive line in the first direction.

10. The package structure of any of claims 1-9, wherein the wiring substrate further comprises:

A first protective layer is located on a side of the insulating structure adjacent to the semiconductor structure and on sides of the conductive pad and the first dummy pad structure in a direction parallel to a major surface of the circuit substrate, spaced apart from the conductive pad, and spaced apart from at least a portion of a sidewall of the first dummy pad structure.

11. The package structure of claim 10, wherein the first protective layer has an opening in which at least a portion of the first dummy pad structure is located, the dummy connector covering a surface of the first dummy pad structure remote from the insulating structure and extending into the opening to cover a sidewall of the at least a portion of the first dummy pad structure.

12. The package structure of claim 10, wherein the first protective layer has an opening in which at least a portion of the first dummy pad structure is located, the first dummy pad structure having a first sidewall and a second sidewall, the first protective layer covering a first portion of a surface of the first dummy pad structure remote from the insulating structure and the first sidewall, the dummy connection covering a second portion of the surface of the first dummy pad structure and the second sidewall.

13. The package structure of any of claims 1-9, wherein the semiconductor structure further comprises:

the second dummy pad structure at least comprises a second dummy pad, the second conductive pad and the second dummy pad are positioned on one side of the semiconductor structure, which is close to the circuit substrate, the second conductive pad is electrically connected with the conductive connecting piece, and the second dummy pad structure is connected with the dummy connecting piece and is electrically floating.

14. The package structure of claim 13, wherein the semiconductor structure further comprises:

the second protection layer is positioned on one side of the semiconductor structure close to the circuit substrate and covers the side walls of the second conductive pads and the second dummy pads and part of the surfaces of the side walls of the second conductive pads and the second dummy pads close to the circuit substrate.

15. The package structure of claim 13, wherein the semiconductor structure further comprises a dielectric structure, the second dummy pad structure further comprises a second dummy reinforcement member, the second dummy pad is located on a surface of the dielectric structure on a side of the circuit substrate, the second dummy reinforcement member is embedded in the dielectric structure and connected to the second dummy pad.

16. The package structure of claims 1-9, further comprising:

the heat dissipation component is arranged on one side of the semiconductor structure far away from the circuit substrate and is attached to the semiconductor structure.

17. The package structure of claims 1-9, wherein the semiconductor structure comprises:

and (3) a chip: and

and the packaging substrate is electrically connected to the chip and is positioned between the chip and the circuit substrate, and the conductive connecting piece and the dummy connecting piece are arranged on one side of the packaging substrate far away from the chip.

18. A method of manufacturing a package structure, comprising:

forming a circuit substrate, comprising: forming an insulating structure and a conductive line, wherein the conductive line is embedded in the insulating structure; forming a first conductive pad on one side of the insulating structure, the first conductive pad being electrically connected to the conductive trace through a conductive via; and forming a first dummy pad structure disposed on the one side of the insulating structure and extending into the insulating structure; and

providing a semiconductor structure and bonding the semiconductor structure to the circuit substrate, wherein the semiconductor structure has a conductive connection and a dummy connection, and bonding the semiconductor structure to the circuit substrate includes bonding the conductive connection and the dummy connection to the first conductive pad and the first dummy pad structure, respectively, of the circuit substrate.

19. The method of manufacturing a package structure of claim 18, wherein forming the first dummy pad structure comprises:

forming a first dummy reinforcement member in the insulating structure; and

a first dummy bonding pad is formed on one side of the first dummy reinforcement member and the insulating structure near the semiconductor structure, and the first dummy bonding pad and the first dummy reinforcement member are connected to each other.

20. The method of manufacturing a package structure of claim 19, wherein the first dummy reinforcement member comprises a dummy via, and forming the first dummy pad structure comprises:

forming an opening in the insulating structure; and

a metal material is formed in the opening of the insulating structure and on a surface thereof on a side of the insulating structure adjacent to the semiconductor structure, wherein a portion of the metal material located in the opening forms the dummy via and a portion of the metal material located on the surface of the insulating structure forms the first dummy pad.

21. The method of manufacturing a package structure of claim 20, wherein forming the first dummy pad structure further comprises:

before the opening is formed, a dummy line embedded in the insulating structure is formed, and the opening is formed to expose the dummy line so that the dummy via hole subsequently formed in the opening is connected with the dummy line, wherein the dummy line and the dummy via hole together constitute the first dummy reinforcing member.

22. The method of manufacturing a package structure according to any one of claims 19-21, wherein at least a portion of the first dummy reinforcement member comprises the same material as the conductive via and is formed by the same patterning process.