CN116721846A - On-chip power transformer based on IC carrier plate - Google Patents
On-chip power transformer based on IC carrier plate Download PDFInfo
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- CN116721846A CN116721846A CN202310631742.3A CN202310631742A CN116721846A CN 116721846 A CN116721846 A CN 116721846A CN 202310631742 A CN202310631742 A CN 202310631742A CN 116721846 A CN116721846 A CN 116721846A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 189
- 238000002955 isolation Methods 0.000 claims abstract description 32
- 238000004804 winding Methods 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004698 Polyethylene Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229920013716 polyethylene resin Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 27
- 230000008569 process Effects 0.000 abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
- H01F2027/348—Preventing eddy currents
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
The application belongs to the field of isolator chips, in particular relates to an on-chip power transformer based on an IC carrier plate, and aims to solve the problem of longitudinal dimension limitation of lines during preparation of the on-chip transformer based on a silicon process, the problem of eddy current effect in the on-chip transformer based on the silicon process and the problem of large current output limitation of an existing on-chip DC-DC isolation power supply. The application comprises the following steps: at least one pair of transformer coils and at least one isolation medium; the transformer coil comprises a primary coil and a secondary coil, and the primary coil and the secondary coil are mutually overlapped; the isolation medium is disposed between the primary coil and the secondary coil. The application improves the output current capability of the on-chip transformer. Meanwhile, lines of the primary coil and the secondary coil, which correspond to the first metal turns and the second metal turns, are staggered, so that parasitic capacitance of the on-chip transformer can be reduced, and quality factor is improved.
Description
Technical Field
The application belongs to the technical field of isolator chips, and particularly relates to an on-chip power transformer based on an IC carrier plate.
Background
The on-chip power transformer with high transmission efficiency, high isolation voltage resistance and large output current is a core module of the integrated DC-DC isolation power supply, and determines key indexes such as the output current, the energy conversion efficiency, the isolation voltage resistance degree and the like.
Typically, on-chip transformers are fabricated using mainly a CMOS process based on a silicon substrate and SiO2 insulating medium to form stacked winding metal coils. When the transformer coil is manufactured by adopting a silicon process, since the silicon material has relatively small resistivity, eddy current loss is formed inside the transformer, the transformer efficiency is inhibited, and the effect is more remarkable particularly in a high-efficiency high-current power transformer. Meanwhile, the metal coil prepared by the silicon process has the problem of line width limitation of the silicon process, and a large-sectional area metal winding coil is difficult to prepare, so that the internal resistance of the metal coil is high, the coil loss is increased, and the coil quality factor is reduced. The formation of large output current on-chip power transformers used in DC-DC isolated power supplies is disadvantageous. Based on the above, the application provides an on-chip power transformer based on an IC carrier plate.
Disclosure of Invention
In order to solve the problems in the prior art, namely, in the application of products such as a magnetic coupling isolation power supply, a digital isolator and the like, the problem of line width limitation of a silicon-based process exists in a metal coil prepared by a silicon process, and a large-sectional-area metal winding coil is difficult to prepare, so that the internal resistance of the metal coil is large, the coil loss is increased, and the coil quality factor is reduced. The application provides an on-chip power transformer based on an IC carrier plate, which is disadvantageous to the problem of forming a large output current on-chip power transformer used in a DC-DC isolated power supply.
In another aspect of the present application, an on-chip power transformer based on an IC carrier is provided, comprising
At least one pair of transformer coils and at least one isolation medium;
the transformer coil comprises a primary coil and a secondary coil, and the primary coil and the secondary coil are mutually overlapped;
the isolation medium is located between the primary coil and the secondary coil, and the isolation medium is capable of galvanically isolating the primary coil from the secondary coil.
In some preferred embodiments, the primary coil is composed of a first metal coil, the first metal coil is circumferentially located in a first metal layer, the first metal coil is in a spiral structure which is arranged in a diffusion manner from inside to outside, and the first metal layer is an electroplated copper layer of the IC carrier plate;
the secondary coil consists of a second metal coil, the second metal coil is circumferentially arranged in a second metal layer, the second metal coil is of a spiral structure which is arranged in a diffusion manner from inside to outside, the second metal layer and the first metal layer are mutually staggered and are arranged in parallel, and the second metal layer is an electroplated copper layer of the IC carrier plate;
the primary coil is connected with the output end of the primary driving circuit, and the secondary coil is connected with the input end of the secondary rectifying circuit;
the on-chip power transformer, the primary coil and the secondary coil are packaged in the same circuit in a multi-chip packaging mode.
In some preferred embodiments, the first metal turn is located above or below the second metal turn.
In some preferred embodiments, the first metal layer where the primary coil is located is etched to form a spiral first winding coil, and the second metal layer where the secondary coil is located is etched to form a spiral second winding coil.
In some preferred embodiments, when the primary coil is located above the secondary coil, the primary coil is an upper coil, the secondary coil is a lower coil, and an upward through hole is located at the outermost end point of the upper coil and is used as an outer connection point of the primary coil; an upward through hole is formed at the inner side end point of the upper layer coil and is used as an inner side connecting point of the primary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the secondary coil; a downward through hole is formed at the innermost end point of the lower coil and is used as an inner connecting point of the secondary coil;
when the secondary coil is positioned above the primary coil, the secondary coil is an upper coil, the primary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connecting point of the secondary coil; an upward through hole is formed at the innermost end point of the upper coil and is used as an inner connecting point of the secondary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the primary coil; a downward through hole is arranged at the innermost end point of the lower coil and is used as an inner connecting point of the primary coil.
In some preferred embodiments, when the primary coil is located above the secondary coil, the connection point on the outer side of the primary coil and the connection point on the inner side of the primary coil are both connected to a top metal through a through hole upwards, and are connected to a PAD outside the coil through a metal lead, where the top metal is the uppermost metal in the IC carrier.
In some preferred embodiments, when the primary coil is located below the secondary coil, the primary coil outer connection point and the primary coil inner connection point are both connected to the lower metal layer of the second metal layer downward through a via hole and connected to the PAD outside the coil through a metal lead.
In some preferred embodiments, when the secondary coil is located above the primary coil, the connection point on the outer side of the secondary coil and the connection point on the inner side of the secondary coil are both connected to a top metal through a through hole upwards and connected to a PAD outside the coil through a metal lead, and the top metal is the uppermost metal in the IC carrier.
In some preferred embodiments, when the secondary coil is located below the primary coil, the secondary coil outer connection point and the secondary coil inner connection point are both connected to the lower metal layer of the second metal layer downward through a through hole, and are connected to the outside of the coil through a metal wire, and are connected to the PAD outside the coil through a metal lead.
In some preferred embodiments, the number of turns of the first winding coil is the same as or different from the number of turns of the second winding coil.
In some preferred embodiments, the isolation medium is an inter-metal medium in the IC carrier, and the material of the isolation medium is any one of polyimide, polyethylene and epoxy resin mixed material.
The application has the beneficial effects that:
(1) The IC carrier plate technology is adopted, and double-layer metal is utilized to manufacture primary side coils and secondary side coils on respective planes. In the longitudinal direction, the primary side and the secondary side are stacked, the primary side and the secondary side form pressure resistance by using an isolating medium, and the pressure resistance of the coil is in direct proportion to the distance between the coils, namely the thickness of the isolating medium.
(2) And in the transverse direction, the primary side coils and the secondary side coils are wound in a staggered manner, so that the superposition of the upper coil and the lower coil is avoided, the parasitic capacitance is reduced, and the transmission efficiency is improved. The transformer coil prepared by the IC carrier plate process can solve the problem that the coil width is limited by the process when the coil is prepared by the silicon process. Meanwhile, compared with an on-chip transformer based on a silicon process, the on-chip transformer based on the IC carrier plate can reduce the eddy current effect, so that the Q value and the coupling coefficient are improved.
(3) The transformer based on the IC carrier plate process is adopted, and the isolation medium is made of high polymer polyester material, so that the eddy current effect in the silicon substrate is avoided, the eddy current loss is reduced, and the efficiency is improved obviously. The on-chip transformer metal coil is prepared by adopting an IC carrier plate mode, so that the problem of line process limitation when the metal coil is prepared by a silicon process is avoided, the coil width is increased, the coil sectional area is increased, the internal resistance of the metal coil can be reduced, and the quality factor of the inductance coil is improved. In the on-chip power transformer prepared by adopting the IC carrier plate, the secondary side coils and the primary side coils are mutually staggered, the overlapping area is small, and the series capacitance is reduced. Meanwhile, polyimide material with high dielectric strength is used as an isolation medium, so that high compressive strength is realized, the coil coupling distance is reduced, a high coupling coefficient is formed, the efficiency of the transformer is improved, and the energy conversion capability of a DC-DC isolation power supply is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a general block diagram of a DC-DC isolated power supply for a single transformer pair;
FIG. 2 is a general block diagram of a DC-DC isolated power supply of a dual transformer pair;
FIG. 3 is a power combining circuit layout based on an on-chip transformer in accordance with a first embodiment of the present application;
FIG. 4 is a first exploded view of FIG. 3;
FIG. 5 is a second exploded view of FIG. 4;
FIG. 6 is a perspective view of the layout corresponding to FIG. 3;
FIG. 7 is a first exploded view of FIG. 6;
FIG. 8 is a first exploded view of FIG. 7;
FIG. 9 is a power combining circuit layout based on an on-chip transformer in a second embodiment of the present application;
FIG. 10 is a first exploded view of FIG. 9;
FIG. 11 is a second exploded view of FIG. 9;
FIG. 12 is a perspective view of the layout corresponding to FIG. 9;
FIG. 13 is a first exploded view of FIG. 12;
fig. 14 is a second exploded view of fig. 12.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Example 1
Referring to fig. 1 to 8, referring to fig. 1 and 3, the present application provides an on-chip power transformer based on an IC carrier, including:
at least one pair of transformer coils and at least one isolation medium;
the transformer coil comprises a primary coil and a secondary coil, and the primary coil and the secondary coil are mutually overlapped;
the isolation medium is located between the primary coil and the secondary coil, and the isolation medium is capable of galvanically isolating the primary coil from the secondary coil.
The power input signals are amplified by the power amplifier and then connected to the input end of the primary coil, the power amplified current signals are converted by the primary coil and the secondary coil to form alternating current signals at the secondary coil, and the alternating current signals are converted into direct current and output after passing through the secondary rectifying circuit.
Wherein, a power input signal is input to the primary coil, and an output current is formed in the secondary coil through electromagnetic conversion.
The specific shape of the primary coil and the secondary coil can be hexagonal or octagonal, or other shapes suitable for manufacturing coils.
Preferably, referring to fig. 1, 3-8, a pair of transformer coil pairs is used as DC-DC isolated mains power conversion devices:
the primary coil consists of a first metal coil, the first metal coil is circumferentially arranged in a first metal layer, the first metal coil is of a spiral structure which is arranged in a diffusion manner from inside to outside, and the first metal layer is an electroplated copper layer of the IC carrier plate;
the secondary coil consists of a second metal coil, the second metal coil is arranged in a second metal layer in a surrounding mode, the second metal coil is of a spiral structure which is arranged in a diffusing mode from inside to outside, the second metal layer and the first metal layer are staggered and arranged in parallel, and the second metal layer is an electroplated copper layer of the IC carrier plate;
the primary coil is connected with the output end of the primary driving circuit, the secondary coil is connected with the input end of the secondary rectifying circuit, and the on-chip power transformer, the primary coil and the secondary coil are packaged in the same circuit in a multi-chip packaging mode.
Wherein the first metal turns and the second metal turns do not overlap each other.
The first metal coil of the innermost layer of the primary coil is positioned between the second metal coil of the innermost layer of the secondary coil and the second metal coil of the secondary outer layer, and the following first metal coil and second metal coil are analogized in sequence. The primary coil and the secondary coil can be opposite in inner and outer sequence, the second metal layer and the first metal layer are staggered and arranged in parallel, the purpose of the arrangement is to reduce the overlapping part, parasitic capacitance can be reduced due to the reduction of the overlapping part, and transmission efficiency is improved.
The primary side driving circuit adopts a power amplifier to drive a transformer, and the secondary side rectifying circuit adopts a rectifying circuit to convert alternating current output by the transformer into direct current output.
Preferably, referring to fig. 6-8, the first metal turn is located above the second metal turn.
Another variant of the application is: the first metal turn is located below the second metal turn.
The purpose of the foregoing disclosure that the first metal layer and the second metal layer are not located on the same layer is that: and forming isolation withstand voltage by using different planes of the metal layer.
Wherein "higher" in the "level of the first metal layer is higher than" level of the second metal layer "is longitudinally higher, and may be understood as being spatially higher.
Wherein "lower" in the "level of the first metal layer is lower than" level of the second metal layer "is lower in the longitudinal direction, and may be understood as being lower in the spatial direction.
Preferably, the first metal layer where the primary coil is located is etched to form a spiral first winding coil, and the second metal layer where the secondary coil is located is etched to form a spiral second winding coil.
Preferably, referring to fig. 3 to 8, when the primary coil is located above the secondary coil, the primary coil is an upper coil, the secondary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connection point of the primary coil; an upward through hole is formed at the inner side end point of the upper layer coil and is used as an inner side connecting point of the primary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the secondary coil; a downward through hole is formed at the innermost end point of the lower coil and is used as an inner connecting point of the secondary coil;
when the secondary coil is positioned above the primary coil, the secondary coil is an upper coil, the primary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connecting point of the secondary coil; an upward through hole is formed at the innermost end point of the upper coil and is used as an inner connecting point of the secondary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the primary coil; a downward through hole is arranged at the innermost end point of the lower coil and is used as an inner connecting point of the primary coil.
Wherein, all the connection points are manufactured by using a through hole process in an IC carrier plate process, and the connection points form a layer jump effect between an upper metal layer and a lower metal layer by using the through hole process in the IC carrier plate process.
Preferably, when the primary coil is located above the secondary coil, the connection point at the outer side of the primary coil and the connection point at the inner side of the primary coil are both connected with a top metal upwards through a through hole and connected to a PAD outside the coil through a metal lead, and the top metal is the uppermost metal in the IC carrier plate;
when the primary coil is positioned below the secondary coil, the connection point at the outer side of the primary coil and the connection point at the inner side of the primary coil are downwards connected with the lower metal layer of the second metal layer through holes and are connected to the PAD outside the coil through metal leads, and the lower metal layer is any metal layer lower than the lower metal layer.
When the secondary coil is located above the primary coil, the connection point at the outer side of the secondary coil and the connection point at the inner side of the secondary coil are both connected with the top metal upwards through the through holes and connected to the PAD outside the coil through the metal lead, and the top metal is the uppermost metal in the IC carrier plate.
When the secondary coil is positioned below the primary coil, the outer side connecting point of the secondary coil and the inner side connecting point of the secondary coil are downwards connected with the lower metal layer of the second metal layer through holes, are connected to the outside of the coil through metal connecting wires and are connected to the PAD outside the coil through metal lead wires, and the lower metal layer is any metal layer lower than the lower metal layer.
Preferably, the number of turns of the first winding coil is the same as the number of turns of the second winding coil.
In another modification of the present application, the number of turns of the first winding coil is different from the number of turns of the second winding coil.
The number of turns and the turn ratio of the first winding coil and the second winding coil can be adjusted according to circuit requirements.
The primary coil and the secondary coil are positioned at the same position, but are not required to be completely overlapped.
Preferably, the isolation medium is an inter-metal medium in the IC carrier, and the material of the isolation medium includes but is not limited to polyimide, polyethylene and other epoxy resin mixed materials.
Another variant of the application may be: referring to fig. 2, an on-chip power transformer bank may also be formed by combining two pairs of transformer coil pairs as a DC-DC isolated power source power conversion module:
the transformer coil pair consists of a transformer coil pair 1 and a transformer coil pair 2, wherein the transformer coil pair 1 comprises a primary coil 11 and a secondary coil 12, and the transformer coil pair 2 comprises a primary coil 21 and a secondary coil 22.
The primary coil 11 and the primary coil 21 are respectively connected with the output end of a primary driving circuit, the primary driving circuit adopts a power amplifier to drive a transformer, the secondary coil 12 and the secondary coil 22 are respectively connected with the input end of a secondary rectifying circuit, and the secondary rectifying circuit converts alternating current output by the transformer into output direct current and outputs the output direct current to a rear-stage load.
Example two
As shown in fig. 1, 2 and 9-14, referring to fig. 1 and 9-14, the present application provides an on-chip power transformer based on an IC carrier, including:
at least one pair of transformer coils and at least one isolation medium;
the transformer coil comprises a primary coil and a secondary coil, and the primary coil and the secondary coil are mutually overlapped;
the isolation medium is located between the primary coil and the secondary coil, and the isolation medium is capable of galvanically isolating the primary coil from the secondary coil.
The power input signals are amplified by the power amplifier and then connected to the input end of the primary coil, the power amplified current signals are converted by the primary coil and the secondary coil to form alternating current signals at the secondary coil, and the alternating current signals are converted into direct current and output after passing through the secondary rectifying circuit.
Wherein, a power input signal is input to the primary coil, and an output current is formed in the secondary coil through electromagnetic conversion.
The specific shape of the primary coil and the secondary coil can be hexagonal or octagonal, or other shapes suitable for manufacturing coils.
Preferably, referring to fig. 9-14, a pair of transformer coil pairs are used as DC-DC isolated power source power conversion devices:
the primary coil consists of a first metal coil, the first metal coil is circumferentially arranged in a first metal layer, the first metal coil is of a spiral structure which is arranged in a diffusion manner from inside to outside, and the first metal layer is an electroplated copper layer of the IC carrier plate;
the secondary coil consists of a second metal coil, the second metal coil is arranged in a second metal layer in a surrounding mode, the second metal coil is of a spiral structure which is arranged in a diffusing mode from inside to outside, the second metal layer and the first metal layer are staggered and arranged in parallel, and the second metal layer is an electroplated copper layer of the IC carrier plate;
the primary coil is connected with the output end of the primary driving circuit, the secondary coil is connected with the input end of the secondary rectifying circuit, and the on-chip power transformer, the primary coil and the secondary coil are packaged in the same circuit in a multi-chip packaging mode.
Wherein the first metal turns and the second metal turns do not overlap each other.
Referring to fig. 9 and 12, the first metal coil of the innermost layer of the primary coil is located at the second metal coil of the innermost layer of the secondary coil, and is intersected with each other to form a certain angle, and then the first metal coil and the second metal coil are analogized sequentially to form a certain angle. Thereby reducing the area between the primary coil and the secondary coil and reducing parasitic capacitance. And the transmission efficiency is improved, and the on-chip transformer with crossed coils is formed.
The primary side driving circuit adopts a power amplifier to drive a transformer, and the secondary side rectifying circuit adopts a rectifying circuit to convert alternating current output by the transformer into direct current output.
Preferably, referring to fig. 12, the first metal turn is located above the second metal turn.
Another variant of the application is: the first metal turn is located below the second metal turn.
The purpose of the foregoing disclosure that the first metal layer and the second metal layer are not located on the same layer is that: and forming isolation withstand voltage by using different planes of the metal layer.
Wherein "higher" in the "level of the first metal layer is higher than" level of the second metal layer "is longitudinally higher, and may be understood as being spatially higher.
Wherein "lower" in the "level of the first metal layer is lower than" level of the second metal layer "is lower in the longitudinal direction, and may be understood as being lower in the spatial direction.
Preferably, the first metal layer where the primary coil is located is etched to form a spiral first winding coil, and the second metal layer where the secondary coil is located is etched to form a spiral second winding coil.
Preferably, when the primary coil is located above the secondary coil, the primary coil is an upper coil, the secondary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connection point of the primary coil; an upward through hole is formed at the inner side end point of the upper layer coil and is used as an inner side connecting point of the primary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the secondary coil; a downward through hole is formed at the innermost end point of the lower coil and is used as an inner connecting point of the secondary coil;
when the secondary coil is positioned above the primary coil, the secondary coil is an upper coil, the primary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connecting point of the secondary coil; an upward through hole is formed at the innermost end point of the upper coil and is used as an inner connecting point of the secondary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the primary coil; a downward through hole is arranged at the innermost end point of the lower coil and is used as an inner connecting point of the primary coil.
Wherein, all the connection points are manufactured by using a through hole process in an IC carrier plate process, and the connection points form a layer jump effect between an upper metal layer and a lower metal layer by using the through hole process in the IC carrier plate process.
Preferably, when the primary coil is located above the secondary coil, the connection point at the outer side of the primary coil and the connection point at the inner side of the primary coil are both connected with a top metal upwards through a through hole and connected to a PAD outside the coil through a metal lead, and the top metal is the uppermost metal in the IC carrier plate;
when the primary coil is positioned below the secondary coil, the connection point at the outer side of the primary coil and the connection point at the inner side of the primary coil are downwards connected with the lower metal layer of the second metal layer through holes and are connected to the PAD outside the coil through metal leads, and the lower metal layer is any metal layer lower than the lower metal layer.
When the secondary coil is located above the primary coil, the connection point at the outer side of the secondary coil and the connection point at the inner side of the secondary coil are both connected with the top metal upwards through the through holes and connected to the PAD outside the coil through the metal lead, and the top metal is the uppermost metal in the IC carrier plate.
When the secondary coil is positioned below the primary coil, the outer side connecting point of the secondary coil and the inner side connecting point of the secondary coil are downwards connected with the lower metal layer of the second metal layer through holes, are connected to the outside of the coil through metal connecting wires and are connected to the PAD outside the coil through metal lead wires, and the lower metal layer is any metal layer lower than the lower metal layer.
Preferably, the number of turns of the first winding coil is the same as the number of turns of the second winding coil.
In another modification of the present application, the number of turns of the first winding coil is different from the number of turns of the second winding coil.
The number of turns and the turn ratio of the first winding coil and the second winding coil can be adjusted according to circuit requirements.
The primary coil and the secondary coil are positioned at the same position, but are not required to be completely overlapped.
Preferably, the isolation medium is an inter-metal medium in the IC carrier, and the material of the isolation medium includes but is not limited to polyimide, polyethylene and other epoxy resin mixed materials.
Another variant of the application may be: referring to fig. 2, an on-chip power transformer bank may also be formed by combining two pairs of transformer coil pairs as a DC-DC isolated power source power conversion module:
the transformer coil pair consists of a transformer coil pair 1 and a transformer coil pair 2, wherein the transformer coil pair 1 comprises a primary coil 11 and a secondary coil 12, and the transformer coil pair 2 comprises a primary coil 21 and a secondary coil 22.
The primary coil 11 and the primary coil 21 are respectively connected with the output end of a primary driving circuit, the primary driving circuit adopts a power amplifier to drive a transformer, the secondary coil 12 and the secondary coil 22 are respectively connected with the input end of a secondary rectifying circuit, and the secondary rectifying circuit converts alternating current output by the transformer into output direct current and outputs the output direct current to a rear-stage load.
The terms "first," "second," and the like, are used for distinguishing between similar objects and not for describing a particular sequential or chronological order.
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus/apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus/apparatus.
Thus far, the technical solution of the present application has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present application is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present application, and such modifications and substitutions will be within the scope of the present application.
Claims (11)
1. An on-chip power transformer based on an IC carrier board, comprising: at least one pair of transformer coils and at least one isolation medium;
the transformer coil comprises a primary coil and a secondary coil, and the primary coil and the secondary coil are mutually overlapped;
the isolation medium is located between the primary coil and the secondary coil, and the isolation medium is capable of galvanically isolating the primary coil from the secondary coil.
2. The on-chip power transformer based on the IC carrier of claim 1, wherein the primary winding is composed of a first metal coil, the first metal coil is circumferentially located in a first metal layer, the first metal coil is in a spiral structure which is arranged in a diffusing manner from inside to outside, and the first metal layer is an electroplated copper layer of the IC carrier;
the secondary coil consists of a second metal coil, the second metal coil is circumferentially arranged in a second metal layer, the second metal coil is of a spiral structure which is arranged in a diffusion manner from inside to outside, the second metal layer and the first metal layer are mutually staggered and are arranged in parallel, and the second metal layer is an electroplated copper layer of the IC carrier plate;
the primary coil is connected with the output end of the primary driving circuit, the secondary coil is connected with the input end of the secondary rectifying circuit, and the on-chip power transformer, the primary coil and the secondary coil are packaged in the same circuit in a multi-chip packaging mode.
3. An on-chip power transformer based on an IC carrier as claimed in claim 2, wherein: the first metal turn is located above or below the second metal turn.
4. An on-chip power transformer based on an IC carrier as recited in claim 3, wherein said first metal layer of said primary winding is etched to form a spiral first winding, and said second metal layer of said secondary winding is etched to form a spiral second winding.
5. The IC carrier based on-chip power transformer of claim 4, wherein when said primary winding is above said secondary winding, said primary winding is an upper winding, said secondary winding is a lower winding, and an upward through hole is provided at an outermost end of said upper winding as a primary winding outer connection point; an upward through hole is formed at the inner side end point of the upper layer coil and is used as an inner side connecting point of the primary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the secondary coil; a downward through hole is formed at the innermost end point of the lower coil and is used as an inner connecting point of the secondary coil;
when the secondary coil is positioned above the primary coil, the secondary coil is an upper coil, the primary coil is a lower coil, and an upward through hole is formed at the outermost end point of the upper coil and is used as an outer connecting point of the secondary coil; an upward through hole is formed at the innermost end point of the upper coil and is used as an inner connecting point of the secondary coil; a downward through hole is formed at the outermost end point of the lower coil and is used as an outer connecting point of the primary coil; a downward through hole is arranged at the innermost end point of the lower coil and is used as an inner connecting point of the primary coil.
6. The IC carrier-based on-chip power transformer of claim 5, wherein when the primary coil is located above the secondary coil, the primary coil outer connection point and the primary coil inner connection point are both connected to a top metal layer, which is the uppermost metal layer in the IC carrier, upward through a via hole and connected to a PAD outside the coil through a metal lead.
7. The IC carrier based on-chip power transformer of claim 5, wherein when the primary coil is located below the secondary coil, the primary coil outside connection point and the primary coil inside connection point are connected to the lower metal layer of the second metal layer downward through vias and connected to the PAD outside the coil through metal leads.
8. An on-chip power transformer based on an IC carrier as recited in claim 5, wherein: when the secondary coil is located above the primary coil, the connection point at the outer side of the secondary coil and the connection point at the inner side of the secondary coil are both connected with the top metal upwards through the through holes and connected to the PAD outside the coil through the metal lead, and the top metal is the uppermost metal in the IC carrier plate.
9. An on-chip power transformer based on an IC carrier as recited in claim 5, wherein: when the secondary coil is positioned below the primary coil, the outer side connecting point of the secondary coil and the inner side connecting point of the secondary coil are downward connected with the lower metal layer of the second metal layer through holes, are connected to the outside of the coil through metal connecting wires, and are connected to the PAD outside the coil through metal lead wires.
10. An on-chip power transformer based on an IC carrier as claimed in claim 9, wherein: the number of turns of the first winding coil is the same as or different from the number of turns of the second winding coil.
11. The on-chip power transformer based on the IC carrier of claim 10, wherein the isolation medium is an inter-metal medium in the IC carrier, and the isolation medium is any one of polyimide, polyethylene, and epoxy resin mixed material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310631742.3A CN116721846A (en) | 2023-05-31 | 2023-05-31 | On-chip power transformer based on IC carrier plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310631742.3A CN116721846A (en) | 2023-05-31 | 2023-05-31 | On-chip power transformer based on IC carrier plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116721846A true CN116721846A (en) | 2023-09-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310631742.3A Pending CN116721846A (en) | 2023-05-31 | 2023-05-31 | On-chip power transformer based on IC carrier plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116721846A (en) |
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2023
- 2023-05-31 CN CN202310631742.3A patent/CN116721846A/en active Pending
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