CN116719684B

CN116719684B - 3D packaged chip test system

Info

Publication number: CN116719684B
Application number: CN202311008071.1A
Authority: CN
Inventors: 王嘉诚; 张少仲
Original assignee: Zhongcheng Hualong Computer Technology Co Ltd
Current assignee: Zhongcheng Hualong Computer Technology Co Ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-10-20
Anticipated expiration: 2043-08-11
Also published as: CN116719684A

Abstract

The invention discloses a 3D packaged chip test system, which belongs to the technical field of integrated circuit test, and comprises a test platform and an FPGA test controller, wherein the test platform comprises a natural language interaction interface and a natural language processing engine, the FPGA test controller is integrated in a 3D packaged chip to be tested, and the natural language interaction interface is used for interacting with a tester in natural language; the natural language processing engine is used for analyzing and identifying natural language commands input by testers, converting the identified command types and parameters into VHDL or Verilog codes in the natural language processing engine and outputting the VHDL or Verilog codes to the FPGA test controller for control or deployment of the hardware auxiliary test module; and the FPGA test controller is used for loading and executing the received VHDL or Verilog codes. The invention improves the usability of 3D packaging chip test, reduces the skill requirement of testers, and realizes the natural language interaction and the integration of the existing hardware test module.

Description

3D packaged chip test system

Technical Field

The invention belongs to the technical field of integrated circuit testing, and particularly relates to a 3D packaged chip testing system.

Background

The 3D packaging technology has become an important trend in chip design and manufacturing, and this technology allows electronic components with different functions to be closely stacked in a three-dimensional space, thereby improving integration, performance and power consumption efficiency. However, as the complexity of 3D packaged chips continues to increase, traditional chip testing methods have difficulty meeting increasingly stringent test requirements.

Existing testing methods often require a high degree of expertise from a tester to write and execute complex digital test commands. These methods may lack flexibility and ease of operation, resulting in the testing process becoming inefficient and cumbersome. In addition, human error in operation and deviation in understanding during the test may lead to inaccuracy of the test result, thereby affecting the quality and reliability of the product.

In addition, existing test controllers are typically hard coded, meaning that the tester needs to have knowledge of the deep hardware description language (e.g., VHDL or Verilog) in order to program and debug the test flow. This approach limits the flexibility of the testing process to a large extent, while increasing the learning cost and skill requirements of the tester.

Therefore, the existing 3D packaging chip testing method has a plurality of defects, and is mainly characterized by complex operation, poor flexibility, low usability, high requirements on skills of testers and the like. Therefore, there is a need to develop a new testing method to overcome these problems and improve the efficiency and accuracy of testing 3D packaged chips.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a 3D packaged chip test system, the test system comprising a test platform and an FPGA test controller, wherein the test platform comprises a natural language interaction interface and a natural language processing engine, the FPGA test controller is integrated in a 3D packaged chip to be tested, characterized in that,

the natural language interaction interface is used for a tester to input a test command in natural language, adjust test parameters and display test results;

the natural language processing engine is used for analyzing and identifying natural language commands input by a tester, converting the identified command types and parameters into VHDL or Verilog codes which can be understood and executed by the FPGA test controller through a custom command protocol in the natural language processing engine, and outputting the VHDL or Verilog codes converted by the natural language processing engine of the test platform to the FPGA test controller for controlling or deploying the hardware auxiliary test module;

And the FPGA test controller is used for loading and executing the received VHDL or Verilog codes.

Wherein the controlling or deploying hardware-assisted test module comprises:

controlling a built-in self-test BIST module;

and deploying a virtual bi-directional built-in self-test BIDI module and a built-in thermal failure test BHFI module.

Wherein the identified command types and parameters are converted in the natural language processing engine into VHDL or Verilog code which can be understood and executed by the FPGA test controller by a custom command protocol, comprising

Creating a VHDL or Verilog code template corresponding to each possible command type;

when an instruction is generated, the identified parameter value is replaced into a corresponding code template;

after parameter replacement is completed, converting the modified code template into executable VHDL or Verilog codes;

wherein placeholders and variables in the code template are replaced with actual signal and register names in the test preparation phase.

The test platform automatically identifies the 3D chip to be tested and acquires related information, and inquires the application scene of the chip to the test personnel according to the 3D chip to be tested;

The test platform generates a recommended test strategy according to the application scene and the historical test data;

the recommended test strategy comprises one or more test items, the test platform displays the recommended test strategy to a tester in a form of a table, and the table contains test parameters and execution/non-execution options for each test item;

wherein for test items that have to be executed, the test parameters are displayed, and for optional test items, the corresponding test parameters are provided only if the item is selected for execution.

The built-in self-test BIST comprises a logic circuit function test, a memory unit function test, an I/O function test and a through silicon hole TSVs test;

the test items of the bi-directional built-in self-test BIDI are a high-speed data transmission interface test and a power supply integrity test;

the test item of the built-in thermal failure test BHFI is an error correction code test ECC under the thermal stability performance test condition.

In the 3D chip package, an FPGA test controller is in quick communication with a hardware auxiliary test module BIST, the FPGA test controller is deployed on a different side of an intermediate silicon board from the hardware auxiliary test module, and the FPGA test controller is in communication with the hardware auxiliary test module BIST through a silicon hole TSVs;

The BIST module shares registers and memories with other modules of the chip to be tested, and specifically comprises taking registers or memories of other modules in the chip to be tested as storage spaces of a test vector generator and a result analyzer;

when there are a plurality of other modules that are selectable as shared registers or memory, the module closest to the horizontal projection distance of the FPGA test controller is selected as the module that shares registers or memory with the BIST.

BIDI testing for high performance computing HPC application scenarios, among others, includes configuring BIDI functionality in the following modules:

configuring a test circuit function of a virtual BIDI module in an FPGA test controller;

configuring a tested circuit function of BIDI in a processor core module;

configuring a tested circuit function of BIDI in a memory controller module;

configuring a tested circuit function of BIDI in an interconnection network module;

after receiving a deployment instruction of an external controller, the FPGA test controller forwards a corresponding configuration code to a corresponding module;

the external controller is a test platform.

The 3D package chip is tested by executing BIST test, if BIDI is needed to be executed, the BIDI test is continuously executed, the BIDI virtual module is deployed to the chip to be tested by an external controller to carry out the BIDI test, after the BIDI test is executed, whether the BHFI test is needed to be executed is judged, and then the test deployment of the BHFI virtual module is carried out based on the test scheme parameters of the BHFI.

Determining partial test parameters of the BHFI according to the test parameters used in the BIDI test, the test results returned in the BIDI test and the performance parameters of the chip, and determining whether the partial test parameters in the recommended test scheme of the BHFI need to be modified according to the difference between the partial test parameters of the BHFI and the test parameters in the recommended test scheme of the BHFI;

when the difference between the two parameters exceeds a preset threshold value, determining partial test parameters which need to be adjusted to BHFI;

and after determining that the partial test parameters of the BHFI need to be adjusted, initiating a modification prompt to a test user through a natural language interaction interface of the test platform and receiving feedback of the test user on whether to modify the partial test parameters in the BHFI recommended test scheme.

The partial test parameters of the BHFI are the test continuous working temperature of the error correction code test ECC under the thermal stability performance test condition of the BHFI test project.

The following test parameters and test results of BIDI test and chip performance parameters are known as the minimum test rate of BIDI test, R_min, R_max, and the chip temperature fed back by the temperature sensor when BIDI test is executed, T_BIDI (R), and the chip supports the highest rate R_chip;

For the test sustained operating temperature of the BHFI test, the average temperature variation ratio k_t in the BIDI test is calculated:

k_T=fracT_BIDI(R_max)-T_BIDI(R_min)/(R_max-R_min)，

wherein, k_t: the temperature change proportionality coefficient is used for representing the change trend of the chip temperature along with the increase of the speed in the BIDI test process;

t_bidi (r_max): chip temperature at maximum rate in the BIDI test;

t_bidi (r_min): chip temperature at minimum rate in the BIDI test;

r_max: maximum rate of BIDI test;

r_min: minimum rate of BIDI test;

the temperature T BHFI at the highest rate supported by the chip is then estimated with the scaling factor k_t as the test sustained operating temperature for the BHFI test:

，

wherein,,

t_bidi (r_min): chip temperature at minimum rate in the BIDI test;

k_t: a temperature change scaling factor;

r_chip: the highest rate supported by the chip;

r_min: minimum rate of BIDI test.

The invention can intuitively input the test command and parameters by the tester through the natural language interactive interface without writing complex digital test commands, thereby greatly simplifying the test flow and improving the flexibility and usability of the test process. Because the commands involved in the testing process of the invention can be input through natural language, the testers do not need to have deep hardware description language knowledge, the learning cost and skill requirements of the testers are reduced, and more testers can participate in the testing work.

The natural language processing engine converts the identified command types and parameters into VHDL or Verilog codes which can be understood and executed by the FPGA test controller through the custom command protocol, and the conversion process is efficient and accurate, so that the reliability of the test result is ensured.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 is a schematic diagram illustrating a 3D packaged chip test system according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.

It should be understood that although the terms first, second, third, etc. may be used to describe … … in embodiments of the present invention, these … … should not be limited to these terms. These terms are only used to distinguish … …. For example, the first … … may also be referred to as the second … …, and similarly the second … … may also be referred to as the first … …, without departing from the scope of embodiments of the present invention.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or device comprising such element.

As shown in fig. 1, a 3D packaged chip test system includes a test platform including a natural language interaction interface and a natural language processing engine, and an FPGA test controller integrated in a 3D packaged chip to be tested.

The testing platform comprises a natural language interaction interface which allows a tester to input testing commands and parameters in natural language so as to improve the flexibility and usability of the testing process and reduce the skill requirements of the tester.

The test platform also comprises a natural language processing engine for analyzing and identifying natural language commands input by testers, wherein the engine comprises functions of command classification, parameter extraction, semantic understanding and the like, and the natural language understanding function can be developed by using the existing natural language processing framework (such as a GPT series model of OpenAI) as a basis. And converting the identified command types and parameters into VHDL or Verilog codes which can be understood and executed by the FPGA test controller through a custom command protocol in a natural language processing engine. The test platform is an external controller.

The VHDL or Verilog code converted from the natural language processing engine of the test platform is output to the test controller for controlling or deploying hardware-assisted test modules (control BIST, deploy BIDI and BHFI). Wherein the generated VHDL or Verilog code is sent to an FPGA test controller, including transmitting the code through a communication interface such as UART, SPI or I2C.

The received VHDL or Verilog code is loaded and executed on the FPGA test controller.

And executing test operation in the test controller, and automatically performing local test, component test and system level test on the chip. Meanwhile, test results are collected in real time, converted into natural language descriptions through a natural language processing engine and displayed on a natural language interaction interface, so that test staff can quickly understand and evaluate the test results.

Through the natural language interaction interface, a tester can easily adjust the test parameters, so that the test process is quickened.

The invention can realize a more intelligent, flexible and easy-to-use 3D packaging chip testing method. The method can improve the test efficiency and reduce the test cost.

Wherein placeholders and variables in the code template need to be replaced with actual signal and register names before the 3D packaged chip test begins in order to integrate with existing FPGA test controller code.

In one embodiment, the identified command types and parameters are converted in the natural language processing engine by a custom command protocol into VHDL or Verilog code that the FPGA test controller can understand and execute.

First, a VHDL or Verilog code template corresponding to each possible command type is created. These templates define how to perform test operations, control or deploy hardware-assisted test modules. For example, a code template is created for the "initiate BIST test" command, which contains logic and control signals for initiating BIST test.

When the instruction is generated, the identified parameter values are replaced into the corresponding code templates. For example, if "test frequency is 100MHz" is included in the natural language input, the parameter value is replaced to the corresponding location in the code template associated therewith.

After parameter replacement is completed, the modified code template is converted into executable VHDL or Verilog code. Wherein placeholders and variables in the code template are replaced with actual signal and register names in the test preparation phase for integration with existing FPGA test controller code.

In one embodiment, in the process of the natural language processing engine implementing instruction translation, the natural language processing engine first needs to identify keywords and phrases in the input natural language to determine user intent and needs, including identifying predetermined keywords such as "test", "start" and "parameters".

The natural language processing engine needs to match the identified keywords and phrases with predefined command templates to determine the specific test command type. Including based on the input text, the engine can sort commands as "initiate BIST test", "adjust test parameters", etc.

After determining the command type, the natural language processing engine needs to further extract relevant parameters in the input text, including specific values related to identification numbers, time, frequency, etc., or identify specific hardware components and test items.

Finally, according to the identified command type and parameters, the natural language processing engine converts the identified command type and parameters into VHDL or Verilog codes which can be understood and executed by the FPGA test controller according to a custom command protocol.

In one embodiment, a tester initiates a test procedure through a user interface. The test platform automatically identifies the 3D chip to be tested and acquires related information. The test platform inquires the application scene of the chip to the tester according to the 3D chip to be tested, for example, the application scene of the chip is planned to be used by the tester by inquiring words on an interface. The test platform generates a recommended test strategy according to the application scene and the historical test data provided by the user, wherein the test strategy comprises one or more test items, and the test parameters and execution/non-execution options for each test item are contained. The test platform displays the recommended test strategy to the testers in a table form, wherein the table contains test parameters and execution/non-execution options for each test item, the test parameters are directly displayed in the table for the test item which needs to be executed, and for the optional test item, the corresponding test parameters are provided only when the test item is selectively executed.

Meanwhile, the test platform describes recommended test strategies through natural language, and helps testers to better understand scheme contents. For example, "according to your XXX application scenario, it is recommended to perform RAM testing based on built-in self-test (BIST), while it is optional to perform bi-directional built-in self-test (BIDI) and built-in thermal failure test (BHFI)".

The tester can modify the recommended test strategy according to the need, and the modification can comprise directly adjusting parameter values in a table or can be performed through natural language indication. For example, the tester may input "adjust BIST test depth from 1024 to 2048".

The tester reviews and validates the final test strategy. The test platform will generate test scripts that can execute the VHDL or Verilog code according to the finalized test strategy. And sending the generated test script to a test controller and executing the test script. The test controller performs corresponding test operations, such as connecting hardware, executing test, collecting data, etc., according to the script content.

After the test is completed, the system platform feeds back the test result to the tester in the form of natural language or visual graph of test data. For example, "RAM test is completed, no failure is found".

In one embodiment, it is assumed that a tester is testing a 3D chip that is primarily used in the field of High Performance Computing (HPC) for large-scale scientific simulation and data processing tasks. The recommended test protocols that the test platform may give may be shown in the following table:

in the above table, built-in self-tests (BISTs) include logic circuit functional tests, memory cell functional tests, I/O functional tests, and Through Silicon Via (TSVs) tests. The sub-project of the bi-directional built-in self test (BIDI) (high speed data transmission interface test and power supply integrity test), the project of the built-in thermal failure test (BHFI) (error correction code test ECC under thermal stability performance test conditions).

Note that the above table is merely an example of a basic test case, and it is possible to set other more detailed test items according to the specific situation of the 3D chip, so as to meet the requirements of the actual test engineering, but the implementation scheme and technical means are consistent with the test case disclosed in the present invention.

For another example, assuming that a tester is testing a 3D chip, the chip is mainly applied to an application field of indoor environment monitoring application, a recommended test scheme given by the test platform may be shown in the following table:

In some application scenarios, including indoor environment monitoring and home appliance control, the chip may not be in a high-temperature environment, and the heat dissipation requirement is low, so that only BIST is performed on the 3D package chip.

In one embodiment, the natural language processing engine converts the parsed natural language commands into VHDL code. VHDL is a hardware description language. The VHDL code is compiled into a bitstream file that is suitable for a particular FPGA chip using the FPGA development tool Xilinx. And downloading the bit stream file into an FPGA chip, wherein the FPGA configures the internal logic resources according to the file, thereby realizing the function of the test controller.

In one embodiment, in a 3D chip package, a test controller implemented by an FPGA is in fast communication with a hardware-assisted test module BIST, the FPGA test controller is deployed on a different side of an intermediate silicon board than the hardware-assisted test module, and the FPGA test controller is in fast, low-latency communication with the hardware-assisted test module BIST through silicon holes TSVs.

In one embodiment, the FPGA is BIST connected to the hardware-assisted test module and the I/O pins of the FPGA are used to communicate with the interface of the hardware-assisted test module. The FPGA is connected to an external interface (JTAG or other debug interface) to download VHDL code generated by the natural language processing engine into the FPGA and collect test results. Logic functions of the test controller are realized in the FPGA through a lookup table (LUTs), a trigger (flip-flop) and other programmable resources, and the functions comprise command analysis, test strategy generation, test execution, test result processing and the like.

BIST (built-in self test) modules are a technique for testing digital integrated circuits, the chip being capable of performing self-tests.

The main functions of the BIST module include generating test vectors: during the test, the BIST module automatically generates input data for the test circuit; applying the test vector, applying the automatically generated test vector to a chip circuit to be tested, and collecting an output result;

analyzing the test result, and analyzing the collected output result to judge whether the circuit to be tested has defects; providing test results and reporting the test results to a test controller.

Before the test starts, the test controller configures the BIST module according to the test requirements. The BIST module automatically generates and applies test vectors, such as pseudo-random sequences, to the circuit under test. The circuit to be tested generates an output result according to the input test vector. The BIST module collects output results of the circuit to be tested and analyzes the output results through a built-in result analyzer. The BIST module reports the test results (pass/fail) to the test controller.

The BIST module comprises the following components. And the test vector generator is responsible for generating input data for testing. This is typically achieved by a Linear Feedback Shift Register (LFSR) or a counter. And the test execution unit is used for applying the test vector to the circuit to be tested and collecting an output result. This is typically accomplished by a Multiplexer (MUX) and registers. And the result analyzer is used for analyzing the collected output result to judge whether the circuit to be tested has defects or not. This is typically achieved by dedicated comparators and state machines. Control logic in communication with the test controller and controlling operation of the BIST module according to its instructions. This is typically accomplished through a state machine and I/O interface.

The communication mechanism between the BIST and the test controller includes:

configuration interface: allowing the test controller to send configuration information to the BIST module before the test begins.

Control signal: for starting, stopping or suspending the test procedure.

Result interface: allowing the BIST module to report the test results to the test controller.

The communication mechanism may be implemented by a parallel or serial interface, such as an SPI, I2C, or other custom interface.

In one embodiment, the BIST module uses certain registers or memories in the chip under test as the storage space for the test vector generator and the result analyzer. The special memory resources required by the BIST module are reduced by sharing registers and memory, thereby saving chip area and power consumption. When there are a plurality of other modules that are selectable as shared registers or memory, the module closest to the horizontal projection distance of the FPGA test controller is selected as the module that shares registers or memory with the BIST.

In one embodiment, the BIST module and the circuit under test share the same clock and reset signals. This may reduce the wiring and I/O resources required for separate clock and reset signals.

In one embodiment, in a non-test mode, the I/O interface of the BIST module is shared with the I/O interface of the circuit under test. By using a Multiplexer (MUX), these interfaces are switched to the input and output of the BIST module in test mode, thereby reducing the chip area and I/O resources required for dedicated test interfaces.

BIDI (bidirectional built-in self test), which is a technique for testing digital integrated circuits, can be a virtual module, and is characterized in that it can perform bidirectional testing, i.e. the module can be used as a test controller or a circuit under test.

In one example of a 3D packaged chip in a 3-layer structure, the controller FPGA is located at the top layer 3 and the hardware assisted test module BIST is located at the bottom layer 1. With a layer of intervening silicon plate therebetween. Communication between the FPGA controller and the BIST module is achieved through silicon holes TSVs, a silicon hole between two layers of silicon boards is a three-dimensional integration technique for providing vertical electrical connections between multiple layers of stacked chips or silicon boards. This way of connection allows a faster signal transmission speed between the different layers.

For shared register or memory configurations, it is assumed that there are two optional modules on the second intermediate silicon board that can be used as shared memory functions, one of which needs to be selected for sharing with the BIST. To ensure optimal communication performance, the memory module closest to the horizontal distance of the layer 4 FPGA controller is selected (e.g., only the projection distance on the horizontal xy plane projection is considered in three-dimensional modeling).

In one embodiment, the BIDI module of the present invention is used for high speed data transmission interface testing (SerDes) and Power supply integrity testing (PSI).

The BIDI module is used as a test controller for generating a test vector, applying the test vector to a circuit to be tested, and collecting and analyzing an output result. High-speed serial data is generated for testing the SerDes interface. The power supply voltage and current are monitored, power supply anomalies are detected, and power supply disturbances are injected for testing the integrity of the power supply.

The BIDI module is used as a tested circuit, receives the test vector from the external test controller, generates a corresponding output result and sends the corresponding output result back to the test controller. High-speed serial data is sent and received for SerDes interface testing. Supply voltage and current measurements and power supply abnormal state information are provided.

In one embodiment, BIDI module operation may be divided into the following phases:

before the test starts, the external controller configures the virtual BIDI module according to the test requirements.

When used as a test controller, the BIDI module automatically generates and applies test vectors to the circuit under test.

When the BIDI module is used as a test controller, the BIDI module generates high-speed serial data and sends the high-speed serial data to a tested SerDes interface; when used as a circuit under test, the BIDI module receives high-speed serial data from the test controller.

When the BIDI module is used as a test controller, the BIDI module monitors the voltage and the current of the power supply, detects the abnormality of the power supply, and injects power supply disturbance; when the BIDI module is used as a tested circuit, the BIDI module provides a power supply measurement result and power supply abnormal state information.

When the BIDI module is used as a test controller, the BIDI module collects the output result of the tested circuit, the SerDes test result and the PSI test result, analyzes the output result, the SerDes test result and the PSI test result, and reports the test result to an external controller.

In one embodiment, for example, when BIDI is applied as a virtual module in a high performance computing HPC scenario, it is desirable to configure the sending and monitoring functions of BIDI in the test controller module, and the receiving and feedback functions of BIDI in the circuit module under test.

Wherein the BIDI is configured in the test controller module, for high-speed serial data transmission, comprising integrating a high-speed serial data generator for generating test vectors and transmitting them to the SerDes interface under test, typically comprises a pseudo random bit sequence PRBS generator, clock generator and serializer. In addition, the integrated power supply voltage and current monitoring function is a power supply monitor for power supply monitoring so as to detect power supply abnormality in real time; the integrated power disturbance injection function is a power disturbance injector and is used for simulating power supply change under actual working conditions.

The BIDI is configured in the tested circuit module, and for high-speed serial data receiving, a high-speed serial data receiver is integrated for receiving the test vector from the test controller, and generally comprises a deserializer, a clock restorer and an error code detector. For power supply measurement and abnormal state feedback, including integrated power supply measurement and power supply abnormal state feedback functions, to send power supply information back to the test controller, including a power supply status reporter and a serial or parallel data interface.

In one embodiment, taking BIDI testing in HPC scenarios as an example, BIDI functionality needs to be configured in the following modules:

FPGA test controller: the test circuit function of the virtual BIDI module is configured.

The processor core: the processor core is the main computational component in the HPC system and requires stringent functional and performance tests. The BIDI's circuit function under test is configured in the processor core module for high-speed interface and power integrity testing thereof.

A memory controller: the memory controller is responsible for processing memory access requests from the processor core, and has high requirements on performance and reliability. The tested circuit functions of BIDI are configured in the memory controller module for high-speed interface and power integrity testing.

Interconnection network: the interconnection network connects the processor core, the memory controller, and other peripherals, and has high latency and throughput requirements. The tested circuit functions of the BIDI are configured in the interconnect network module for high speed interface and power integrity testing thereof.

In a certain embodiment, since the FPGA test controller and the module to be tested are in communication connection inside the 3D package chip, after the FPGA test controller receives the deployment instruction of the external controller, the FPGA test controller receives all the deployment instructions and then forwards the corresponding configuration codes to the corresponding modules.

A Built-in thermal failure test BHFI (build-inHardwareFaultInjection) module is a hardware-assisted test module for automatically injecting faults during chip testing to evaluate the performance and reliability of a chip in the face of faults.

The virtual BHFI (build-inHardwareFaultInjection) module is a software-based fault injection method for automatically injecting faults during software testing to evaluate the performance and reliability of software in the face of faults.

In one embodiment, to implement an Error Correction Code (ECC) test at a specific operating temperature in an actual physical environment, it is necessary to combine the actual hardware environment, including hardware heat dissipation and temperature control devices, and then combine the virtual BHFI module with the hardware environment to perform the ECC test.

In order to perform temperature control in an actual hardware environment, special heat dissipation and temperature control equipment is required, and the temperature of the chip is adjusted by adjusting the power of the heat sink through the heat dissipation and temperature control equipment so as to perform ECC test within a specific working temperature range.

After the temperature of the hardware environment is set, the virtual BHFI module is used for ECC testing.

In one embodiment, the test control module is connected with the hardware heat dissipation and temperature control device and the temperature sensor inside the 3D chip to perform the functions of data monitoring and hardware control.

In one embodiment, the virtual BHFI module hosts a preset fault model, including a fault model associated with operating temperature and a fault model associated with memory. The generated fault sequence is injected into a specific part of the hardware, which may be a simulator/simulator plug-in, or a piece of instrumented code. The virtual BHFI module controls the fault injection process and collects response data of hardware when affected by faults, and the response data can be achieved by adding data collection sentences into the instrumentation code or calling a data collection function provided by the FPGA test controller.

In one embodiment, the BHFI module is written using a hardware description language (e.g., VHDL or Verilog) that is suitable for use with existing FPGA test controllers. This module includes a fault model library, fault injectors, and data collection and processing functions.

And integrating the designed BHFI module into the hardware design of the existing FPGA test controller.

The FPGA test controller is connected with a target module which needs to be subjected to fault injection test, so that the test controller can perform fault injection and data collection on the target module.

To achieve ECC testing at a particular operating temperature, a temperature sensor (e.g., a thermistor) and a temperature control device (e.g., a PID controller and a heat sink) are required to monitor and adjust the temperature of the system. And the output signal of the temperature sensor is connected to the FPGA test controller, so that the temperature of the system can be monitored in real time. Meanwhile, the temperature control equipment is connected with the FPGA so that the test controller can adjust the working temperature of the system according to the requirement.

And configuring a fault injection strategy according to the test requirement, wherein the fault injection strategy comprises the steps of selecting the fault type to be injected, fault distribution and the occurrence time of the fault.

And performing ECC (error correction code) test at a specific working temperature in an actual hardware environment, simulating fault injection by using a BHFI module on the existing FPGA test controller, and collecting response data of the chip when the chip is affected by the fault. Based on the collected data, the performance and reliability of the ECC under different temperature environments are evaluated.

In a certain embodiment, a fault model of a test that selects a 3D packaged chip to be tested is determined. Common fault models include: bit flipping (single or multiple bits), random faults, timing faults, shorts, opens, and the like.

Determining the object (registers, memory, logic gates, etc.) and location to inject the fault may select the critical components of the system as the object and location to inject the fault.

The distribution and probability of fault injection is selected, e.g., uniform distribution, normal distribution. The probability of faults, such as fixed probability or probability of change with time or temperature, is determined, and proper distribution and probability are selected to better simulate error conditions under actual working conditions. The moment at which the fault occurs is determined, for example, a periodic injection, a random point in time injection, or a specific event triggered injection. And configuring parameters of the fault injector, including fault type, position and occurrence probability, according to the selected fault model and strategy.

And applying the configured fault injection strategy to a test controller, and executing an actual fault injection test.

In one embodiment, when BIDI test is needed, the test platform further refines the test parameters of SerDes according to the application scenario of the 3D packaged chip and the performance parameters of the 3D packaged chip. If applied to the field of High Performance Computing (HPC), the test platform adjusts SerDes test parameters according to the characteristics of the HPC. The test platform may further ask questions to the test user to obtain a specific HPC application type.

In one embodiment, where high throughput and high bandwidth data transmission requirements are critical, such as in a large model training scenario, the test rate range may need to cover the highest rate supported by the chip to ensure stable performance is still maintained under high load, the steps should be set small to allow detailed assessment of SerDes performance at different rates. For example, if the chip supports the highest rate of 56Gbps, the test rate range is set to 10Gbps to 56Gbps, and the step is set to 2Gbps.

In certain embodiments, such as in the context of applications such as scientific simulation and data analysis, the test platform may be concerned with delay-sensitive data transmission and parallel processing capabilities for complex scientific computing and large-scale data analysis applications. The test rate range is set to cover the rates required for common scientific computing and data analysis applications, while the stepping can be set to moderate to ensure adequate testing of SerDes performance in critical rate intervals. For example, if the chip supports a maximum rate of 56Gbps, the test rate range is set to 1Gbps to 40Gbps, and the step-by-step is set to 5Gbps.

In some embodiments, such as high performance graphics processing scenarios, for high performance graphics processing applications, such as real-time rendering and virtual reality, the test platform may be concerned with the transmission capabilities of high resolution video signals, with test rate ranges ranging from low resolution to high resolution and high frame rates, which are required to cover various common graphics processing applications. The step can be set to be moderate or small in order to test the SerDes performance in detail in the critical rate interval. For example, if the chip supports the highest rate of 56Gbps, the test rate range is set to 2.5Gbps to 32.4Gbps (conforming to the HDMI2.1 standard), and the step-by-step setting is set to 2Gbps.

In one embodiment, the test rate range should cover at least the minimum rate and the maximum rate stated in the chip specification. To ensure performance reliability of the chip under various operating conditions, the test rate range may need to be slightly extended, including a range below the minimum rate and above the maximum rate.

In one embodiment, the choice of test steps depends on the test requirements and resolution. In determining the step, a trade-off between test resolution and test time is required, including setting smaller steps in critical performance intervals (e.g., near minimum rate, maximum rate, or other rates required for a particular application scenario), and larger steps in other intervals.

In a certain embodiment, the order of executing the test on the 3D package chip is BIST test, if the BIDI test needs to be executed, the BIDI test is continuously executed, the external controller deploys the BIDI virtual module to the chip to be tested to perform the BIDI test, after the execution of the BIDI test is finished, whether the BHFI test needs to be executed is judged, if yes, part of the test parameters of the BHFI are determined according to the test parameters used in the BIDI test, the test results returned in the BIDI test and the performance parameters of the chip, and if not, the test parameters in the recommended test scheme of the BHFI need to be modified are determined according to the difference between the test parameters of the BHFI and the test parameters in the recommended test scheme of the BHFI. And when the difference between the two parameters exceeds a preset threshold value, determining that the test parameters of the BHFI need to be adjusted. And after determining that the test parameters of the BHFI need to be adjusted, initiating a modification prompt to a test user through a natural language interaction interface of the test platform, receiving feedback of the test user on whether to modify the test parameters in the BHFI recommended test scheme, and then performing test deployment of the BHFI virtual module based on the test scheme parameters of the BHFI.

In one embodiment, the test parameters include a test rate range of the BIDI test, the test results include a chip temperature at the time of executing the BIDI test fed back by the temperature sensor in the BIDI test, and the chip performance parameters are chip support highest rates.

And determining partial test parameters of the BHFI based on a preset algorithm, wherein the partial test parameters of the BHFI are the test continuous working temperature.

In one embodiment, the following test parameters and test results and chip performance parameters of the BIDI test are known: the minimum test rate R_min of BIDI test, the maximum test rate R_max, the chip temperature T_BIDI (R) fed back by the temperature sensor when BIDI test is executed, and the chip supports the highest rate R_chip.

k_T=fracT_BIDI(R_max)-T_BIDI(R_min)/(R_max-R_min)，

wherein, k_t: the temperature change proportionality coefficient is used for representing the change trend of the chip temperature along with the increase of the speed in the BIDI test process.

T_bidi (r_max): chip temperature at maximum rate in the BIDI test.

T_bidi (r_min): chip temperature at minimum rate in the BIDI test.

R_max: maximum rate of BIDI test.

R_min: minimum rate of BIDI test.

。

wherein,,

t_bidi (r_min): chip temperature at minimum rate in the BIDI test.

k_t: temperature change scaling factor.

R_chip: the highest rate supported by the chip.

R_min: minimum rate of BIDI test.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

The foregoing description of the preferred embodiments of the present invention has been presented for purposes of clarity and understanding, and is not intended to limit the invention to the particular embodiments disclosed, but is intended to cover all modifications, alternatives, and improvements within the spirit and scope of the invention as outlined by the appended claims.

Claims

1. A 3D packaged chip test system comprising a test platform and an FPGA test controller, wherein the test platform comprises a natural language interaction interface and a natural language processing engine, the FPGA test controller is integrated in a 3D packaged chip to be tested, characterized in that,

The FPGA test controller is used for loading and executing the received VHDL or Verilog codes;

the method comprises the steps of converting recognized command types and parameters into VHDL or Verilog codes which can be understood and executed by an FPGA test controller through a custom command protocol in a natural language processing engine, and comprises the following steps:

2. The 3D packaged chip testing system of claim 1, wherein the controlling or deploying hardware-assisted test module comprises:

controlling a built-in self-test BIST module;

3. The 3D packaged chip testing system of claim 1, wherein the chip testing system comprises a plurality of test pads,

a tester starts a test flow through a user interface, a test platform automatically identifies a 3D chip to be tested and acquires related information, and the test platform inquires the tester about the application scene of the chip according to the 3D chip to be tested;

4. The 3D packaged chip test system of claim 1 or 3,

the built-in self-test BIST comprises a logic circuit function test, a memory cell function test, an I/O function test and a through silicon hole TSVs test;

5. The 3D packaged chip testing system of claim 2, wherein the chip testing system comprises a plurality of test pads,

6. The 3D packaged chip test system of claim 4, wherein the BIDI test for high performance computing HPC application scenarios comprises configuring BIDI functions in the following modules:

configuring a tested circuit function of BIDI in a processor core module;

configuring a tested circuit function of BIDI in a memory controller module;

the external controller is a test platform.

7. The 3D packaged chip testing system of claim 4, wherein the chip testing system comprises a plurality of test pads,

And the sequence of executing the test on the 3D packaged chip is to execute the BIST test firstly, if BIDI is required to be executed, continuing to execute the BIDI test, deploying the BIDI virtual module to the chip to be tested by an external controller to execute the BIDI test, judging whether the BHFI test is required to be executed after the BIDI test is executed, and then performing the test deployment of the BHFI virtual module based on the test scheme parameters of the BHFI.

8. The 3D packaged chip testing system of claim 7,

9. The 3D packaged chip testing system of claim 8, wherein the chip testing system comprises a plurality of chips,

and the partial test parameters of the BHFI are the test continuous working temperature of the error correction code test ECC under the thermal stability performance test condition of the BHFI test project.

10. The 3D packaged chip testing system of any one of claim 8 or 9,

knowing the following test parameters and test results of BIDI test and chip performance parameters as the minimum test rate of BIDI test, R_min, maximum test rate, R_max, and chip temperature fed back by a temperature sensor when BIDI test is executed, T_BIDI (R), and the chip supports the highest rate R_chip;

k_T=fracT_BIDI(R_max)-T_BIDI(R_min)/(R_max-R_min)，

t_bidi (r_max): chip temperature at maximum rate in the BIDI test;

t_bidi (r_min): chip temperature at minimum rate in the BIDI test;

r_max: maximum rate of BIDI test;

r_min: minimum rate of BIDI test;

，

Wherein,,

t_bidi (r_min): chip temperature at minimum rate in the BIDI test;

k_t: a temperature change scaling factor;

r_chip: the highest rate supported by the chip;

r_min: minimum rate of BIDI test.