CN116719006B - Satellite-borne passive positioning method and device based on multi-core heterogeneous architecture - Google Patents
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
The application provides a satellite-borne passive positioning method and device based on a multi-core heterogeneous architecture, which are applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture. The application fully utilizes the advantages of hardware, the FPGA realizes three paths of parallel data acquisition, preprocessing and mixed product operation in a pipeline mode, and adopts a double-DSP architecture for the operation process, and performs time-frequency difference estimation in a multi-kernel parallel mode, thereby greatly shortening the calculation time and meeting the requirements of algorithm realization on the DSP processing capacity. In addition, the application improves the parameter estimation precision through the time-frequency difference coarse value estimation and the second-order curved surface fitting, so as to realize the frequency difference estimation when the signal is high-precision and quick, and has lower calculation complexity and can fully save calculation resources. The method has the advantages of low hardware cost and short algorithm time consumption, and can meet the requirement of real-time processing and improve the precision of parameter estimation at the same time, thereby realizing the passive target positioning more efficiently and accurately.
Description
Technical Field
The application belongs to the field of satellite-borne passive positioning, and particularly relates to a satellite-borne passive positioning method and device based on a multi-core heterogeneous architecture.
Background
The three-satellite positioning is an important technology of satellite-borne passive positioning, the system adopts a main satellite and two auxiliary satellites to estimate the time delay from a target echo signal to the main satellite and the auxiliary satellites, and when the three satellites work, two groups of Time Differences (TDOA) are calculated by using the intercepted three-way target echo signals, and the position estimation of a target source is carried out by combining prior information. The method adopts a mode of passively intercepting the target signal, has strong concealment and can effectively locate the target with high precision. The main principle of time difference estimation is to use the correlation of each path of source signals. The parameter estimation mainly adopts a mutual blurring function algorithm to estimate the positioning parameters.
CAF (cross ambiguity function, mutual ambiguity function) is an important method for joint positioning of time-frequency differences. Due to the difference in distance and relative velocity of the target with respect to the plurality of airborne satellites, certain delay and doppler shifts are generated between the received echo signals. The mutual blurring function can be regarded as a two-dimensional correlation of time delay and Doppler shift, and parameter estimation is realized by two-dimensional searching of the peak of the mutual blurring function.
In order to ensure accuracy, the traditional mutual blurring function algorithm needs longer data accumulation, has larger calculated amount and is not beneficial to real-time processing. Some algorithms based on high order statistics have a good effect of suppressing related noise, but the problem of large calculation amount is not solved. In the time-frequency difference estimation method based on long-time coherent accumulation, sliding time delay adjustment is adopted, but the calculated amount is large, and the real-time processing is not facilitated. Therefore, the time-frequency estimation precision of the prior art on the three-star positioning is lower, and the calculation resources are more consumed.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides a satellite-borne passive positioning method and device based on a multi-core heterogeneous architecture. The technical problems to be solved by the application are realized by the following technical scheme:
the application provides a satellite-borne passive positioning method based on a multi-core heterogeneous architecture, which is applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture, and the satellite-borne passive positioning method based on the multi-core heterogeneous architecture comprises the following steps:
s100, the FPGA acquires echo data of three satellites, and segments the echo data in a time difference searching range to obtain segmented data;
s200, the FPGA sequentially performs preprocessing and mixed product operation on the segmented data to obtain mixed product data, and performs truncation rearrangement on the mixed product data; packaging and transmitting the truncated and rearranged mixed product data to a first DSP;
s300, the first DSP performs fixed-point to floating-point conversion operation on the received mixed product data to obtain floating-point data, and performs FFT processing on the floating-point data through a plurality of cores of the first DSP to obtain a CAF matrix;
s400, the first DSP determines a coarse estimated value of time delay and a coarse estimated value of Doppler frequency shift through peak search in a two-dimensional plane formed by the CAF matrix, and determines a precise estimated value of time delay and a precise estimated value of Doppler frequency shift through second-order surface fitting; transmitting the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to a second DSP;
s500, the second DSP performs positioning calculation according to the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to obtain the three-dimensional coordinates of the target, and uploads the three-dimensional coordinates of the target to the upper computer.
The application provides a multi-core heterogeneous architecture-based satellite-borne passive positioning device, wherein a signal processing module is arranged in the multi-core heterogeneous architecture-based satellite-borne passive positioning device and is used for realizing a multi-core heterogeneous architecture-based satellite-borne passive positioning method.
The application provides a satellite-borne passive positioning method based on a multi-core heterogeneous architecture, which is applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture. The application fully utilizes the advantages of hardware, the FPGA realizes three paths of parallel data acquisition, preprocessing and mixed product operation in a pipeline mode, and adopts a double-DSP architecture for the operation process, and 8-core parallel time-frequency difference estimation is adopted, so that the calculation time is greatly shortened, and the requirements of the algorithm on the DSP processing capability are met. In addition, the application improves the parameter estimation precision through the time-frequency difference coarse value estimation and the second-order curved surface fitting, so as to realize the frequency difference estimation when the signal is high-precision and quick, and has lower calculation complexity and can fully save calculation resources. The method has the advantages of low hardware cost and short algorithm time consumption, and can meet the requirement of real-time processing and improve the precision of parameter estimation at the same time, thereby realizing the passive target positioning more efficiently and accurately.
The present application will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic flow chart of a satellite-borne passive positioning method based on a multi-core heterogeneous architecture;
FIG. 2 is a schematic diagram of the implementation principle of the three-star positioning system provided by the application;
FIG. 3 is a schematic diagram of the configuration of the satellite-borne passive positioning algorithm provided by the application;
FIG. 4 is a schematic diagram of an implementation of the FIFO preprocessing for data buffering provided in the present application;
FIG. 5 is a schematic diagram of a mixed product operation result provided by the present application.
Detailed Description
The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.
The application provides a satellite-borne passive positioning method based on a multi-core heterogeneous architecture, which is applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture.
The chip model of the FPGA used in the application is JFM VX690T-FFG1761, and the FPGA is used for realizing acquisition, preprocessing and mixed product operation of three paths of parallel data. The model of the DSP chip used in the application is FT-M6678, which is used for realizing peak search, second order surface fitting and positioning calculation. The application can also select a DSP chip TMS320C6678. The two DSPs are DSP1 and DSP2 respectively. The DSP1 stores the result processed by the algorithm in a SRIO (Serial Rapid IO) sending buffer area, then transmits the result to the DSP2 through SRIO to perform positioning resolving processing to obtain the three-dimensional coordinates of the target, and returns and displays the processing result of the algorithm through Ethernet after positioning resolving is completed.
Referring to fig. 1 to 3, the application provides a satellite-borne passive positioning method based on a multi-core heterogeneous architecture, which comprises the following steps:
s100, the FPGA acquires echo data of three satellites, and segments the echo data in a time difference searching range to obtain segmented data;
referring to fig. 2, fig. 2 shows the principle of implementing a three-satellite positioning system, where the position information of three satellites is known, an aerial satellite intercepts a radar signal of a target source, filters the radar signal, and sends the signal to a ground receiving station, and performs delay parameter estimation at the ground receiving station, so as to implement target source positioning.
In fig. 2, three satellites are a main satellite Sat0 and auxiliary satellites Sat1 and Sat2 respectively, echo data S1, S2 and S3 of the three satellites are collected, time delays from signals to the main satellite and the auxiliary satellite are estimated, and two groups of time difference TDOA are calculated by using intercepted three paths of target echo signals. Taking the time difference estimation of the echo data of the main star Sat0 and the auxiliary star Sat1 as an example, the target source positioning process of the application is described in detail.
S200, the FPGA sequentially performs preprocessing and mixed product operation on the segmented data to obtain mixed product data, and performs truncation rearrangement on the mixed product data; packaging and transmitting the truncated and rearranged mixed product data to a first DSP;
noteworthy are: the segmented data of the three satellites are preprocessed to become two paths of data, the two paths of data are buffered through the FIFO, and the FIFO is buffered and input into the data between the two auxiliary satellites and the main satellite respectively.
S300, the first DSP performs fixed-point to floating-point conversion operation on the received mixed product data to obtain floating-point data, and performs FFT processing on the floating-point data synchronously and parallelly through a plurality of cores of the first DSP to obtain a CAF matrix;
s400, the first DSP determines a coarse estimated value of time delay and a coarse estimated value of Doppler frequency shift through peak search in a two-dimensional plane formed by the CAF matrix, and determines a precise estimated value of time delay and a precise estimated value of Doppler frequency shift through second-order surface fitting; transmitting the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to a second DSP;
s500, the second DSP performs positioning calculation according to the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to obtain the three-dimensional coordinates of the target, and uploads the three-dimensional coordinates of the target to the upper computer.
FIG. 3 is a block diagram of the satellite-borne passive positioning algorithm of the application, wherein the FPGA sequentially collects, pre-processes, mixed product operation and truncates and rearranges three paths of parallel data. And then, transmitting the truncated and rearranged mixed product data to the DSP1 through SRIO for peak value searching and second order surface fitting, so as to realize time difference estimation, transmitting the result processed by the algorithm to the DSP2 by the DSP1 for positioning and resolving to obtain the three-dimensional coordinates of the target, transmitting the processing result of the algorithm to an upper computer through Ethernet after positioning and resolving, and carrying out feedback display by the upper computer.
The application provides a satellite-borne passive positioning method based on a multi-core heterogeneous architecture, which is applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture. The application fully utilizes the advantages of hardware, the FPGA realizes three paths of parallel data acquisition, preprocessing and mixed product operation in a pipeline mode, and adopts a double-DSP architecture for the operation process, and 8-core parallel time-frequency difference estimation calculation greatly shortens the calculation time so as to meet the requirements of algorithm realization on DSP processing capacity. In addition, the application improves the parameter estimation precision through the time-frequency difference coarse value estimation and the second-order curved surface fitting to realize the frequency difference estimation when the signal is high-precision and quick, has lower calculation complexity and can fully save calculation resources. The method has the advantages of low hardware cost and short algorithm time consumption, and can meet the requirement of real-time processing and improve the precision of parameter estimation at the same time, thereby realizing the passive target positioning more efficiently and accurately.
In a specific embodiment of the present application, S100 includes:
s110, the FPGA divides the time difference searching range into time sequencesHObtaining each search sub-range by the segment;
s120, the FPGA acquires echo data of three satellites in each search sub-range to obtain segmented data.
The application divides the time difference searching range intoHAnd a segment for receiving two paths of data in parallel. For the segment data, the algorithm processing flow is basically consistent, and the application selects the first segment data in all segment dataHThe segment data sets forth the processing flow of the time-frequency difference estimation algorithm.
In a specific embodiment of the present application, S200 includes:
s210, enabling the two paths of FIFO and the selector module by the FPGA through an enabling signal to enable the two paths of FIFO and the selector module to work, and enabling the selector module to select input data through a selecting signal;
when the FPGA collects data, the input of pre-delay data is realized through the write-enabling of the design selector module and the FIFO. For a priori informationHS2 path of each segment in the segment data is pre-delayed, and the pre-delayed S2 path is pre-delayedHThe segment data is buffered through the FIFO, and the two paths of the FIFO respectively receive the segment data of the S1 path and the S2 path.
When the rising edge of the enabling signal comes, the write enabling of the two paths of FIFOs is pulled up, the two paths of FIFOs can write data, and the selector module starts to work; when the write enable of the two-way FIFO is high and the select signal of the selector module is low, the FPGA writes a 0 into the second-way FIFO.
The FIFO receive data module refers to fig. 4, two paths of signals of the segment data are respectively input from s1_data and s2_data, that is, the S1 path of signals are directly connected to the S1 path of FIFOs, the S2 path of signals are firstly input through the selector module, and the output is connected to the S2 path of FIFOs.
The enabling signal is also used for enabling a counter, and the counter is used for counting 0 written into the second-path FIFO to obtain a counting result when the rising edge of the enabling signal arrives and the selection signal is low; the counting is ended when the rising edge of the selection signal is detected, and the segmented data is written to the second FIFO in turn.
The s1_valid signal is used as a write enable signal of the two-way FIFO and an enable signal of the S2-way selector module, and the s2_valid signal is used as a selection signal of the S2-way selector module to select data written into the S2-way FIFO. When the rising edge of the valid signal of the S1 path is detected to arrive, the write enable of the two paths of FIFOs is pulled high, the FIFOs of the S1 path and the FIFOs of the S2 path are enabled, the FIFOs execute write operation, meanwhile, the valid signal is also used as a mark for starting the work of the counter, and the counter starts counting when the rising edge of the valid signal arrives. When the valid signal of the S1 path is high and the valid signal of the S2 path is low, writing 0 into the FIFO of the S2 path, and obtaining the first path according to the delay relationship on the assumption that the clock period is tclkHThe number of FIFO writes 0 for the second path S2 within the segment search sub-range is:
；
wherein,,representing clock period +.>Indicate->Delay length of segment data, < >>Represent the firstHDelay length of the segment data.
S220, when the FPGA works in two paths of FIFO, the segmented data of the main satellite are cached in a first path of FIFO, and under the combined action of the selection signal and the enabling signal, the segmented data of the remaining two auxiliary satellites are cached in a second path of FIFO;
s230, overlapping data are selected from the two paths of FIFO, and the overlapping data are divided into M sections to obtain M sections of sub data;
s240, selecting a plurality of processing points in the sub-data, and carrying out mixed product processing on the sub-data at each processing point to obtain a mixed product processing result;
when the rising edge of the valid signal of the S2 way is detected, the counting ends. Meanwhile, the data written in the FIFO of the S2 path is switched from 0 to the effective data received by the S2 path. When the valid signal of the S1 path is pulled down, write enabling of FIFOs of the S1 path and the S2 path is simultaneously pulled down, and data buffering is completed. Each segment of data has equal length, so that the follow-up is convenientDivision of segments. And (3) after the S2 path is delayed, taking the overlapped part of the S1 path and the S2 path to perform subsequent data preprocessing. Dividing the two paths of received data into +.>Segments, each segment having a data length +.>Selecting +.>Point (S)>Representing a preset value greater than 0, +.>A preset value greater than 0.
S250, cutting and rearranging the mixed product processing result, and packaging the cut and rearranged result to obtain packaged data;
according to the application, the frequency spectrum of each section of mixed product data in the mixed product processing result is shifted, so that the left half part and the right half part are exchanged to complete cut-off rearrangement.
And S260, transmitting the packed data and coordinates of the three satellites to the first DSP.
The application packages the satellite coordinates required by the DSP1 and the data processed by each small packet, and transmits the data to a section of continuous storage space in DDR SRAM (Double Data Rate Static Random-Access Memory) of the DSP1 through a high-speed serial link RapidIO.
In a specific embodiment of the present application, S240 includes:
s241, selecting a plurality of processing points in the sub-data;
s242, FFT processing, complex multiplication processing and IFFT processing are sequentially carried out on the sub-data at each processing point to obtain a mixed product processing result.
Referring to fig. 5, the two paths of data after the FPGA preprocessing are subjected to a mixed product processing, and the purpose of the mixed product processing is to convert the time domain convolution into spectral multiplication. The mixed product processing is FFT processing, complex multiplication processing, IFFT processing in this order. The treatment is completed to obtain:
；
wherein,,regarding the processed data as dimension size of +.>Is>Points representing each set of frequency domain dimension data, +.>Is a discrete time delay parameter.
In a specific embodiment of the present application, S300 includes:
s310, the first DSP performs matrix transposition rearrangement on the received mixed product data to obtain transposed rearranged data;
s320, the first DSP sequentially transmits transposed rearranged data to the second-level SRAM through DMA (Direct Memory Access ) according to the sequence of the distance dimension;
the DSP1 in the application performs matrix transposition rearrangement on mixed product data transmitted by the FPGA pulse by pulse, and sequentially transmits the data to the two-stage SRAM through DMA according to the sequence of distance dimension to finish fixed point-to-floating point operation of the data.
S330, the two-stage SRAM performs fixed-point to floating point operation on the transposed rearranged data to obtain floating point data;
s340, the first DSP distributes floating point data to each kernel according to the frequency domain dimension, and the distributed part of floating point data is subjected to FFT processing by each kernel to obtain FFT data.
In order to save the overhead in code time, floating point data is completed by a calculation module, which performs synchronous operation in 8 cores, and equally divides the data into 8 parts to each core according to the frequency domain dimension. FFT processing is carried out on floating point data, and the specific implementation formula is as follows:
；
wherein,,for time resolution, +.>For frequency resolution, +.>Is a discrete time delay parameter->Is a discrete frequency shift parameter.
As a specific embodiment of the present application, S400 includes:
s410, a first DSP determines a rough estimation value of time delay and a rough estimation value of Doppler frequency shift through peak search in a two-dimensional plane formed by a CAF matrix;
searching for peaks in a two-dimensional plane, determining coarse estimates of delay and doppler shift, expressed as:
；
s420, the first DSP determines the accurate estimated value of the time delay and the accurate estimated value of the Doppler frequency shift by adopting a second-order surface fitting method on the rough estimated value of the time delay and the rough estimated value of the Doppler frequency shift;
the DSP1 adopts a second order surface fitting method to determine accurate estimated values of time delay and Doppler frequency shift. The quadric equation is as follows:
；
wherein,,for the coefficients to be determined, eight points around the peak are recorded for determining the coefficients. The coefficients +.>The least square solution of (2) and the peak coordinate can be obtained through a quadric equation to satisfy the following conditions:
；
；
the offset of the time-frequency difference fine estimation result compared with the original peak value can be obtained by solving the equation:
；
；
wherein,,indicating the offset of the frequency difference +.>Representing the time difference offset.
The accurate estimated value of the time delay and the accurate estimated value of the Doppler frequency shift are respectively:
；
；
namely, the delay estimation Tdoa1 of the echo signals received by the main star Sat0 and the auxiliary star Sat1 is +.>The offset is the offset of the frequency difference of the echo signals received by the main star Sat0 and the auxiliary star Sat 1. And the same estimation is carried out on the S1 path and the S3 path, so that the delay estimation Tdoa2 and the frequency offset of the echo signals received by the main star Sat0 and the auxiliary star Sat2 can be obtained, and the estimation of the two groups of time differences is realized in parallel in the DSP 1.
And S430, transmitting the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to a second DSP.
The application transmits the coordinate parameters of two groups of time differences and three satellites to the DSP2 for positioning and resolving, solves the three-dimensional coordinates of the target, and transmits the final result back to the upper computer for display.
Noteworthy are: the accurate estimated value of the time delay and the accurate estimated value of the Doppler frequency shift are two groups, and the settlement process is completed by the DSP2. The positioning solution of the target source is performed under the ECEF system, and the coordinates of three satellites are firstly converted from the geodetic coordinate system to rectangular coordinates of the ECEF system. And then calculating the initial value of the coordinates of the target, namely determining two space hyperboloids by using two sets of time difference information, intersecting the two space hyperboloids in a line in space, and solving the intersection point of the line and the ground to obtain the position information of the target source. And finally, further improving the positioning accuracy by using an LM iterative algorithm, and outputting the optimal estimated value of the target source coordinate. And transmitting the target positioning result back to the upper computer through the Ethernet.
The application provides a multi-core heterogeneous architecture-based satellite-borne passive positioning device, wherein a signal processing module is arranged in the multi-core heterogeneous architecture-based satellite-borne passive positioning device and is used for realizing a multi-core heterogeneous architecture-based satellite-borne passive positioning method.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.
Claims (9)
1. The satellite-borne passive positioning method based on the multi-core heterogeneous architecture is characterized by being applied to a signal processing module, wherein the signal processing module adopts an FPGA+double DSP architecture, and the satellite-borne passive positioning method based on the multi-core heterogeneous architecture comprises the following steps:
s100, acquiring echo data of three satellites by an FPGA, and segmenting the echo data in a time difference searching range to obtain segmented data;
s200, the FPGA sequentially performs preprocessing and mixed product operation on the segmented data to obtain mixed product data, and the mixed product data is truncated and rearranged; packaging and transmitting the truncated and rearranged mixed product data to a first DSP;
s300, the first DSP performs fixed point to floating point conversion operation on the received mixed product data to obtain floating point data, and performs FFT processing on the floating point data synchronously and parallelly through a plurality of cores of the first DSP to obtain a CAF matrix;
s400, the first DSP determines a rough estimated value of time delay and a rough estimated value of Doppler frequency shift through peak search in a two-dimensional plane formed by the CAF matrix, and determines a precise estimated value of time delay and a precise estimated value of Doppler frequency shift through second-order surface fitting; transmitting the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and coordinates of three satellites to a second DSP;
s500, the second DSP performs positioning calculation according to the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and the coordinates of the three satellites to obtain three-dimensional coordinates of a target, and uploads the three-dimensional coordinates of the target to an upper computer;
s300 includes:
s310, the first DSP performs matrix transposition rearrangement on the received mixed product data to obtain transposed rearranged data;
s320, the first DSP sequentially transmits the transposed rearranged data to a secondary SRAM through DMA according to the sequence of distance dimension;
s330, the second-level SRAM performs fixed-point to floating-point operation on the transposed rearranged data to obtain floating-point data;
and S340, the first DSP distributes the floating point data to each kernel of the first DSP according to the frequency domain dimension, and the distributed partial data of each kernel is subjected to FFT processing to obtain a CAF matrix.
2. The method for positioning satellite borne passive based on multi-core heterogeneous architecture according to claim 1, wherein S100 comprises:
s110, dividing the time difference searching range into H sections according to the time sequence by the FPGA to obtain each searching sub-range;
and S120, the FPGA acquires echo data of three satellites in each search sub-range to obtain segmented data.
3. The method for positioning on-board passive positioning based on multi-core heterogeneous architecture of claim 2, wherein S200 comprises:
s210, enabling two paths of FIFO and a selector module by the FPGA through an enabling signal to enable the two paths of FIFO and the selector module to work, and enabling the selector module to select input data through a selecting signal;
s220, when the FPGA works in two paths of FIFO, the FPGA caches the segmented data of the main satellite to the first path of FIFO, and under the combined action of the selection signal and the enabling signal, the segmented data of the remaining two auxiliary satellites are cached to the second path of FIFO;
s230, overlapping data are selected from the two paths of FIFO, and the overlapping data are divided into M sections to obtain M sections of sub data;
s240, selecting a plurality of processing points in the sub-data, and performing mixed product processing on the sub-data at each processing point to obtain a mixed product processing result;
s250, cutting and rearranging the mixed product processing result, and packaging the cut and rearranged result to obtain packaged data;
and S260, transmitting the packed data and coordinates of the three satellites to a first DSP.
4. The method for positioning the satellite-borne system based on the multi-core heterogeneous architecture according to claim 3, wherein when the rising edge of the enabling signal arrives, the write enabling of the two paths of FIFOs is pulled up, the two paths of FIFOs can both write data, and the selector module starts to work; when the write enable of the two-way FIFO is high and the select signal of the selector module is low, the FPGA writes a 0 into the second-way FIFO.
5. The method for positioning a satellite-borne system based on a heterogeneous multi-core architecture according to claim 3, wherein the enable signal is further used for enabling a counter, and the counter is used for counting 0 written into a second FIFO when a rising edge of the enable signal arrives and the selection signal is low to obtain a count result; the counting is ended when the rising edge of the selection signal is detected to come, and the segment data is written into the second path FIFO in turn.
6. The space-borne passive positioning method based on the multi-core heterogeneous architecture according to claim 5, wherein the number of the second path of FIFO write-in 0 in the H-th segment search sub-range is as follows:
wherein t is clk Representing clock period, t H-1 Representing the delay length of the H-1 segment data, t H Representing the delay length of the H-th segment of data.
7. The method for satellite-borne passive positioning based on multi-core heterogeneous architecture of claim 3, wherein S240 comprises:
s241, selecting a plurality of processing points in the sub-data;
s242, FFT processing, complex multiplication processing and IFFT processing are sequentially carried out on the sub-data at each processing point to obtain a mixed product processing result.
8. The method for positioning on-board passive positioning based on multi-core heterogeneous architecture of claim 1, wherein S400 comprises:
s410, the first DSP determines a rough estimated value of time delay and a rough estimated value of Doppler frequency shift through peak search in a two-dimensional plane formed by the CAF matrix;
s420, the first DSP determines a precise estimated value of the time delay and a precise estimated value of the Doppler frequency shift by adopting a second-order surface fitting method on the rough estimated value of the time delay and the rough estimated value of the Doppler frequency shift;
and S430, transmitting the accurate estimated value of the time delay, the accurate estimated value of the Doppler frequency shift and coordinates of three satellites to a second DSP.
9. The spaceborne passive positioning device based on the multi-core heterogeneous architecture is characterized in that a signal processing module is arranged inside the spaceborne passive positioning device based on the multi-core heterogeneous architecture and is used for realizing the spaceborne passive positioning method based on the multi-core heterogeneous architecture as claimed in any one of claims 1 to 8.
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