CN116707521A - 8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end - Google Patents
8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end Download PDFInfo
- Publication number
- CN116707521A CN116707521A CN202310712731.8A CN202310712731A CN116707521A CN 116707521 A CN116707521 A CN 116707521A CN 202310712731 A CN202310712731 A CN 202310712731A CN 116707521 A CN116707521 A CN 116707521A
- Authority
- CN
- China
- Prior art keywords
- data
- phase
- signal
- sampling
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011084 recovery Methods 0.000 title abstract description 16
- 238000005070 sampling Methods 0.000 claims abstract description 85
- 238000012795 verification Methods 0.000 claims description 17
- 238000013139 quantization Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 abstract description 3
- 238000004891 communication Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 3
- 238000004422 calculation algorithm Methods 0.000 description 3
- 101150071746 Pbsn gene Proteins 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012300 Sequence Analysis Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Nonlinear Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a clock data recovery key circuit system for a receiving end of an 8.1Gbps eDP high-speed display interface, which belongs to the field of high-speed communication, and synchronizes an 8.1Gbps input signal into parallel data through a sampling synchronization module. The phase detector and the majority voter then perform a phase comparison of the parallel data and the sampling clock to produce a phase error signal. The phase error signal is filtered by a digital filter and a data shaper to remove high frequency noise jitter, and finally a phase adjustment signal is formed in a phase accumulator. The phase adjustment signal is transmitted to the phase interpolation module, and the phase of the sampling clock is adjusted, so that the closed loop of the system is realized. In the system structure, the phase discriminator has a simple structure and lower power consumption and area, and meanwhile, the data shaper can improve the data precision, effectively inhibit system oscillation and increase the robustness of the system.
Description
Technical Field
The invention relates to the technical field of high-speed communication, in particular to a key circuit system for clock data recovery of a receiving end of an 8.1Gbps eDP high-speed display interface.
Background
Along with the increasing requirement of ultra-high definition video display technology on data transmission rate, the display requirement of a high definition panel cannot be met by a traditional data interface. The Video Electronics Standards Association (VESA) has therefore established a new embedded display interface (eDP) specification, the architecture of which comprises 4 main transmission channels, each channel having a transmission rate up to 8.1Gbps, and a total data effective rate up to 25.92Gbps.
Although the eDP display interface specification increases the data transmission rate, in a high frequency data transmission scenario, the rising edge time of the signal is shortened and the amplitude is reduced, resulting in the signal high frequency effect being dominant. Thus, there is a need to employ Serdes high-speed link design techniques to address the signal integrity challenges faced by high-speed eDP interfaces. In a long-distance transmission scenario, in order to further reduce the common influence of environmental noise such as channel crosstalk, PVT, etc. on a clock signal and a data signal, a serial asynchronous architecture is mainly used for a high-speed link.
The serial asynchronous architecture has advantages of not considering synchronicity between parallel data, and low complexity compared to the parallel synchronous architecture. However, the serial asynchronous architecture has only a single data channel, no independent clock channel, and the data signal and the clock signal are transmitted together at the time of transmission. Because of the lack of clock information for the data, the receiving end needs a clock data recovery Circuit (CDR) to recover the clock from the received signal and reconstruct the original data stream.
Since the eDP protocol is designed for the display environment of the embedded battery, the power consumption is lower than that of other interfaces, which puts low power consumption design requirements on the CDR. At the same time, the protocol standard requires higher noise margin and frequency offset margin, and under the above technical challenges, the circuit system needs to be redesigned by combining the protocol standard to solve the above problems.
Disclosure of Invention
The invention provides a clock data recovery key circuit system for a receiving end of an 8.1Gbps eDP high-speed display interface, which is applicable to various index requirements of an eDP 1.5 version protocol. The system circuit is provided with the phase discriminator with small area and low power consumption, and is more suitable for the eDP protocol interface with low power consumption. Meanwhile, a data shaper in the system can improve data precision, quickly inhibit system oscillation, increase system robustness and shorten system locking time.
The embodiment of the invention provides a key circuit system for recovering clock data of a receiving end of an 8.1Gbps eDP high-speed display interface, which comprises the following components: the input end of the sampling synchronization module is connected with the input serial signal and is used for synchronizing the input signal of 8.1Gbps into parallel data;
the input end of the phase discriminator is connected with the output end of the sampling synchronization module and is used for judging the phase relation between a sampling clock and data bits according to the parallel data and outputting a plurality of leading and lagging signals for adjusting the phase of the sampling clock according to the phase relation;
the input end of the majority voter is connected with the output end of the phase discriminator and is used for judging a plurality of leading and lagging signal samples generated by the phase discriminator and outputting a phase error signal;
the input end of the digital filter is connected with the output end of the majority voter, and is used for carrying out proportion and integral operation on the phase error signal output by the majority voter, and finally adding the proportion path data and the integral path data to obtain output data of the digital filter;
the input end of the data shaper is connected with the output end of the digital filter and is used for compressing output data of the digital filter, reducing jump amplitude of the numerical value of the output data, converting amplitude information into duty ratio information, shaping quantization noise through a high-pass filter and filtering a low-frequency part;
the input end of the phase accumulator is connected with the output end of the data shaper, and the output end of the phase accumulator is connected with the input end of the phase interpolation module and is used for recording information after phase adjustment according to the output data of the data shaper and outputting a phase adjustment signal with corresponding data bit width according to the precision of the phase interpolation module;
the output end of the phase interpolation module is connected with the other input end of the sampling synchronization module and is used for adjusting the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal;
and the input end of the verification module is connected with the other output end of the sampling synchronization module, and the output end outputs a verification signal and output data, and is used for verifying the output data of the sampling synchronization module, determining whether the system is in self-adaptive convergence or not, and verifying the bit error rate index according to the verification signal.
Optionally, in an embodiment of the present invention, the sampling synchronization module is further configured to collect the synchronous edge bit information and the data bit information respectively using two edge sampling clocks and two data sampling clocks using a 1/2 rate oversampling scheme.
Optionally, in one embodiment of the present invention, the phase detector decides a decision formula of a phase relationship between a sampling clock and a data bit according to the parallel data, as follows:
wherein E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock,representing an exclusive-or operation, the phase detector performs a logic operation on a group of adjacent data bit information and edge bit information, and outputs "leading" and "lagging" information of the sampling clock phase.
Optionally, in an embodiment of the present invention, the decision calculation formula of the majority voter is:
wherein up i Indicating that the i-th bit data phase is discriminated as a lead signal,dn i indicating that the ith data phase is a lag signal, up sig Representing the number of leading signals in k sets of data as greater than the number of lagging signals, dn sig The up_dn is the output value of the majority voter, the first stage of the majority voter counts the number of k advance signals and the number of k retard signals respectively, the second stage compares the numbers of the two signals, if the number of the advance signals in the k groups of data is greater than the number of the retard signals, the majority voter outputs an advance signal, otherwise, outputs a retard signal, and if the number of the advance signals is greater than the number of the retard signals, the majority voter outputs no action signal, which means that no phase adjustment is performed.
Optionally, in an embodiment of the present invention, the digital filter is further configured to operate output data of the majority voter through a proportional path and an integral path, where the proportional path shifts data to the left with a symbol, and implements power amplification of 2; and the integrating path sums the data in each clock period, carries out signed bit right shift on the summed data, realizes power reduction of 2, and carries out addition operation of signed numbers on the proportional path data and the integrating path data to obtain the output data of the digital filter.
Optionally, in an embodiment of the present invention, the phase interpolation module provides four-phase sampling clocks, the sampling clock period is one half of the serial data period, and two phases of the four-phase sampling clocks are different by a fixed n/2 phase.
Optionally, in an embodiment of the present invention, the verification module is further configured to take the continuous 32-bit serial data at the input end, sequentially fill the serial data into the 0-31-bit registers after 32 clocks, and verify the current circuit 1+x 28 +X 31 Generating the subsequent correct data, performing exclusive-or processing on the generated data and the sampled data, observing an exclusive-or result, determining whether the current sampled data is correct or not, and X is the nth bit of the shift register.
The 8.1Gbps eDP-oriented high-speed display interface receiving end clock data recovery key circuit system provided by the embodiment of the invention has the following beneficial effects:
1. the phase detector has lower power consumption and area.
2. And a data shaper is introduced to change the output data structure of the digital filter, compress the amplitude and improve the accuracy of the output data of the digital filter.
3. In the circuit implementation stage, a design method is optimized aiming at the problem of large loop delay of a system so as to improve the frequency difference tolerance of the CDR.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a key circuit system for clock data recovery at a receiving end of an 8.1Gbps eDP-oriented high-speed display interface according to an embodiment of the invention;
FIG. 2 is a hardware block diagram of a key circuit system for clock data recovery of a receiving end of an 8.1Gbps eDP-oriented high-speed display interface according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an implementation process of a clock data recovery key circuit system for a receiving end of an 8.1Gbps eDP high-speed display interface according to an embodiment of the invention;
FIG. 4 is a four-phase sampling clock schematic diagram of a sampling synchronization module according to an embodiment of the present invention;
FIG. 5 is an equivalent circuit diagram of a data shaper according to an embodiment of the present invention;
FIG. 6 is a flowchart of the operation of a phase accumulator according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a phase interpolator generating a four phase sampling clock according to an embodiment of the present invention;
fig. 8 is a chart of noise margin performance tests according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Fig. 1 is a schematic diagram of a clock data recovery key circuit system for a receiving end of an eDP high-speed display interface with 8.1Gbps according to an embodiment of the present invention.
As shown in fig. 1, the clock data recovery key circuit system for the receiving end of the 8.1Gbps eDP high-speed display interface includes: an oversampling synchronization module 100, a phase detector 200, a majority voter 300, a digital filter 400, a data shaper 500, a phase accumulator 600, a phase interpolation module 700, and a verification module 800.
The input end of the sampling synchronization module 100 is connected with an input serial signal and is used for synchronizing the input signal of 8.1Gbps into parallel data;
an input end of the phase discriminator 200 is connected with an output end of the sampling synchronization module 100, and is used for judging a phase relation between a sampling clock and data bits according to parallel data and outputting a plurality of leading and lagging signals for adjusting the phase of the sampling clock according to the phase relation;
the input end of the majority voter 300 is connected with the output end of the phase discriminator 200, and is used for judging a plurality of leading and lagging signal samples generated by the phase discriminator and outputting a phase error signal;
the input end of the digital filter 400 is connected with the output end of the majority voter 300, and is used for performing proportion and integral operation on the phase error signal output by the majority voter, and finally adding the proportion path data and the integral path data to obtain output data of the digital filter;
the input end of the data shaper 500 is connected with the output end of the digital filter 400, and is used for compressing the output data of the digital filter, reducing the jump amplitude of the output data value, converting the amplitude information into duty ratio information, shaping quantization noise through a high-pass filter, and filtering out the low-frequency part;
the input end of the phase accumulator 600 is connected with the output end of the data shaper 500, the output end is connected with the input end of the phase interpolation module 700, and is used for recording the information after phase adjustment according to the output data of the data shaper and outputting a phase adjustment signal with corresponding data bit width according to the precision of the phase interpolation module;
the output end of the phase interpolation module 700 is connected with the other input end of the sampling synchronization module 100, and is used for adjusting the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal;
the input end of the verification module 800 is connected to the other output end of the sampling synchronization module 100, and the output end outputs a verification signal and output data, which are used for verifying the output data of the sampling synchronization module 100, determining whether the system is adaptive to convergence, and verifying the bit error rate index according to the verification signal.
Based on the modules, synchronizing an input signal with the speed of 8.1Gbps into parallel data through a sampling synchronization module; the phase discriminator judges the phase relation between the sampling clock and the data bit according to the parallel data, and outputs 'lead' and 'lag' signals for adjusting the phase of the sampling clock according to the phase relation; the majority voter combines a plurality of 'leading' and 'lagging' signal samples generated by the phase discriminator to output a result with larger confidence; the digital filter performs proportion and integral operation on the output of the majority voter, and proportion path data and integral path data are finally added to obtain output data of the digital filter; the data shaper compresses the data output by the digital filter, reduces the jump amplitude of the value of the data, converts the amplitude information into duty ratio information, shapes quantization noise through the high-pass filter, and filters out the low-frequency part; the phase accumulator continuously accumulates the output data of the data shaper, records the information after phase adjustment, and outputs a phase adjustment signal with corresponding data bit width according to the precision of the phase interpolation module; and the phase difference value module adjusts the phase of the sampling clock according to the phase adjustment signal, tracks the change of the data of the receiving end and finally realizes the correct acquisition of the data of the receiving end. The verification module completes the verification of the data output by the sampling synchronization module to indicate whether the current system is in a stable working state or not in self-adaptive convergence. And meanwhile, according to the output signal of the verification module, the error rate index can be verified.
In an embodiment of the present invention, the sampling synchronization module 100 employs a 1/2 rate oversampling scheme using two edge sampling clocks and two data sampling clocks to respectively acquire synchronous edge bit information and data bit information.
In an embodiment of the present invention, the phase detector decides the phase relationship between the sampling clock and the data bit according to parallel data as follows:
wherein E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock,representing exclusive or operation, the phase detector performs logic operation on a group of adjacent data bit information and edge bit information, and outputs 'leading' and 'lagging' information of the sampling clock phase.
In the embodiment of the invention, the decision calculation formula of the majority voter is as follows:
wherein up i Representing the phase discrimination of the ith bit data as a lead signal, dn i Indicating that the ith data phase is a lag signal, up sig Representing the number of leading signals in k sets of data as greater than the number of lagging signals, dn sig Indicating that the number of lag signals in k groups of data is more than the number of lead signals, up_dn is the output value of a majority voter, wherein the first stage of the majority voter respectively counts the number of k lead signals and the number of lag signals, the second stage compares the numbers of the two signals, and if the number of lead signals in k groups of data is more than the number of lag signals, the majority voter outputs a lead signal, otherwise,then a lag signal is output and when the number of lead signals is greater than the number of lag signals by equal, the majority voter outputs a no-action signal, representing no phase adjustment.
In the embodiment of the present invention, as shown in fig. 2, the digital filter 400 is further configured to operate output data of the majority voter through a proportional path and an integral path, where the proportional path shifts the data to the left with a symbol, so as to achieve power amplification of 2; and the integrating path sums the data in each clock period, carries out signed bit right shift on the summed data, realizes power reduction of 2, and carries out addition operation of signed numbers on the proportional path data and the integrating path data to obtain output data of the digital filter.
The specific calculation process of the digital filter 400 is: and adding the X signal with m bits and the fed-back m-bit signal to obtain an m+1-bit quantizer input signal V, and taking the Most Significant Bit (MSB) of the quantizer input signal V to finish a 1-bit quantization process. The remaining m-bit signal, representing the negative value of the quantization error signal, is stored in a register of bit width m and added to the m-bit input signal X in the next clock cycle. The digital filter alters the digital filter output data structure, compressing the amplitude. On the premise of not losing data information, the amplitude of the phase adjustment signal is reduced, and the accuracy of the output data of the digital filter is improved.
In an embodiment of the present invention, the phase interpolation module 700 provides four phase sampling clocks, the sampling clock period is one half of the serial data period, and the four phase sampling clocks are different by a fixed pi/2 phase.
In the embodiment of the present invention, the verification module 800 is further configured to take the continuous 32-bit serial data at the input end, sequentially fill the serial data into the 0-31-bit registers after 32 clocks, and verify the current 1+X circuit 28 +X 31 Generating the subsequent correct data, performing exclusive-or processing on the generated data and the sampled data, observing an exclusive-or result, determining whether the current sampled data is correct or not, and X represents the nth bit of the shift register.
Specifically, from 1+X 28 +X 31 The PRBS signal generation principle of the code pattern is known, and the outputThe exclusive or result of the 28 th bit and the 31 st bit is used as the input of the 0 th bit register, and the generation of the subsequent data flow is based on the data stored in the 0-31 th bit register because the PRBS generating circuit has a cyclic structure. Therefore, the principle of the verification circuit is obvious, namely, as long as continuous 32-bit data which is generated logically and correctly is taken in the generated cyclic data, the continuous 32-bit data is sequentially filled into 0-31-bit registers after 32 clocks, and the current circuit can generate subsequent correct data. And performing exclusive-or processing on the generated data and the sampling data, and observing an exclusive-or result to obtain whether the current sampling data is correct or not.
In the circuit implementation stage, the critical path is analyzed, and each part comprises a summing circuit, so that the structure of register beat register data appears in the summing circuit, namely, the path from the register of the digital filter to the register of the phase accumulating circuit is called the critical path. And (3) carrying out time sequence analysis on the establishment time and the maintenance time of the critical path, and placing summation logic of the data shaper on a feedback branch after comprehensively considering algorithm performance and the rationality of time sequence so as to obtain maximum index improvement.
The working principle of the method of the invention is as follows: the sampling synchronization module collects serial data of 8.1Gbps through a four-phase sampling clock, is divided into two types of data bit information and edge bit information, and is respectively synchronized into parallel data. The phase detector generates phase error signals "lead" and "lag" by performing a logical operation on the data bit information and the edge bit information. The majority voter compresses the parallel phase error signals and selects the result with the highest confidence and outputs the result. And then, the digital filter and the data shaper carry out low-pass filtering on the output data of the majority voter, shape and filter high-frequency noise, and realize the study and accumulation of frequency difference. And finally, forming a phase adjustment signal in the phase accumulator, transmitting the phase adjustment signal to a phase interpolation module, and adjusting the phase of a sampling clock to realize the closed loop of the system. The circuit system has the self-adaptive adjustment function, even if the phase of the sampling clock is not at ideal time in the initial stage of system starting, the system gradually converges and tends to be stable under the self-adaptive adjustment of the circuit system, and the phase of the sampling clock gradually tends to be at the position with the largest open signal eye diagram, namely at the position with the lowest signal error rate.
The key circuit system for clock data recovery is applied to an 8.1Gbps eDP high-speed display interface, and the algorithm flow is shown in FIG. 3 and comprises the following steps:
(1) The sampling synchronization module samples the input 8.1Gbps serial data using four phase and each phase different fixed pi/2 phase sampling clocks, as shown in fig. 4. Within one period, two data bit information and two edge bit information may be sampled. However, in order to reduce the operating frequency of the core circuit, the data is again shaped to be synchronized into 9-bit edge bit information and 8-bit data bit information, respectively. The edge bit information is one bit more than the data bit information, and the meaning is that whether the jump edge appears between the adjacent bits can be obtained through exclusive OR logic, and the judgment of the phase information is only carried out when the jump edge information exists.
(2) The phase detector carries out logic operation on 9-bit edge bit information and 8-bit data bit information, and the decision relation between every two bits of data is shown as a formula (1).
Two sets of 8-bit wide information representing the phase "lead" and "lag" are obtained, respectively, each bit representing the relationship between the current bit and the sampling clock phase.
(3) At this time, the majority voter is also designed to be 8-bit wide, and the number of two sets of "leading" and "lagging" information of 8-bit wide are counted respectively, and after passing through the comparator, the information with the largest number is output, and the information represents the final phase error relation.
(4) After the digital filter receives the signal output by the majority voter, the signal is processed by a proportional path and an integral path, wherein the proportional path amplifies data by 8 times through a signed left shift operation, and the integral path reduces data by 32 times through a signed right shift operation. Signed shift operations fall into two cases: when the positive number is operated, the shift can be directly carried out, and when the negative number is operated, the bit expansion is needed, then the shift operation is carried out after the complement is taken, and finally the complement is taken again for the shifted data, so that the negative number after the operation is obtained. The integrating path accumulates the data after operation once every clock cycle and stores the data in a register file, and can continuously provide frequency difference components to promote phase adjustment. The addition of the data of the proportional and integral paths may result in the final output of the digital filter.
(5) The threshold of the data shaper is designed to be 1/16, and the bit width of the data shaper is 4 bits in the circuit design level, so that only data higher than 4 bits in the final output result of the digital filter is needed to be intercepted as the output result, and the remaining lower 4 bits continue to participate in the operation of the accumulation circuit in the data shaper, as shown in fig. 5. X n is the input data of the data shaper, Y n is the output data, and m is 4 in the present invention.
(6) The phase accumulator is designed to be 1/64 according to the accuracy of the phase interpolation module, so that the output data range of the phase accumulator is 0-63, the working flow of the phase accumulator is shown in fig. 6 aiming at the positive and negative values of the phase adjustment information, when the frequency difference exists, the phase adjustment information is continuously adjusted to one direction, and when the phase adjustment information is positive, the output value of the phase accumulator is increased from 0 to the maximum value 64, and is updated to 0. If the phase adjustment information is negative, the output value of the phase accumulator is updated to 63 when the output value decreases from 63 to the minimum value 0.
(7) When there is a forward frequency difference between the transmitting end and the receiving end, the output of the phase accumulator is regularly increased from 0 to the maximum value 63, the positive phase offset of clk_out and ref_clk reaches the maximum value 1UI (123 ps), and at this time, the clk_out clock is switched to ref_clk inversion, as shown in fig. 6. When negative frequency difference exists between the transmitting end and the receiving end, the output of the phase accumulator regularly decreases from 63 to a minimum value of 0, the negative phase offset of clk_out and ref_clk reaches a maximum value of 1UI (123 ps), the clk_out clock is switched to ref_clk phase inversion, and the four-phase sampling clock is generated by taking clk_out as a reference clock.
Based on the algorithm flow, the circuit forms a negative feedback system, and the self-adaptive adjustment can be realized after the system is started so as to track frequency difference and noise.
In order to verify the practical effect of the scheme provided by the present invention, theoretical analysis and circuit simulation experiments are performed on the system of the present invention, respectively, to obtain noise margin (JTOL) data as shown in FIG. 8. In fig. 8, the uppermost broken line is circuit simulation data, the middle curve is a theoretical analysis result, the lowermost broken line is 8.1Gbps eDP protocol standard, the circuit simulation data is similar to the theoretical analysis result, the rationality of the design is represented, and the circuit simulation data are higher than the protocol standard, and represent the effectiveness of the design.
Meanwhile, compared with two documents in recent years, the invention has certain advantages in terms of noise margin and frequency difference index. The literature A2.68mW/Gbps,1.62-8.1Gb/s Receiver for Embedded DisplayPort version1.4b to Support14dB Channel Loss, based on the 10nm process, has a noise margin of 0.45Uipp@10MHz and a frequency difference of 1500ppm. The literature of a clock data recovery circuit with self-adaptive adjustment of loop bandwidth is based on simulation test of a 55nm process, and the noise margin is 0.55UIpp@10MHz. The invention is based on the simulation test of the 40nm technology, 0.74UIpp@10MHz, and the frequency difference is 1800ppm. The details are shown in the following table.
In summary, the design method and the system for the clock data recovery key circuit of the receiving end of the 8.1Gbps eDP high-speed display interface provided by the invention have obvious advantages compared with the prior art.
The 8.1Gbps eDP-oriented high-speed display interface receiving end clock data recovery key circuit system of the embodiment of the invention synchronizes 8.1Gbps input signals into parallel data through the sampling synchronization module. The phase detector and the majority voter then perform a phase comparison of the parallel data and the sampling clock to produce a phase error signal. The phase error signal is filtered by a digital filter and a data shaper to remove high frequency noise jitter, and finally a phase adjustment signal is formed in a phase accumulator. The phase adjustment signal is transmitted to the phase interpolation module, and the phase of the sampling clock is adjusted, so that the closed loop of the system is realized. In the system structure, the phase discriminator has a simple structure and lower power consumption and area, and meanwhile, the data shaper can improve the data precision, effectively inhibit system oscillation and increase the robustness of the system.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Claims (7)
1. The key circuit system for recovering clock data of a receiving end of an 8.1Gbps eDP high-speed display interface is characterized by comprising:
the input end of the sampling synchronization module is connected with the input serial signal and is used for synchronizing the input signal of 8.1Gbps into parallel data;
the input end of the phase discriminator is connected with the output end of the sampling synchronization module and is used for judging the phase relation between a sampling clock and data bits according to the parallel data and outputting a plurality of leading and lagging signals for adjusting the phase of the sampling clock according to the phase relation;
the input end of the majority voter is connected with the output end of the phase discriminator and is used for judging a plurality of leading and lagging signal samples generated by the phase discriminator and outputting a phase error signal;
the input end of the digital filter is connected with the output end of the majority voter, and is used for carrying out proportion and integral operation on the phase error signal output by the majority voter, and finally adding the proportion path data and the integral path data to obtain output data of the digital filter;
the input end of the data shaper is connected with the output end of the digital filter and is used for compressing output data of the digital filter, reducing jump amplitude of the numerical value of the output data, converting amplitude information into duty ratio information, shaping quantization noise through a high-pass filter and filtering a low-frequency part;
the input end of the phase accumulator is connected with the output end of the data shaper, and the output end of the phase accumulator is connected with the input end of the phase interpolation module and is used for recording information after phase adjustment according to the output data of the data shaper and outputting a phase adjustment signal with corresponding data bit width according to the precision of the phase interpolation module;
the output end of the phase interpolation module is connected with the other input end of the sampling synchronization module and is used for adjusting the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal;
and the input end of the verification module is connected with the other output end of the sampling synchronization module, and the output end outputs a verification signal and output data, and is used for verifying the output data of the sampling synchronization module, determining whether the system is in self-adaptive convergence or not, and verifying the bit error rate index according to the verification signal.
2. The system of claim 1, wherein the sampling synchronization module is further configured to use a 1/2 rate oversampling scheme to acquire the synchronous edge bit information and the data bit information using two edge sampling clocks and two data sampling clocks, respectively.
3. The system of claim 1, wherein the phase detector determines a phase relationship between a sampling clock and a data bit based on the parallel data by a determination formula:
wherein E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock,representing an exclusive-or operation, the phase detector performs a logic operation on a group of adjacent data bit information and edge bit information, and outputs "leading" and "lagging" information of the sampling clock phase.
4. The system of claim 1, wherein the decision calculation formula of the majority voter is:
wherein up i Representing the phase discrimination of the ith bit data as a lead signal, dn i Indicating that the ith data phase is a lag signal, up sig Representing the number of leading signals in k sets of data as greater than the number of lagging signals, dn sig Indicating that the number of lag signals in k groups of data is greater than the number of lead signals, up_dn is the output value of a majority voter, wherein the first stage of the majority voter respectively counts the number of k lead signals and the number of lag signals, the second stage compares the numbers of the two signals, and if the number of lead signals in k groups of data is greater than the number of lag signals, the majority voter outputs a lead signal, otherwise, outputs a lag signalAnd the majority voter outputs a no-action signal when the number of the leading signals is more than the number of the lagging signals, which means that no phase adjustment is performed.
5. The system of claim 1, wherein the digital filter is further configured to operate on output data of the majority voter via a proportional path and an integral path, respectively, the proportional path shifting the data left with a sign, to achieve a power of 2 amplification; and the integrating path sums the data in each clock period, carries out signed bit right shift on the summed data, realizes power reduction of 2, and carries out addition operation of signed numbers on the proportional path data and the integrating path data to obtain the output data of the digital filter.
6. The system of claim 1, wherein the phase interpolation module provides four phase sampling clocks, the sampling clock period being one half of the serial data period, and the four phase sampling clocks each differing by a fixed n/2 phase.
7. The system of claim 1, wherein the verification module is further configured to take the continuous 32-bit serial data at the input terminal, sequentially fill the serial data into the 0-31-bit registers after 32 clocks, and verify the current circuit 1+X 28 +X 31 Generating the subsequent correct data, performing exclusive-or processing on the generated data and the sampled data, observing an exclusive-or result, and determining whether the current sampled data is correct or not, wherein X represents the nth bit of the shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310712731.8A CN116707521A (en) | 2023-06-15 | 2023-06-15 | 8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310712731.8A CN116707521A (en) | 2023-06-15 | 2023-06-15 | 8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116707521A true CN116707521A (en) | 2023-09-05 |
Family
ID=87844752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310712731.8A Pending CN116707521A (en) | 2023-06-15 | 2023-06-15 | 8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116707521A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117254894A (en) * | 2023-11-20 | 2023-12-19 | 西安智多晶微电子有限公司 | Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment |
| CN117375642A (en) * | 2023-12-06 | 2024-01-09 | 杭州长川科技股份有限公司 | Signal transmitting device, tester and signal output method thereof |
| CN117783836B (en) * | 2024-02-26 | 2024-06-11 | 成都电科星拓科技有限公司 | PRBS generation and self-detection system and PRBS self-detection method |
-
2023
- 2023-06-15 CN CN202310712731.8A patent/CN116707521A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117254894A (en) * | 2023-11-20 | 2023-12-19 | 西安智多晶微电子有限公司 | Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment |
| CN117254894B (en) * | 2023-11-20 | 2024-03-19 | 西安智多晶微电子有限公司 | Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment |
| CN117375642A (en) * | 2023-12-06 | 2024-01-09 | 杭州长川科技股份有限公司 | Signal transmitting device, tester and signal output method thereof |
| CN117375642B (en) * | 2023-12-06 | 2024-04-02 | 杭州长川科技股份有限公司 | Signal transmitting device, tester and signal output method thereof |
| CN117783836B (en) * | 2024-02-26 | 2024-06-11 | 成都电科星拓科技有限公司 | PRBS generation and self-detection system and PRBS self-detection method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116707521A (en) | 8.1Gbps eDP-oriented key circuit system for clock data recovery of high-speed display interface receiving end | |
| US11063741B2 (en) | Phase control block for managing multiple clock domains in systems with frequency offsets | |
| US7366270B2 (en) | PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator | |
| US8149980B2 (en) | System and method for implementing a phase detector to support a data transmission procedure | |
| US8320770B2 (en) | Clock and data recovery for differential quadrature phase shift keying | |
| US9143367B2 (en) | Clock and data recovery architecture with adaptive digital phase skew | |
| CN102510328B (en) | High-speed parallel interface circuit | |
| US8270526B2 (en) | Communication system | |
| JP2000504514A (en) | Digital architecture for reproducing NRZ / NRZI data | |
| US20080145065A1 (en) | Transmitting equipment and receiving equipment | |
| KR20080084726A (en) | Clock and data recovery circuit and communication apparatus including the same | |
| TW200952342A (en) | System and method for implementing a digital phase-locked loop | |
| CN113992319B (en) | CDR circuit for receiver, duo Binary PAM4 receiver and transmission system | |
| JP5086014B2 (en) | Data recovery method and data recovery circuit | |
| KR100371300B1 (en) | Bit synchronizing circuit | |
| US11108536B1 (en) | Method and apparatus for performing clock and data recovery (CDR) | |
| US7532645B1 (en) | Receiver operable to receive data at a lower data rate | |
| KR100393198B1 (en) | Timing recovery apparatus for E2PR4ML and method therefor and apparatus for judqing last data | |
| CN1385972A (en) | Up high-speed data synchronous receiving method and circuit in optical communication system | |
| Park et al. | A single-data-bit blind oversampling data-recovery circuit with an add-drop FIFO for USB2. 0 high-speed interface | |
| US7242739B2 (en) | Method and apparatus for multiphase, fast-locking clock and data recovery | |
| JP5369524B2 (en) | Clock data recovery circuit | |
| KR20050021491A (en) | Fsk receiver having a variable threshold slicer stage and corresponding method | |
| CN116054990B (en) | Parameter self-adaptive high-speed SerDes phase tracking method and system thereof | |
| JP4413664B2 (en) | Signal processing apparatus, applied equalizer, data receiving apparatus, and signal processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |