CN116705704A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN116705704A
CN116705704A CN202210171997.1A CN202210171997A CN116705704A CN 116705704 A CN116705704 A CN 116705704A CN 202210171997 A CN202210171997 A CN 202210171997A CN 116705704 A CN116705704 A CN 116705704A
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Prior art keywords
fin structures
voltage region
shallow trench
trench isolation
fin
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CN202210171997.1A
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Inventor
许嘉榕
傅思逸
许智凯
邱淳雅
陈金宏
林毓翔
林建廷
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202210171997.1A priority Critical patent/CN116705704A/zh
Priority to US17/706,574 priority patent/US20230268424A1/en
Priority to EP22190017.8A priority patent/EP4235763A1/en
Priority to TW111130933A priority patent/TW202335178A/zh
Publication of CN116705704A publication Critical patent/CN116705704A/zh
Pending legal-status Critical Current

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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法主要先提供一基底包含一高压区以及一低压区，形成多个第一鳍状结构于该高压区，再进行一氧化制作工艺以形成一栅极氧化层于该等第一鳍状结构上并接触该等第一鳍状结构。在本实施例中，栅极氧化层底表面包含多个第一突块设于该等第一鳍状结构上而栅极氧化层顶表面则包含多个第二突块。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种整合高压元件与低压元件的方法。
背景技术
以目前的半导体技术水准，业界已能将控制电路、存储器、低压操作电路以及高压操作电路及元件同时整合制作在单一芯片上，由此降低成本，同时提高操作效能，其中如垂直扩散金属氧化物半导体(vertical double-diffusion metal-oxide-semiconductor,VDMOS)、绝缘栅极双载流子晶体管(insulated gate bipolar transistor,IGBT)以及横向扩散金属氧化物半导体(lateral-diffusion metal-oxide-semiconductor,LDMOS)等制作在芯片内的高压元件，由于具有较佳的切换效率(power switching efficiency)，因此又较常被应用。如本领域技术人员所知，前述的高压元件往往被要求能够承受较高的击穿电压，并且能在较低的阻值下操作。
另外随着元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子沟道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短沟道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的沟道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而随着元件尺寸持续缩小下现行高压元件与低压元件如鳍状结构场效晶体管的整合上仍存在许多挑战，例如漏电流以及击穿电压的控制等等。因此，如何改良现有高压元件与低压元件的架构即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作半导体元件的方法，其主要先提供一基底包含一高压区以及一低压区，形成多个第一鳍状结构于该高压区，再进行一氧化制作工艺以形成一栅极氧化层于该等第一鳍状结构上并接触该等第一鳍状结构。在本实施例中，栅极氧化层底表面包含多个第一突块设于该等第一鳍状结构上而栅极氧化层顶表面则包含多个第二突块。
本发明另一实施例揭露一种半导体元件，其主要包含一基底包含一高压区以及一低压区、多个第一鳍状结构设于高压区以及一栅极氧化层设于该等第一鳍状结构上并接触该等第一鳍状结构。
附图说明
图1至图11为本发明一实施例制作半导体元件的方法示意图。
主要元件符号说明
12:基底
14:高压区
16:低压区
20:鳍状结构
22:衬垫层
24:衬垫层
26:硬掩模
28:突块
30:绝缘层
32:浅沟隔离
34:凹槽
36:绝缘层
38:浅沟隔离
40:硬掩模
42:图案化掩模
44:蚀刻制作工艺
46:栅极氧化层
48:突块
50:突块
52:图案化掩模
54:蚀刻制作工艺
56:栅极氧化层
58:栅极结构
60:源极/漏极区域
62:外延层
具体实施方式
请参照图1至图11，图1至图11为本发明一实施例制作半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有两个或以上的晶体管区，例如包括一高压区14以及一低压区16，其中高压区14较佳于后续制作工艺中制备高压元件而低压区16中则用来制备低压元件。在本实施例中，高压区14以及低压区16可包含相同导电型式或不同导电型式的晶体管区，例如各为PMOS晶体管区以及/或NMOS晶体管区，且两个区域分别预定为后续制作不同临界电压(threshold voltage)的栅极结构。在本实施例中可先选择于高压区14利用离子注入制作工艺形成P型深阱区并于低压区16中形成N型深阱区，但各区域的导电型式均不局限于此。
然后于高压区14以及于低压区16的基底12上分别形成多个鳍状结构20。依据本发明的优选实施例，鳍状结构20较佳通过侧壁图案转移(sidewall image transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑***，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层或轴心体(mandrel)于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构20的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构20。另外，鳍状结构20的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构20。这些形成鳍状结构20的实施例均属本发明所涵盖的范围。
在本实施例中，鳍状结构20顶表面可于上述图案化过程中设有一衬垫层22、一衬垫层24以及一硬掩模26于基底12上，其中衬垫层22较佳包含氧化硅，衬垫层24较佳包含氮化硅，硬掩模26较佳包含氧化硅，但均不局限于此。
然后如图2所示，进行一鳍状结构移除(fin removal)以及/或鳍状结构切割(fincut)制作工艺去除高压区14与低压区16的部分鳍状结构20，以于鳍状结构20旁形成突块28。在本实施例中，鳍状结构移除制作工艺可于俯视角度下去除沿着相同方向延伸的部分鳍状结构而鳍状结构切割制作工艺则可于俯视角度下将原本呈现环状的鳍状结构分隔为多条各自独立且沿着同一方向延伸的鳍状结构。
随后如图3所示，进行一可流动式化学气相沉积(flowable chemical vapordeposition,FCVD)制作工艺形成一由氮氢氧化硅(SiONH)所构成的绝缘层30于突块28与鳍状结构20上并填满鳍状结构20之间的凹槽，再进行一平坦化制作工艺例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分绝缘层30与硬掩模26使绝缘层30顶表面切齐衬垫层24顶表面。在此阶段高压区14与低压区16中鳍状结构20周围所剩余的绝缘层30较佳形成浅沟隔离32。
如图4所示，接着进行一光刻及蚀刻制作工艺，例如可先形成一图案化掩模(图未示)例如图案化光致抗蚀剂于高压区14与低压区16并暴露出部分浅沟隔离30表面，再利用图案化掩模为掩模以蚀刻方式去除高压区14的与低压区16的部分浅沟隔离32、部分突块28以及部分基底12形成多个凹槽34，较佳使得凹槽34的深度大于鳍状结构20间的凹槽的深度。
随后先进行一次大气压化学气相沉积(sub-atmospheric chemical vapordeposition,SACVD)制作工艺以形成另一绝缘层36于高压区14与低压区16并填满凹槽34，再利用硬掩模26当作停止层来进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分绝缘层36。在此阶段高压区14与低压区16中所剩余的绝缘层36较佳形成浅沟隔离38且浅沟隔离38顶表面较佳切齐浅沟隔离32顶表面。需注意的是，本阶段所形成的绝缘层36与图3所形成的绝缘层30较佳包含不同材料，例如图3所形成的绝缘层30或浅沟隔离32较佳包含氮氢氧化硅(SiONH)而本阶段所形成的绝缘层36或浅沟隔离38则较佳包含二氧化硅(SiO2)。
另外又需注意的是，本阶段所进行的SACVD制作工艺较佳以四乙氧基硅烷(tetraethyl orthosilicate,TEOS)与臭氧(O3)为前驱物以及二氧化硅为后期沉积物。前述图3所进行的FCVD制作工艺则以三硅烷胺(trisilyamine)、氨气(NH3)以及氧气(O2)为前驱物以及氮氢氧化硅(SiONH)为后期沉积物。
之后如图5所示，先形成一由氮化硅所构成的硬掩模40并全面性覆盖高压区14与低压区16的浅沟隔离32、38，形成一图案化掩模42如图案化光致抗蚀剂于硬掩模40上并暴露出高压区14的部分鳍状结构20与浅沟隔离38，接着利用图案化掩模42为掩模进行一蚀刻制作工艺44去除高压区14的部分硬掩模40及同样由氮化硅所构成的衬垫层24但较佳不去除任何浅沟隔离32、38与鳍状结构20。
如图6所示，然后再利用图案化掩模42为掩模进行另一蚀刻制作工艺去除高压区14中的部分浅沟隔离32与部分浅沟隔离38，使部分剩余的浅沟隔离32、38顶表面略低于鳍状结构20顶表面。需注意的是，本阶段利用蚀刻去除部分浅沟隔离32、38时由氧化硅所构成的衬垫层22虽仍设于鳍状结构20顶表面，但不局限于此，依据本发明其他实施例又可于去除部分浅沟隔离32、38时同时去除由氧化硅所构成的衬垫层22并暴露出鳍状结构20顶表面。
如图7所示，接着进行一氧化制作工艺以形成栅极氧化层46于高压区14的鳍状结构20上。更具体而言，本阶段所进行的氧化制作工艺较佳以炉管方式将原本剩余由氧化硅所构成的衬垫层22一同反应并形成一横跨多个鳍状结构的栅极氧化层46，其中所形成的栅极氧化层46较佳同时接触多个鳍状结构20。从结构上来看，栅极氧化层46底表面包含多个突块48设于并接触多个鳍状结构20，且栅极氧化层46顶表面也包含多个突块50，其中栅极氧化层46顶表面的突块50与底表面的突块48较佳相互对称，顶表面的各突块50宽度可略小于底表面的各突块48宽度，顶表面的各突块50体积可略小于底表面的各突块48体积，但均不局限于此。
随后如图8所示，先形成一图案化掩模52如图案化光致抗蚀剂于高压区14的栅极氧化层46与两侧的部分浅沟隔离38上，再利用图案化掩模52为掩模进行一蚀刻制作工艺54去除高压区14与低压区16的所有硬掩模40及衬垫层24并暴露出下方的衬垫层22。
如图9所示，然后可选择去除或不去除图案化掩模52，再进行另一蚀刻制作工艺去除高压区14与低压区16的部分浅沟隔离32、38，使剩余的浅沟隔离32、38顶表面略低于鳍状结构20顶表面。在本实施例中，剩余的浅沟隔离32、38顶表面可选择略高于、切齐或略低于栅极氧化层46底表面例如栅极氧化层46与下方突块48的交界处或突块48底表面，这些均属本发明所涵盖的范围。
之后请同时参照图10至图11，图10至图11为本发明一实施例接续图9制作半导体元件的方法示意图，其中图10为本发明一实施例制作半导体元件的俯视图，图11则为图10中沿着切线AA’以及切线BB’方向制作半导体元件的剖面示意图。如图10至图11所示，可先去除高压区14与低压区16的衬垫层22，进行一道或以上氧化制作工艺例如现场蒸气成长制作工艺(in-situ steam generation,ISSG)制作工艺形成一由氧化硅所构成的栅极氧化层56于低压区16的鳍状结构20上。接着可于高压区14与低压区16的鳍状结构20上分别形成栅极结构58或虚置栅极。如同前述实施例，栅极结构58的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-kfirst)制作工艺或后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。随后可选择于各栅极结构58两侧形成间隙壁，在间隙壁两侧的基底12内形成源极/漏极区域60以及/或外延层62，形成层间介电层(图未示)环绕各栅极结构，并可选择以金属栅极置换制作工艺将各栅极结构转换为金属栅极。由于依据金属栅极置换制作工艺将各栅极结构转换为金属栅极为本领域所熟知技术，在此不另加赘述。
需注意的是，从图10的俯视角度来看，高压区14中包含源极/漏极区域60的鳍状结构20与栅极结构58正下方所重叠的鳍状结构20较佳沿着Y方向延伸且包含源极/漏极区域60的鳍状结构20两侧边缘如顶部边缘与尾端边缘均沿着X方向切齐栅极结构58正下方的鳍状结构20顶部与尾端边缘。低压区16中包含源极/漏极区域60的鳍状结构20与栅极结构58正下方的鳍状结构20虽然也沿着Y方向延伸，但仅有一侧包含源极/漏极区域60的鳍状结构20边缘是切齐栅极结构58正下方的鳍状结构20边缘。
从另一角度来看，高压区14中包含源极/漏极区域60的鳍状结构20与栅极结构58正下方的鳍状结构20较佳为不同根鳍状结构，而低压区16中包含源极/漏极区域60的鳍状结构20与栅极结构58正下方的鳍状结构20则为同一根鳍状结构。此外，高压区14及低压区16中的栅极结构58各包含至少一长边沿着X方向延伸以及至少一短边沿着Y方向延伸，其中高压区14的中包含源极/漏极区域60的鳍状结构20设于短边两侧而低压区16中包含源极/漏极区域60的鳍状结构20则是设于长边两侧。
另外从图11的剖面结构来看，高压区14中的栅极氧化层46底部包含多个突块48设于并接触多个鳍状结构20且栅极氧化层46顶部也包含多个突块50，其中底部的突块48均高于各鳍状结构20顶表面且未低于鳍状结构20侧壁，顶部的突块50顶表面则可选择低于、切齐或高于两侧的源极/漏极区域60以及/或外延层62顶表面。
综上所述，本发明揭露一种整合高压元件与低压元件的方法，其主要先于高压区与低压区中形成多个鳍状结构20，然后于高压区中形成一栅极氧化层46横跨并同时连接下方多个鳍状结构。依据本发明的优选实施例，于高压区中制备多个鳍状结构可延展源极区域与漏极区域之间的沟道长度并缓和高压元件中高负荷的电压。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (13)

1.一种制作半导体元件的方法，其特征在于，包含：
提供基底包含高压区以及低压区；
形成多个第一鳍状结构于该高压区；以及
进行氧化制作工艺以形成栅极氧化层于该多个第一鳍状结构上并接触该多个第一鳍状结构。
2.如权利要求1所述的方法，还包含：
形成多个第二鳍状结构于该高压区的该多个第一鳍状结构两侧以及多个第三鳍状结构于该低压区；
形成第一浅沟隔离环绕该多个第一鳍状结构、该多个第二鳍状结构以及该多个第三鳍状结构；
形成第二浅沟隔离于该多个第一鳍状结构以及该多个第二鳍状结构之间；
去除该高压区上的该第一浅沟隔离以及该第二浅沟隔离；
形成该栅极氧化层于该多个第一鳍状结构上；
去除该低压区上的该第一浅沟隔离以及该第二浅沟隔离；以及
形成外延层于该多个第二鳍状结构上。
3.如权利要求2所述的方法，其中该第二浅沟隔离底表面低于该第一浅沟隔离底表面。
4.如权利要求2所述的方法，其中该第一浅沟隔离底表面切齐该多个第一鳍状结构底表面。
5.如权利要求2所述的方法，还包含形成该外延层于该多个第三鳍状结构上。
6.如权利要求1所述的方法，其中该栅极氧化层底表面包含多个第一突块设于该多个第一鳍状结构上。
7.如权利要求1所述的方法，其中该栅极氧化层顶表面包含多个第二突块。
8.一种半导体元件，其特征在于，包含：
基底，包含高压区以及低压区；
多个第一鳍状结构，设于该高压区；以及
栅极氧化层，设于该多个第一鳍状结构上并接触该多个第一鳍状结构。
9.如权利要求8所述的半导体元件，还包含：
多个第二鳍状结构，设于该高压区的该多个第一鳍状结构两侧；
多个第三鳍状结构，设于该低压区；
第一浅沟隔离，环绕该多个第一鳍状结构、该多个第二鳍状结构以及该多个第三鳍状结构；
第二浅沟隔离，设于该多个第一鳍状结构以及该多个第二鳍状结构之间；以及
外延层，设于该多个第二鳍状结构上。
10.如权利要求9所述的半导体元件，其中该第二浅沟隔离底表面低于该第一浅沟隔离底表面。
11.如权利要求9所述的半导体元件，其中该第一浅沟隔离底表面切齐该多个第一鳍状结构底表面。
12.如权利要求8所述的半导体元件，其中该栅极氧化层底表面包含多个第一突块设于该多个第一鳍状结构上。
13.如权利要求8所述的半导体元件，其中该栅极氧化层顶表面包含多个第二突块。
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