CN116644702A - Fault-tolerant chip lamination structure of coarse-granularity reconfigurable array three-dimensional integrated circuit, control method and three-dimensional integrated circuit - Google Patents

Fault-tolerant chip lamination structure of coarse-granularity reconfigurable array three-dimensional integrated circuit, control method and three-dimensional integrated circuit Download PDF

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CN116644702A
CN116644702A CN202310572958.7A CN202310572958A CN116644702A CN 116644702 A CN116644702 A CN 116644702A CN 202310572958 A CN202310572958 A CN 202310572958A CN 116644702 A CN116644702 A CN 116644702A
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unit
working
output
port
input
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王康
范建华
王观武
陈桂林
胡敏慧
胡永扬
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National University of Defense Technology
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National University of Defense Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00—Three dimensional [3D] modelling, e.g. data description of 3D objects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a fault-tolerant chip lamination structure of a coarse-granularity reconfigurable array three-dimensional integrated circuit, a control method and the three-dimensional integrated circuit. The fault-tolerant chip laminated structure comprises a plurality of PE blocks, wherein each PE block comprises working PE units and redundant PE units, and the number of the redundant PE units is determined according to the scale of the working PE units; the input signal is connected to the working PE unit and the redundant PE unit through a multiplexer, the output of the PE unit is connected to the multiplexer, and the signal is output through the multiplexer. The structure can route the signals of the failure working PE units to the redundant PE units, so that the normal operation of the chip is ensured, the yield of the coarse-granularity reconfigurable array three-dimensional integrated circuit is greatly improved, the manufacturing cost is reduced, and the reliability is improved.

Description

Fault-tolerant chip lamination structure of coarse-granularity reconfigurable array three-dimensional integrated circuit, control method and three-dimensional integrated circuit
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a fault-tolerant chip laminated structure of a coarse-grained reconfigurable array three-dimensional integrated circuit, a control method and a three-dimensional integrated circuit thereof.
Background
Coarse-grained reconfigurable array integrated circuits have greater flexibility than application-specific integrated circuits, often used for computationally intensive applications. In the latter molar age, semiconductor integrated circuits have been limited in transistor size, cost effectiveness, etc., and three-dimensional integrated circuit (3D IC) technology has been developed to break through these limitations. The coarse-grain reconfigurable array integrated circuit adopts a three-dimensional integrated circuit technology, and a small-scale circuit is stacked and integrated into a large-scale coarse-grain reconfigurable circuit through a chip, so that compared with the coarse-grain reconfigurable array integrated circuit designed by adopting an application-specific integrated circuit technology, the coarse-grain reconfigurable array integrated circuit adopting a 3D IC technology is smaller in area and lower in cost.
A coarse-grain reconfigurable array three-dimensional integrated circuit (3D IC) stacks and integrates multiple layers of Processing Elements (PE) through silicon through holes (Through Silicon Via, TSVs), and the silicon through holes vertically distributed between the stacked layers replace long interconnection lines of the two-dimensional integrated circuit, so that the lengths of the interconnection lines between PE of different stacks are greatly shortened, the delay and the power consumption of the 3D IC are reduced, and the performance of the 3D IC is improved. Fig. 1 gives an example of a coarse-grained reconfigurable array three-dimensional integrated circuit, where the chip comprises a first chip stack and a second chip stack, and in actual designs the chip may comprise 2 or more chip stacks. A plurality of through silicon via structures are arranged between the first chip stack layer and the second chip stack layer for data interaction between PE units.
However, during the manufacture and use of the coarse-grain reconfigurable array 3D IC, defects or faults of part of PEs may be caused, and the PEs with defects are very likely to fail rapidly during the use of the chip, and if the corresponding fault-tolerant structure and method are not available, the failure of part of PEs will cause the failure of the whole coarse-grain reconfigurable array 3D IC.
Disclosure of Invention
The invention aims to solve the technical problem of providing a fault-tolerant chip laminated structure which can improve the yield and reliability of a coarse-grain reconfigurable array three-dimensional integrated circuit and reduce the manufacturing cost of the three-dimensional integrated circuit.
In order to solve the technical problems, the invention adopts the following technical scheme: a fault tolerant chip stack architecture for a coarse-grained reconfigurable array three-dimensional integrated circuit, comprising: the PE block comprises a plurality of working PE units and a plurality of redundant PE units,
the input port of the input control multiplexer is connected with an input signal, the selection signal input port of the input control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output port of the input control multiplexer is connected with the input ends of the working PE unit and the redundant PE unit;
The input port of the output control multiplexer is connected with the output ends of the working PE unit and the redundant PE unit, the selection signal input port of the output control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output end of the output control multiplexer is connected with the TSV;
the fault tolerant control module causes the failed working PE unit to be replaced by a redundant PE unit by controlling the input control multiplexer and the output control multiplexer.
The further technical proposal is that: the input control multiplexer is used for routing the input signals of the working or redundant PE units, the input ports are connected with the input signals of the working PE units, the selection signal ports are connected with the selection signal output ports of the fault-tolerant control module, and the output ports are connected with the input ports of the corresponding working or redundant PE units; the fault-tolerant control module controls the selection signal of the input control multiplexer to control the transmission path of the input signal, disconnects the failure working PE unit from the input signal, and routes the input signal to the redundant PE unit.
The output control multiplexer is used for routing output signals of the working or redundant PE units, an input port is connected with the output port of the working or redundant PE units, a selection signal port is connected with a selection signal output port of the fault-tolerant control module, and the output port is connected with a corresponding TSV; the fault-tolerant control module controls the selection signal of the output control multiplexer to control the transmission path of the output signal, disconnects the output port of the failure PE unit from the output signal, and connects the output port of the redundancy PE unit with the output signal.
The further technical proposal is that: the fault-tolerant control module comprises a nonvolatile storage unit, a failure PE unit detection module and an input/output fault-tolerant module; the failure PE unit detection module is used for detecting and marking a failure working PE unit and comprises a PE unit input signal input port, a PE unit output signal input port, an address port (ADDR), a DATA port (DATA) and a read-write enabling port (WR); the PE unit input signal input port is connected with the PE unit input signal, the PE unit output signal input port is connected with the PE unit output signal, and the address port, the data port and the read-write enabling port are respectively connected with the address port, the data port and the read-write enabling port of the nonvolatile memory unit; the failure PE unit detection module judges whether the working PE unit is a failure PE unit or not by detecting an input signal and an output signal of the working PE unit, if the working PE unit does not have the output signal after inputting the signal, the working PE unit is judged to be failed, failure information of the working PE unit is written into a corresponding bit in the nonvolatile storage module, namely the corresponding bit is written into 0;
the nonvolatile storage unit is used for storing the state of the working PE unit and comprises a data port, an address port and a read-write enabling port, and is connected with the input-output fault-tolerant module and the failure PE unit detection module; 1 bit records the status information of a working PE unit, wherein a bit of 1 indicates that the working PE unit is normal, and a bit of 0 indicates that the working PE unit is invalid; the fault-tolerant control module identifies a failed working PE unit according to the working PE unit state information stored in the nonvolatile storage unit, disconnects a signal connected to the failed working PE unit by generating a selection signal corresponding to the multiplexer, and connects the disconnected signal to the redundant PE unit;
The input/output fault-tolerant module comprises a selection signal output port, an address port, a data port and a read/write enabling port, wherein the selection signal output port is connected with the input control multiplexer and the selection signal input port of the output control multiplexer, and the address port, the data port and the read/write enabling port are respectively connected with the address port, the data port and the read/write enabling port of the nonvolatile memory unit; the input-output fault-tolerant module controls a transmission path of a signal, i.e., disconnects a signal connected to a failed working PE unit, based on the working PE unit state information stored in the nonvolatile memory unit, and connects the disconnected signal to the redundant PE unit.
The further technical proposal is that: the input/output fault-tolerant module comprises a PE state information reading unit, a judging unit and an output unit, wherein the PE state information reading unit is in bidirectional connection with the judging unit, the PE state information reading unit is connected with an address port (ADDR), a DATA port (DATA) and a read/write enabling port (WR) of the nonvolatile storage unit, the judging unit is in bidirectional connection with the output unit, and the output unit is connected with the input control multiplexer and the output control multiplexer; the PE state information reading unit reads the state information of the working PE units stored in the nonvolatile storage unit in real time, the judging unit identifies the invalid working PE unit according to the working PE state information read by the PE state information reading unit, the output unit generates a selection signal of the multiplexer according to the invalid working PE unit identified by the judging unit and outputs the selection signal to the multiplexer, and then the multiplexer routes the input and output signals connected with the invalid working PE unit to the redundant PE unit so as to achieve the aim of fault tolerance of the invalid PE unit.
The further technical proposal is that: the laminated structure comprises three PE blocks, each PE block comprises three working PE units and one redundant PE unit, the redundant PE units are arranged on the front side or the rear side of the PE block, IN each PE block, an input signal IN_1 is connected with a No. 2 port of a two-way selector MUX1 and a No. 1 port of a two-way selector MUX2, an input signal IN_2 is connected with a No. 1 port of the two-way selector MUX2 and a No. 1 port of a two-way selector MUX3, and an input signal IN_3 is connected with a No. 2 port of the two-way selector MUX3 and a No. 1 port of the two-way selector MUX 4; the output port of the two-way selector MUX1 is connected with the input port of the working PE1 unit, the output port of the two-way selector MUX2 is connected with the input port of the working PE2 unit, the output port of the two-way selector MUX3 is connected with the input port of the working PE3 unit, and the output port of the two-way selector MUX4 is connected with the input port of the redundant R_PE1 unit; the output port of the working PE1 unit is connected with the No. 1 port of the two-way selector MUX5, the output port of the working PE2 unit is connected with the No. 2 port of the two-way selector MUX5 and the No. 1 port of the two-way selector MUX6, the output port of the working PE3 unit is connected with the No. 2 port of the two-way selector MUX6 and the No. 1 port of the two-way selector MUX7, and the output port of the redundant R_PE1 unit is connected with the No. 2 port of the two-way selector MUX 7; the output port of the two-way selector MUX5 is used as an output signal OUT_1 to be connected with a first TSV, the output port of the two-way selector MUX6 is used as an output signal OUT_2 to be connected with a second TSV, and the output port of the two-way selector MUX7 is used as an output signal OUT_3 to be connected with a third TSV; the selection signals of all the two-way selectors and the input and output signals of all the PE units are connected with the selection signal output end of the fault-tolerant control module.
The further technical proposal is that: the laminated structure comprises three PE blocks, each PE block comprises three working PE units and a redundant PE unit, the redundant PE units are arranged on the front side or the rear side of the PE block, an input signal IN_1 is divided into two paths, the first path is connected with a signal input end of the working PE1 unit, and the first path is connected with a No. 1 input port of a four-path selector MUX 1; the input signal IN_2 is divided into two paths, wherein the first path is connected with the signal input end of the working PE2 unit, and the second path is connected with the No. 2 input port of the four-path selector MUX 1; the input signal IN_3 is divided into two paths, the first path is connected with the signal input end of the working PE3 unit, and the second path is connected with the No. 3 input port of the four-path selector MUX 1; the output port of the four-way selector MUX1 is connected to the redundant R_PE unit; the output signal of the working PE1 unit is connected to the No. 1 input port of the two-way selector MUX2, the output signal of the working PE2 unit is connected to the No. 1 input port of the two-way selector MUX3, the output signal of the working PE3 unit is connected to the No. 1 input port of the two-way selector MUX4, and the output signals of the redundant R_PE unit are respectively connected to the No. 2 ports of the two-way selector MUX2, the two-way selector MUX3 and the two-way selector MUX 4; the selection signal input end of the selector is connected with the selection signal output end of the fault-tolerant control module;
After the working PE1 unit fails, the fault-tolerant control module generates a selection signal of a corresponding selector, the selection signal of the four-way selector MUX1 is 00, the input signal IN_1 is connected to the redundant R_PE unit, the selection signal of the two-way selector MUX2 is 1, the connection between the output port of the working PE1 unit and the output signal OUT_1 is disconnected, and the output port of the redundant R_PE unit is connected to the output signal OUT_1.
The invention also discloses a control method of the fault-tolerant chip laminated structure of the coarse-grain reconfigurable array three-dimensional integrated circuit, which comprises the following steps: when a failure working PE unit does not appear IN the PE block, the PE block works normally, the selection signal of the two-way selector MUX1 is 0, the selection signal of the two-way selector MUX5 is 1, at the moment, the input signal IN_1 is input to the working PE1 unit through the two-way selector MUX1, and the output signal of the working PE1 unit outputs an OUT_1 signal to the first TSV through the two-way selector MUX 5; the selection signal of the two-way selector MUX2 is 1, the selection signal of the two-way selector MUX6 is 0, at the moment, the input signal IN_2 is input into the working PE2 unit through the two-way selector MUX2, and the output signal of the working PE2 unit is output into the second TVS through the two-way selector MUX 6; the selection signal of the two-way selector MUX3 is 1, the selection signal of the two-way selector MUX7 is 0, at the moment, the input signal IN_3 is input to the working PE3 unit through the two-way selector MUX3, and the output signal of the working PE3 unit is output from the signal OUT_3 to the third TVS through the two-way selector MUX 7; the two-way selector MUX4 selects a signal of 0, which indicates that the redundant R_PE1 unit has no input/output signal and is in an idle state;
When a working PE1 unit fails and fails due to a certain reason, a failure PE unit detection module of the fault-tolerant control module detects that no output signal exists after the input signal of the working PE1 unit, the failure PE unit detection module judges the working PE1 unit as a failure PE unit, and writes failure information into a nonvolatile storage unit, and the bit corresponding to the working PE1 unit is changed into 0; and then the input/output fault-tolerant module of the fault-tolerant control module reads that the bit corresponding to the working PE1 unit in the nonvolatile storage unit is 0, the judging unit judges that the working PE1 unit is a failure working PE unit and transmits a judging result to the output unit of the input/output fault-tolerant module, and the output unit generates a selection signal of a two-way selector according to the judging result and routes the input signal of the working PE1 unit to the redundant R_PE unit.
The further technical proposal is that: after the failure PE unit detects that the working PE1 unit fails, the working PE1 unit is marked by modifying bit information corresponding to the working PE1 unit in the nonvolatile storage unit, and then the input/output fault-tolerant module identifies the failure information of the working PE1 unit and generates a selection signal of a two-way selector according to the failure information;
The selection signal of the two-way selector MUX1 is changed to 0, the selection signal of the two-way selector MUX5 is changed to 1, and the connection between the working PE1 unit and the input signal IN_1 and the connection between the working PE1 unit and the output signal OUT_1 are respectively disconnected;
the selection signal of the two-way selector MUX2 is changed to 0, the selection signal of the two-way selector MUX6 is changed to 1, the connection between the working PE2 unit and the input signal IN_2 and the connection between the working PE2 unit and the output signal OUT_2 are respectively disconnected, meanwhile, the input signal IN_1 is connected to the working PE2 unit, and the output of the working PE2 unit is connected with the output signal OUT_1;
the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, meanwhile, the input signal IN_2 is connected to the working PE3 unit, and the output of the working PE3 unit is connected to the output signal OUT_2;
the selection signal of the two-way selector MUX4 is changed to 1, the input signal in_3 is connected to the redundant r_pe1 unit, and the output of the redundant r_pe1 unit is connected to the output signal out_3.
The further technical proposal is that: when the working PE3 unit fails, the fault-tolerant control module detects and marks the failed working PE unit, and as the working PE3 unit is adjacent to the redundant R_PE1 unit, signals passing through the working PE3 unit can be directly routed to the redundant R_PE1 unit; the fault-tolerant control module generates a selection signal of a two-way selector according to the identified failure PE unit information, the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, the selection signal of the two-way selector MUX4 is changed to 1, the input signal IN_3 is connected to the redundant R_PE1 unit, and the output of the redundant R_PE1 unit is connected to the output signal OUT_3.
The invention also discloses a coarse-grained reconfigurable array three-dimensional integrated circuit, which comprises more than two fault-tolerant chip laminated structures, wherein the two fault-tolerant chip laminated structures are connected together through a plurality of TSVs (through silicon vias), so that the stacked integration of chips is realized.
The beneficial effects of adopting above-mentioned technical scheme to produce lie in: and each PE block in the fault-tolerant chip laminated structure is provided with one or more redundant PE units, and if a failure PE unit occurs in the PE block, the signals of the failure PE unit are routed to the redundant PE units. By the method for setting the redundant PE units, when the failure PE units occur, normal use of the three-dimensional integrated circuit of the coarse-granularity reconfigurable array can be ensured, the problem that the failure PE units cause the failure of the three-dimensional integrated circuit of the whole coarse-granularity reconfigurable array is solved, and therefore the yield and reliability of the three-dimensional integrated circuit of the coarse-granularity reconfigurable array are improved, and the manufacturing cost of the three-dimensional integrated circuit is reduced.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a schematic diagram of a conventional coarse-grained reconfigurable array three-dimensional integrated circuit structure in the prior art;
FIG. 2 is a schematic diagram illustrating a coarse-grained reconfigurable array three-dimensional integrated circuit, in accordance with an embodiment of the invention;
FIG. 3A is a schematic top view of the fault tolerant chip stack of FIG. 2;
FIG. 3B is a schematic block diagram of the fault tolerant chip architecture of FIG. 2;
FIG. 4 is a functional block diagram of a fault-tolerant control module in a fault-tolerant chip architecture;
FIG. 5 is a functional schematic diagram of a failure PE unit detection module after a PE unit fails in a fault tolerant chip stack;
FIG. 6 is a functional block diagram of the input-output fault tolerance module of FIG. 4 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a fault tolerant chip stack without a failed PE unit;
FIG. 8 is a schematic diagram of fault tolerant function after failure of an active PE1 unit in the fault tolerant chip stack;
FIG. 9 is a flow chart of a fault tolerant method after a working PE1 unit fails in a fault tolerant chip stack;
FIG. 10 is a schematic diagram of the fault tolerance function after failure of the working PE3 unit in the fault tolerant chip stack;
FIG. 11 is a schematic diagram of another fault tolerant chip architecture in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
In general, the embodiment of the invention discloses a fault-tolerant chip stacking structure of a coarse-grain reconfigurable array three-dimensional integrated circuit, which comprises the following components: the PE block comprises a plurality of working PE units and a plurality of redundant PE units,
the input port of the input control multiplexer is connected with an input signal, the selection signal input port of the input control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output port of the input control multiplexer is connected with the input ends of the working PE unit and the redundant PE unit;
the input port of the output control multiplexer is connected with the output ends of the working PE unit and the redundant PE unit, the selection signal input port of the output control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output end of the output control multiplexer is connected with the TSV;
The fault-tolerant control module detects whether the working PE unit fails, marks the failed working PE unit, and routes the signal transmission path of the failed working PE unit to the redundant PE unit through the selection signal control multiplexer, so that the purpose of fault-tolerant working PE unit is achieved, and normal operation of the coarse-granularity reconfigurable array three-dimensional integrated circuit is ensured.
As can be seen from fig. 1, in the conventional coarse-grain reconfigurable array three-dimensional integrated circuit, each chip stack is only provided with a working PE unit, and the PE unit is easy to fail and fail due to the fact that the PE unit is not firmly pasted and is unevenly stressed in the manufacturing process of the three-dimensional integrated circuit to damage the chip structure, and finally the whole coarse-grain reconfigurable array three-dimensional integrated circuit fails. In order to solve the above problems, a fault-tolerant structure is designed in a coarse-grained reconfigurable array three-dimensional integrated circuit, as shown in fig. 2, a certain proportion of redundant PE units are placed in each chip stack, so that fault tolerance can be effectively performed on the failed PE units, the fault-tolerant capability, the manufacturing yield and the reliability of the chip are improved, and the manufacturing cost of the chip is reduced.
According to the invention, the fault-tolerant chip laminated structure is divided into a plurality of PE blocks according to the scale of the coarse-granularity reconfigurable array three-dimensional integrated circuit, each PE block comprises a plurality of working PE units and a plurality of redundant PE units, the working PE units and the redundant PE units are placed in each PE block according to a proportion, the redundant PE units can be placed in the middle of the working PE units, the fault-tolerant path is reduced, the timeliness of data transmission is ensured, and the redundant PE units can be placed on the front side or the rear side of the working PE units. The greater the number of redundant PE units, the better the fault-tolerant effect, but the greater the number of redundant PE units, the greater the chip area and the higher the cost, so the number of redundant PE units needs to be determined according to the factors of the actual situation balance.
The fault-tolerant chip stack structure will be described in further detail with reference to fig. 3A and 3B. As can be seen from fig. 3A, the present embodiment divides the PE units in the fault tolerant chip stack structure into 3 PE blocks, each PE block includes 3 working PE units and 1 redundant PE unit, and the redundant PE units are placed at the bottom of the PE blocks. As can be seen from fig. 3B, the input signal in_1 is connected to the input port No. 2 of the two-way selector MUX1 and the input port No. 1 of the two-way selector MUX2, the input signal in_2 is connected to the input port No. 1 of the two-way selector MUX2 and the input port No. 1 of the two-way selector MUX3, and the input signal in_3 is connected to the input port No. 2 of the two-way selector MUX3 and the input port No. 1 of MUX 4; the output port of the two-way selector MUX1 is connected with the input port of the working PE1 unit, the output port of the two-way selector MUX2 is connected with the input port of the working PE2 unit, the output port of the two-way selector MUX3 is connected with the input port of the working PE3 unit, and the output port of the two-way selector MUX4 is connected with the input port of the redundant R_PE1 unit; the output port of the working PE1 unit is connected with the No. 1 port of the two-way selector MUX5, the output port of the working PE2 unit is connected with the No. 2 input port of the MUX5 and the No. 1 input port of the two-way selector MUX6, the output port of the working PE3 unit is connected with the No. 2 input port of the two-way selector MUX6 and the No. 1 input port of the two-way selector MUX7, and the output port of the redundant R_PE1 unit is connected with the No. 2 input port of the two-way selector MUX 7; the signal OUT_1 output by the output port of the two-way selector MUX5 is connected with the TSV, the output port of the two-way selector MUX6 is connected with the TSV through the output signal OUT_2, and the output port of the two-way selector MUX7 is connected with the TSV through the output signal OUT_3; the selection signals of all the two-way selectors and the input and output signals of all the PE units are connected with the fault-tolerant control module.
In the invention, the fault-tolerant control module mainly completes the work such as failure detection of the working PE unit and routing of the signal transmission path, and as shown in fig. 4, the fault-tolerant control module mainly comprises a failure PE detection module, an input/output fault-tolerant module and a nonvolatile storage unit. As shown in fig. 6, the failure working PE unit detection module determines whether the working PE unit is a failed PE unit by detecting an input signal and an output signal of the working PE unit, if the working PE unit has no output signal after the input signal of the working PE unit, determines that the working PE unit has failed, and writes failure information of the working PE unit into a corresponding bit in the nonvolatile memory module, that is, writes the corresponding bit as 0.
And the nonvolatile storage unit stores the failure information of the working PE unit, 1 bit records the state information of one working PE unit, wherein a bit of 1 indicates that the working PE unit is normal, and a bit of 0 indicates that the working PE unit is failed. As shown in fig. 6, the input/output fault-tolerant module includes a PE status information reading unit, a decision unit and an output unit, where the PE status information reading unit is connected to the non-volatile storage unit, reads failure information of a working PE unit in the PE block from the non-volatile storage unit, identifies a failure working PE unit according to the read failure information, sends the identified result to the output unit, generates selection signals of two-way selectors by the output unit, and outputs the selection signals to the two-way selectors in the PE block, controls a transmission path of the input/output signals by the selection signals, disconnects a signal transmission path of the failure working PE unit, and connects the signal transmission path of the redundant PE unit, thereby achieving the purpose of shielding the failure working PE unit.
In the embodiment of the invention, the fault-tolerant chip lamination structure of the coarse-granularity reconfigurable array three-dimensional integrated circuit manages the PE unit and controls the two-way selector through the fault-tolerant control module, and the transmission path of the input and output signals is controlled through the two-way selector. When no failure PE unit occurs in the PE block, the PE block operates normally, and the signal transmission path is shown in FIG. 7. At this time, the two-way selector MUX1 select signal is 0, the two-way selector MUX5 select signal is 1, which means that the input signal in_1 is input to PE1 through MUX1, and the PE1 output signal is output to out_1 through MUX 5; the MUX2 select signal is 1, the MUX6 select signal is 0, indicating that the input signal IN_2 is input to PE2 through MUX2, and the PE2 output signal is output to OUT_2 through MUX 6; the MUX3 select signal is 1, the MUX7 select signal is 0, indicating that the IN_3 signal is input to PE3 through MUX3, and the PE3 output signal is output to OUT_3 through MUX 7; the MUX4 select signal is 0, indicating that R_PE1 has no input/output signal and is in an idle state.
When a failure working PE unit occurs IN a PE block, the fault tolerant structure can timely play a role of fault tolerance, and as an example of fig. 8, further describing the fault tolerant structure and the control method IN detail, it can be seen from fig. 8 that the PE block has 3 input signals in_1, in_2 and in_3, and three output signals out_1, out_2 and out_3 respectively correspond to the working PE1 unit, the working PE2 unit and the working PE3 unit, and meanwhile, the PE block further includes 1 redundant PE unit, 7 two-way selectors and a fault tolerant control module. When the working PE1 unit fails and fails due to a certain reason, the failure PE unit detection module of the fault-tolerant control module detects that no output signal exists after the input signal of the working PE1 unit is detected, the failure PE unit detection module judges the working PE1 unit as a failure PE unit, failure information is written into the nonvolatile storage unit, and the bit corresponding to the working PE1 unit is changed into 0. And then the input/output fault-tolerant module of the fault-tolerant control module reads that the bit corresponding to the working PE1 unit in the nonvolatile storage unit is 0, the judging unit judges that the working PE1 unit is a failure PE unit and transmits a judging result to the output unit of the input/output fault-tolerant module, and the output unit generates a selection signal of a two-way selector according to the judging result and routes the input signal of the working PE1 unit to the redundant R_PE unit.
FIG. 9 shows a detailed flow of a fault tolerant control method, in which after a failed PE unit detects that a working PE1 unit fails, the failed PE unit marks bit information corresponding to the working PE1 unit in a nonvolatile memory unit by modifying the bit information, and then an input/output fault tolerant module identifies the failure information of the working PE1 unit and generates a selection signal of a two-way selector according to the failure information. The selection signal of the two-way selector MUX1 is changed to 0, the selection signal of the two-way selector MUX5 is changed to 1, and the connection between the working PE1 unit and the input signal IN_1 and the connection between the working PE1 unit and the output signal OUT_1 are respectively disconnected; the selection signal of the two-way selector MUX2 is changed to 0, the selection signal of the two-way selector MUX6 is changed to 1, the connection between the working PE2 unit and the input signal IN_2 and the connection between the working PE2 unit and the output signal OUT_2 are respectively disconnected, meanwhile, the input signal IN_1 is connected to the working PE2 unit, and the output of the working PE2 unit is connected with the output signal OUT_1; the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, meanwhile, the input signal IN_2 is connected to the working PE3 unit, and the output of the working PE3 unit is connected to the output signal OUT_2; the selection signal of the two-way selector MUX4 is changed to 1, the input signal IN_3 is connected to the redundant R_PE1 unit, and the output of the redundant R_PE1 unit is connected to the output signal OUT_3; the fault tolerance function of the chip is realized through the cooperation of the fault tolerance control module and the two-way selector.
FIG. 10 shows a data transmission path after the failure of the working PE3 unit, and after the failure of the working PE3 unit, the fault-tolerant control module detects and marks the failed working PE unit, and because the working PE3 unit is adjacent to the redundant R_PE1 unit, signals passing through the working PE3 can be directly routed to the fault-tolerant R_PE1 unit. The fault-tolerant control module generates a selection signal of a two-way selector according to the identified failure PE unit information, the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, the selection signal of the two-way selector MUX4 is changed to 1, the input signal IN_3 is connected to the redundant R_PE1 unit, and the output of the redundant R_PE1 unit is connected to the output signal OUT_3. Through the control operation, when the working PE3 unit fails, the fault-tolerant structure can successfully shield the failure unit, and the normal operation of the chip is ensured.
FIG. 11 shows another fault tolerant chip stack structure, from which it can be seen that input signal IN_1 is connected to working PE1 unit, port 1 of four-way selector MUX1, input signal IN_2 is connected to working PE2 unit, port 2 of four-way selector MUX1, input signal IN_3 is connected to working PE3 unit, port 3 of four-way selector MUX1, output port of four-way selector MUX1 is connected to redundant R_PE unit; the output signal of the working PE1 unit is connected to the No. 1 port of the two-way selector MUX2, the output signal of the working PE2 unit is connected to the No. 1 port of the two-way selector MUX3, the output signal of the working PE3 unit is connected to the No. 1 port of the two-way selector MUX4, and the output signal of the redundant R_PE unit is connected to the No. 2 ports of the MUX2, the MUX3 and the MUX 4; the selection signals of all the selectors are connected to the fault tolerant control module. IN this embodiment, after the working PE1 unit fails, the fault-tolerant control module generates a selection signal of the corresponding selector, where the selection signal of MUX1 is 00, the input signal in_1 is connected to the redundant r_pe unit, the selection signal of MUX2 is 1, the connection between the output port of the working PE1 unit and the output signal out_1 is disconnected, and the output port of the redundant r_pe unit is connected to the output signal out_1.
According to the fault-tolerant chip stacking structure and the control method of the coarse-granularity reconfigurable array three-dimensional integrated circuit, when the working PE unit fails, the failed working PE unit can be disconnected in time, and the redundant PE unit is connected, so that an input signal originally transmitted to the failed working PE unit is routed to the redundant PE unit through the fault-tolerant structure, and the fault-tolerant purpose is achieved. The structure and the method disclosed by the invention can realize fault tolerance of the failure PE unit, so that the yield of the chip can be improved, the manufacturing cost of the chip can be reduced, and the reliability of the chip can be improved.

Claims (10)

1. A fault tolerant chip stack architecture for a coarse-grained reconfigurable array three-dimensional integrated circuit, comprising: the PE block comprises a plurality of working PE units and a plurality of redundant PE units,
the input port of the input control multiplexer is connected with an input signal, the selection signal input port of the input control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output port of the input control multiplexer is connected with the input ends of the working PE unit and the redundant PE unit;
The input port of the output control multiplexer is connected with the output ends of the working PE unit and the redundant PE unit, the selection signal input port of the output control multiplexer is connected with the selection signal output end of the fault-tolerant control module, and the output end of the output control multiplexer is connected with the TSV;
the fault tolerant control module causes the failed working PE unit to be replaced by a redundant PE unit by controlling the input control multiplexer and the output control multiplexer.
2. The fault tolerant chip architecture of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 1, wherein:
the input control multiplexer is used for routing the input signals of the working or redundant PE units, the input ports are connected with the input signals of the working PE units, the selection signal ports are connected with the selection signal output ports of the fault-tolerant control module, and the output ports are connected with the input ports of the corresponding working or redundant PE units; the fault-tolerant control module is used for controlling the selection signal of the input control multiplexer to control the transmission path of the input signal, disconnecting the failure working PE unit from the input signal and routing the input signal to the redundant PE unit;
The output control multiplexer is used for routing output signals of the working or redundant PE units, an input port is connected with the output port of the working or redundant PE units, a selection signal port is connected with a selection signal output port of the fault-tolerant control module, and the output port is connected with a corresponding TSV; the fault-tolerant control module controls the selection signal of the output control multiplexer to control the transmission path of the output signal, disconnects the output port of the failure PE unit from the output signal, and connects the output port of the redundancy PE unit with the output signal.
3. The fault tolerant chip architecture of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 1, wherein: the fault-tolerant control module comprises a nonvolatile storage unit, a failure PE unit detection module and an input/output fault-tolerant module;
the failure PE unit detection module is used for detecting and marking a failure working PE unit and comprises a PE unit input signal input port, a PE unit output signal input port, an address port (ADDR), a DATA port (DATA) and a read-write enabling port (WR); the PE unit input signal input port is connected with the PE unit input signal, the PE unit output signal input port is connected with the PE unit output signal, and the address port, the data port and the read-write enabling port are respectively connected with the address port, the data port and the read-write enabling port of the nonvolatile memory unit; the failure PE unit detection module judges whether the working PE unit is a failure PE unit or not by detecting an input signal and an output signal of the working PE unit, if the working PE unit does not have the output signal after inputting the signal, the working PE unit is judged to be failed, failure information of the working PE unit is written into a corresponding bit in the nonvolatile storage module, namely the corresponding bit is written into 0;
The nonvolatile storage unit is used for storing the state of the working PE unit and comprises a data port, an address port and a read-write enabling port, and is connected with the input-output fault-tolerant module and the failure PE unit detection module; 1 bit records the status information of a working PE unit, wherein a bit of 1 indicates that the working PE unit is normal, and a bit of 0 indicates that the working PE unit is invalid; the fault-tolerant control module identifies a failed working PE unit according to the working PE unit state information stored in the nonvolatile storage unit, disconnects a signal connected to the failed working PE unit by generating a selection signal corresponding to the multiplexer, and connects the disconnected signal to the redundant PE unit;
the input/output fault-tolerant module comprises a selection signal output port, an address port, a data port and a read/write enabling port, wherein the selection signal output port is connected with the input control multiplexer and the selection signal input port of the output control multiplexer, and the address port, the data port and the read/write enabling port are respectively connected with the address port, the data port and the read/write enabling port of the nonvolatile memory unit; the input-output fault-tolerant module controls a transmission path of a signal, i.e., disconnects a signal connected to a failed working PE unit, based on the working PE unit state information stored in the nonvolatile memory unit, and connects the disconnected signal to the redundant PE unit.
4. The fault tolerant chip architecture of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 3, wherein:
the input/output fault-tolerant module comprises a PE state information reading unit, a judging unit and an output unit, wherein the PE state information reading unit is in bidirectional connection with the judging unit, the PE state information reading unit is connected with an address port (ADDR), a DATA port (DATA) and a read/write enabling port (WR) of the nonvolatile storage unit, the judging unit is in bidirectional connection with the output unit, and the output unit is connected with the input control multiplexer and the output control multiplexer; the PE state information reading unit reads the state information of the working PE units stored in the nonvolatile storage unit in real time, the judging unit identifies the invalid working PE unit according to the working PE state information read by the PE state information reading unit, the output unit generates a selection signal of the multiplexer according to the invalid working PE unit identified by the judging unit and outputs the selection signal to the multiplexer, and then the multiplexer routes the input and output signals connected with the invalid working PE unit to the redundant PE unit so as to achieve the aim of fault tolerance of the invalid PE unit.
5. The fault tolerant chip architecture of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 1, wherein: the laminated structure comprises three PE blocks, each PE block comprises three working PE units and one redundant PE unit, the redundant PE units are arranged on the front side or the rear side of the PE block, IN each PE block, an input signal IN_1 is connected with a No. 2 port of a two-way selector MUX1 and a No. 1 port of a two-way selector MUX2, an input signal IN_2 is connected with a No. 1 port of the two-way selector MUX2 and a No. 1 port of a two-way selector MUX3, and an input signal IN_3 is connected with a No. 2 port of the two-way selector MUX3 and a No. 1 port of the two-way selector MUX 4; the output port of the two-way selector MUX1 is connected with the input port of the working PE1 unit, the output port of the two-way selector MUX2 is connected with the input port of the working PE2 unit, the output port of the two-way selector MUX3 is connected with the input port of the working PE3 unit, and the output port of the two-way selector MUX4 is connected with the input port of the redundant R_PE1 unit; the output port of the working PE1 unit is connected with the No. 1 port of the two-way selector MUX5, the output port of the working PE2 unit is connected with the No. 2 port of the two-way selector MUX5 and the No. 1 port of the two-way selector MUX6, the output port of the working PE3 unit is connected with the No. 2 port of the two-way selector MUX6 and the No. 1 port of the two-way selector MUX7, and the output port of the redundant R_PE1 unit is connected with the No. 2 port of the two-way selector MUX 7; the output port of the two-way selector MUX5 is used as an output signal OUT_1 to be connected with a first TSV, the output port of the two-way selector MUX6 is used as an output signal OUT_2 to be connected with a second TSV, and the output port of the two-way selector MUX7 is used as an output signal OUT_3 to be connected with a third TSV; the selection signals of all the two-way selectors and the input and output signals of all the PE units are connected with the selection signal output end of the fault-tolerant control module.
6. The fault tolerant chip architecture of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 1, wherein:
the laminated structure comprises three PE blocks, each PE block comprises three working PE units and a redundant PE unit, the redundant PE units are arranged on the front side or the rear side of the PE block, an input signal IN_1 is divided into two paths, the first path is connected with a signal input end of the working PE1 unit, and the first path is connected with a No. 1 input port of a four-path selector MUX 1; the input signal IN_2 is divided into two paths, wherein the first path is connected with the signal input end of the working PE2 unit, and the second path is connected with the No. 2 input port of the four-path selector MUX 1; the input signal IN_3 is divided into two paths, the first path is connected with the signal input end of the working PE3 unit, and the second path is connected with the No. 3 input port of the four-path selector MUX 1; the output port of the four-way selector MUX1 is connected to the redundant R_PE unit; the output signal of the working PE1 unit is connected to the No. 1 input port of the two-way selector MUX2, the output signal of the working PE2 unit is connected to the No. 1 input port of the two-way selector MUX3, the output signal of the working PE3 unit is connected to the No. 1 input port of the two-way selector MUX4, and the output signals of the redundant R_PE unit are respectively connected to the No. 2 ports of the two-way selector MUX2, the two-way selector MUX3 and the two-way selector MUX 4; the selection signal input end of the selector is connected with the selection signal output end of the fault-tolerant control module;
After the working PE1 unit fails, the fault-tolerant control module generates a selection signal of a corresponding selector, the selection signal of the four-way selector MUX1 is 00, the input signal IN_1 is connected to the redundant R_PE unit, the selection signal of the two-way selector MUX2 is 1, the connection between the output port of the working PE1 unit and the output signal OUT_1 is disconnected, and the output port of the redundant R_PE unit is connected to the output signal OUT_1.
7. The method for controlling the fault-tolerant chip stack structure of the coarse-grain reconfigurable array three-dimensional integrated circuit of claim 5, wherein:
when a failure working PE unit does not appear IN the PE block, the PE block works normally, the selection signal of the two-way selector MUX1 is 0, the selection signal of the two-way selector MUX5 is 1, at the moment, the input signal IN_1 is input to the working PE1 unit through the two-way selector MUX1, and the output signal of the working PE1 unit outputs an OUT_1 signal to the first TSV through the two-way selector MUX 5; the selection signal of the two-way selector MUX2 is 1, the selection signal of the two-way selector MUX6 is 0, at the moment, the input signal IN_2 is input into the working PE2 unit through the two-way selector MUX2, and the output signal of the working PE2 unit is output into the second TVS through the two-way selector MUX 6; the selection signal of the two-way selector MUX3 is 1, the selection signal of the two-way selector MUX7 is 0, at the moment, the input signal IN_3 is input to the working PE3 unit through the two-way selector MUX3, and the output signal of the working PE3 unit is output from the signal OUT_3 to the third TVS through the two-way selector MUX 7; the two-way selector MUX4 selects a signal of 0, which indicates that the redundant R_PE1 unit has no input/output signal and is in an idle state;
When a working PE1 unit fails and fails due to a certain reason, a failure PE unit detection module of the fault-tolerant control module detects that no output signal exists after the input signal of the working PE1 unit, the failure PE unit detection module judges the working PE1 unit as a failure PE unit, and writes failure information into a nonvolatile storage unit, and the bit corresponding to the working PE1 unit is changed into 0; and then the input/output fault-tolerant module of the fault-tolerant control module reads that the bit corresponding to the working PE1 unit in the nonvolatile storage unit is 0, the judging unit judges that the working PE1 unit is a failure working PE unit and transmits a judging result to the output unit of the input/output fault-tolerant module, and the output unit generates a selection signal of a two-way selector according to the judging result and routes the input signal of the working PE1 unit to the redundant R_PE unit.
8. The method for controlling the fault-tolerant chip stack structure of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 6, wherein:
after the failure PE unit detects that the working PE1 unit fails, the working PE1 unit is marked by modifying bit information corresponding to the working PE1 unit in the nonvolatile storage unit, and then the input/output fault-tolerant module identifies the failure information of the working PE1 unit and generates a selection signal of a two-way selector according to the failure information;
The selection signal of the two-way selector MUX1 is changed to 0, the selection signal of the two-way selector MUX5 is changed to 1, and the connection between the working PE1 unit and the input signal IN_1 and the connection between the working PE1 unit and the output signal OUT_1 are respectively disconnected;
the selection signal of the two-way selector MUX2 is changed to 0, the selection signal of the two-way selector MUX6 is changed to 1, the connection between the working PE2 unit and the input signal IN_2 and the connection between the working PE2 unit and the output signal OUT_2 are respectively disconnected, meanwhile, the input signal IN_1 is connected to the working PE2 unit, and the output of the working PE2 unit is connected with the output signal OUT_1;
the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, meanwhile, the input signal IN_2 is connected to the working PE3 unit, and the output of the working PE3 unit is connected to the output signal OUT_2;
the selection signal of the two-way selector MUX4 is changed to 1, the input signal in_3 is connected to the redundant r_pe1 unit, and the output of the redundant r_pe1 unit is connected to the output signal out_3.
9. The method for controlling the fault-tolerant chip stack structure of a coarse-grained reconfigurable array three-dimensional integrated circuit of claim 6, wherein:
When the working PE3 unit fails, the fault-tolerant control module detects and marks the failed working PE unit, and as the working PE3 unit is adjacent to the redundant R_PE1 unit, signals passing through the working PE3 unit can be directly routed to the redundant R_PE1 unit; the fault-tolerant control module generates a selection signal of a two-way selector according to the identified failure PE unit information, the selection signal of the two-way selector MUX3 is changed to 0, the selection signal of the two-way selector MUX7 is changed to 1, the connection between the working PE3 unit and the input signal IN_3 and the connection between the working PE3 unit and the output signal OUT_3 are respectively disconnected, the selection signal of the two-way selector MUX4 is changed to 1, the input signal IN_3 is connected to the redundant R_PE1 unit, and the output of the redundant R_PE1 unit is connected to the output signal OUT_3.
10. A coarse-grained reconfigurable array three-dimensional integrated circuit, characterized by: the stacked chip structure comprises more than two fault-tolerant chip stacked structures as claimed in any one of claims 1-6, wherein the two fault-tolerant chip stacked structures are connected together through a plurality of TSVs (through silicon vias), so that stacked integration of chips is realized.
CN202310572958.7A 2023-05-19 2023-05-19 Fault-tolerant chip lamination structure of coarse-granularity reconfigurable array three-dimensional integrated circuit, control method and three-dimensional integrated circuit Pending CN116644702A (en)

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