CN116639645A - Piezoelectric microelectromechanical system (MEMS) structure and method of forming the same - Google Patents

Piezoelectric microelectromechanical system (MEMS) structure and method of forming the same Download PDF

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Publication number
CN116639645A
CN116639645A CN202310350634.9A CN202310350634A CN116639645A CN 116639645 A CN116639645 A CN 116639645A CN 202310350634 A CN202310350634 A CN 202310350634A CN 116639645 A CN116639645 A CN 116639645A
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electrode
layer
piezoelectric layer
piezoelectric
alscn
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陈亭蓉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00158—Diaphragms, membranes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
    • B81B3/0021—Transducers for transforming electrical into mechanical energy or vice versa
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00166—Electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material

Abstract

The film is formed by a process comprising: depositing a first piezoelectric layer; depositing a first electrode layer over the first piezoelectric layer; patterning the first electrode layer to form a first electrode; depositing a second piezoelectric layer over the first electrode; depositing a second electrode layer over the second piezoelectric layer; patterning the second electrode layer to form a second electrode; and depositing a third piezoelectric layer over the second electrode. The third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer are etched to form a via. The through-hole is laterally spaced apart from the first electrode and the second electrode. Then, a first contact plug and a second contact plug are formed to be electrically connected to the first electrode and the second electrode, respectively. Embodiments of the present application also relate to piezoelectric microelectromechanical system (MEMS) structures and methods of forming the same.

Description

Piezoelectric microelectromechanical system (MEMS) structure and method of forming the same
Technical Field
Embodiments of the present application relate to piezoelectric microelectromechanical system (MEMS) structures and methods of forming the same.
Background
Microelectromechanical Systems (MEMS) devices typically have a membrane that is a movable flexible structure. The membranes are thin enough so that they can vibrate. In order to vibrate the membrane, thin through holes are formed in the membrane so that air flow can pass through. The through holes are designed smaller so that gas leakage is reduced.
Disclosure of Invention
Some embodiments of the present application provide a method of forming a piezoelectric microelectromechanical system (MEMS) structure, comprising: forming a film, comprising: depositing a first piezoelectric layer; depositing a first electrode layer over the first piezoelectric layer; patterning the first electrode layer to form a first electrode; depositing a second piezoelectric layer over the first electrode; depositing a second electrode layer over the second piezoelectric layer; patterning the second electrode layer to form a second electrode; and depositing a third piezoelectric layer over the second electrode; etching the third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer to form a via, wherein the via is laterally spaced apart from the first electrode and the second electrode; and forming a first contact plug and a second contact plug electrically connected to the first electrode and the second electrode, respectively.
Other embodiments of the present application provide a piezoelectric microelectromechanical system (MEMS) structure comprising: a film, comprising: a first piezoelectric layer; a first electrode located above the first piezoelectric layer; a second piezoelectric layer located over the first electrode; a second electrode located above the second piezoelectric layer; and a third piezoelectric layer located over the second electrode; and a through hole penetrating the first, second, and third piezoelectric layers, wherein the through hole is laterally spaced apart from the first and second electrodes.
Still further embodiments of the present application provide a piezoelectric microelectromechanical system structure, comprising: a film, comprising: a piezoelectric layer; a first electrode embedded in the piezoelectric layer; a second electrode embedded in the piezoelectric layer, wherein the second electrode is located above the first electrode; and a third electrode embedded in the piezoelectric layer, wherein the third electrode is located above the second electrode; and a through hole penetrating the piezoelectric layer, wherein the first electrode, the second electrode, and the third electrode include edges facing the through hole, and the edges are in contact with the piezoelectric layer.
Drawings
The various aspects of the application are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-15 illustrate cross-sectional views of intermediate stages in the formation of a device including a piezoelectric microelectromechanical system (MEMS) device, in accordance with some embodiments.
Fig. 16 illustrates a lattice structure of AlScN according to some embodiments.
Fig. 17 illustrates breaking of bonds between atoms in an AlScN layer according to some embodiments.
Fig. 18 and 19 illustrate a comparison of airflow profiles in different piezoelectric MEMS devices according to some embodiments.
Fig. 20 illustrates a top view of a piezoelectric MEMS device according to some embodiments.
Fig. 21 illustrates a process flow for forming a piezoelectric MEMS device, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present application may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Piezoelectric microelectromechanical systems (MEMS) devices and methods of forming the same are provided. According to some embodiments of the application, an electrode layer (such as a molybdenum layer) is formed in a piezoelectric layer (such as an AlScN layer). The electrode layers and the piezoelectric layers are alternately formed. Each of the electrode layers is patterned into an electrode prior to depositing the overlying AlScN layer. During etching of the AlScN layer to form the acoustic holes, the acoustic holes are spaced apart from the electrode layer. Thus, in the etching process, the homogenous AlScN layer is etched, and thus the sidewalls of the acoustic holes are smooth. The embodiments discussed herein are intended to provide examples of the subject matter that can be made or used, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the contemplation of the various embodiments. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.
Fig. 1-15 illustrate cross-sectional views of intermediate stages in the formation of a piezoelectric MEMS device according to some embodiments of the application. The corresponding process is also schematically reflected in the process flow shown in fig. 21.
Referring to fig. 1, a support substrate 20 is provided. According to some embodiments, the support substrate 20 includes silicon, and may be a crystalline silicon substrate (semiconductor substrate). According to alternative embodiments, the support substrate 20 may be formed of other materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and the like. The support substrate 20 may have a single-layer structure or a multi-layer structure.
According to some embodiments, layer 22 is formed. Layer 22 may be used as an etch stop layer in a subsequent etching process. Thus, layer 22 is sometimes referred to as etch stop layer 22. The corresponding process is shown as process 202 in process flow 200 as shown in fig. 21. The layer 22 is formed of or includes a material different from that of the support substrate 20. Layer 22 may be formed by a deposition process, an oxidation process, a nitridation process, or the like. For example, layer 22 may be formed using Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. When the support substrate 20 is a silicon substrate, the layer 22 may also be formed by a thermal oxidation process, and the resulting layer 22 includes silicon oxide. According to an alternative embodiment, layer 22 is formed by a nitridation process, and the resulting layer 22 comprises silicon nitride. The thickness T1 of layer 22 may range between about 1 μm and about 5 μm. According to some embodiments, the top surface of layer 22 is planarized, for example, by a Chemical Mechanical Polishing (CMP) process or a mechanical polishing process.
Referring to fig. 2, a piezoelectric layer 24-1 is deposited. According to some embodiments, the piezoelectric layer 24-1 comprises scandium (Sc) doped aluminum nitride (AlScN), and is therefore referred to throughout the description as an AlScN layer. The corresponding process is shown as process 204 in process flow 200 as shown in fig. 21. Other piezoelectric materials such as AlN, gaN, alGaN may also be used. According to some embodiments, the AlScN layer 24-1 is formed by physical vapor deposition (sputtering). For example, alSc may be used to form a target, and AlSc sputtered from the target to deposit on the layer 22. In the deposition process, nitrogen (N 2 ) As a process gas, to deposit AlScN to form AlScN layer 24-1. According to other embodiments, other suitable deposition methods may be used, such as CVD, metal Organic Chemical Vapor Deposition (MOCVD), and the like.
According to some embodiments, the process conditions are selected such that the resulting AlScN layer 24-1 is a single crystal layer. For example, in the deposition of AlScN layer 24-1, the temperature of support substrate 20 is selected to be within a certain range. When the temperature is too low (such as below about 200 ℃), amorphous AlScN or more can be depositedThe AlScN is crystallized and the lattice of subsequently formed electrode layer 26-1 is not aligned with the surface of AlScN layer 24-1. When the temperature is too high (such as above about 800 ℃), the stress in the AlScN layer 24-1 will be unbalanced, which causes the resulting film (64 in fig. 15) to deflect or mismatch during sensing. According to some embodiments, in the deposition of the AlScN layer 24-1, the temperature of the support substrate 20 may be in a range between about 200 ℃ and about 800 ℃ to form a crystalline structure. The temperature may also be in the range between about 200 ℃ and about 500 ℃. In addition, the deposition rate (increase in thickness per unit time) of the AlScN layer 24-1 may also be selected. When the deposition rate is too high, the resulting AlScN layer 24-1 may be amorphous. When the deposition rate is too low, the yield of the manufacturing process is too low. According to some embodiments, the deposition rate of the support substrate 20 may be aboutPer minute and about->In the range between/min. According to some embodiments, the thickness T2 of AlScN layer 24-1 may be about +.>And about->Within a range between.
Furthermore, the lattice structure of AlScN is affected by the atomic percentages of Al, sc, and N, and the lattice structure may affect the etching angle. According to some embodiments, the atomic percent of aluminum may be in a range between about 10% and about 45%, and the atomic percent of nitrogen may be in a range between about 45% and about 75%. The atomic percent scandium may be in a range between about 0% and about 40%. When the atomic percentage of scandium is 0%, the resulting layer is an AlN layer. Adjustment of the atomic percentages in the AlScN layer 24-1 can be achieved by adjusting the atomic percentages of Al and Sc in the target and by adjusting the flow rate of nitrogen.
Fig. 16 and 17 illustrate exemplary crystal structures of AlScN according to some embodiments. AlScN may have wurtzite or hexagonal structures that are used in a subsequent etching process to create an acutely etched with a certain etching angle, as will be discussed in the subsequent paragraphs.
Referring back to fig. 2, an electrode layer 26-1 is deposited on the AlScN layer 24-1. The corresponding process is shown as process 206 in process flow 200 as shown in fig. 21. According to some embodiments, the material of electrode layer 26-1 is selected such that electrode layer 26-1 may also have a lattice structure, the lattice constant of electrode layer 26-1 being as close as possible to the lattice constant of AlScN layer 24-1. Thus, in the subsequent deposition of the AlScN layer, a lattice structure with minimal defects is easily formed. According to some embodiments, electrode layer 26-1 comprises molybdenum, although other suitable materials may be used, such as Mo, pt, ti, tiN, and the like.
According to some embodiments, the electrode layer 26-1 may be formed by physical vapor deposition (PVD, which may be by RF sputtering) using a molybdenum target. Alternatively, electrode layer 26-1 may be deposited using CVD or similar deposition methods. According to some embodiments, the thickness T3 of the electrode layer 26-1 may be aboutAnd about->Within a range between.
The process conditions for depositing electrode layer 26-1 are also selected such that electrode layer 26-1 forms a crystalline layer. According to some embodiments, electrode layer 26-1 has a lattice constant similar to that of AlScN layer 24-1 (e.g., has a difference of less than about 20%). Thus, the electrode layer 26-1 is epitaxially grown from the AlScN layer 24-1. For example, when the deposition temperature for depositing electrode layer 26-1 is in the range between about 200 ℃ and about 500 ℃, the resulting electrode layer 26-1 may be crystalline. According to some embodiments, to increase manufacturing yield, the temperature used to deposit electrode layer 26-1 is selected to be the same as the deposition temperature used to deposit AlScN layer 24-1, such that no adjustment of temperature is required when the process transitions from depositing AlScN layer 24-1 to depositing electrode layer 26-1. Thus, according to some embodiments, the temperatures used to deposit AlScN layer 24-1 and electrode layer 26-1 may be in the same range between about 200 ℃ and about 500 ℃ and may be the same as each other. According to alternative embodiments, the temperature used to deposit electrode layer 26-1 may be lower or higher than the deposition temperature used to deposit AlScN layer 24-1. Furthermore, the deposition rate of the electrode layer 26-1 is controlled not to be too high so that epitaxial growth can occur.
An etch mask 28-1 is then formed and patterned. According to some embodiments, the etch mask 28-1 comprises photoresist. The etch mask 28-1 may be a single layer etch mask or a multi-layer etch mask. For example, the etch mask 28-1 may include a patterned photoresist, and may or may not include a bottom antireflective coating (BARC) underneath the patterned photoresist. The etch mask 28-1 may or may not also include an intermediate layer between the underlayer and the patterned photoresist. According to some embodiments, a top view of the etch mask 28-1 may be similar to the pattern shown in fig. 20, wherein the etch mask 28-1 has a rectangular (such as square) top view shape with an X-shaped opening therein.
Next, as shown in fig. 3, the electrode layer 26-1 is patterned in an etching process, wherein an etching mask 28-1 is used to define the pattern of the remaining portion of the electrode layer, also referred to as the (bottom) electrode 26-1. The corresponding process is shown as process 208 in process flow 200 as shown in fig. 21. According to some embodiments, the etching of electrode layer 26-1 may be performed by a dry etching process, for example, by Reactive Ion Etching (RIE). The etching gas may include a fluorine-containing gas such as SF 6 、CHF 3 、CF 4 HF, or the like, or combinations thereof. The etching process may be performed at a temperature in a range between about 200 ℃ and about 275 ℃. According to an alternative embodiment, the electrode layer 26-1 uses XeF 2 Vapor and room temperature. According to still other alternative embodiments, wet etching may be performed, wherein a process including KOH, HNO may be used 3 Etc., which may use H 2 O is used as a solvent. Hydrogen peroxide (H) 2 O 2 ). The etching gas/chemical solution is selected such that the AlScN layer 24-1 functions as an etch stop layer. In an etching processThereafter, the etching mask 28-1 is removed.
An exemplary top view of electrode 26-1 is shown in fig. 20. Electrode 26-1 has an opening 32-1, which may have the shape of an "X" in top view.
Fig. 4 shows the deposition of the piezoelectric layer 24-2. The corresponding process is shown as process 210 in process flow 200 as shown in fig. 21. According to some embodiments, the piezoelectric layer 24-2 is or includes AlScN or AlN. In addition, the material of the piezoelectric layer 24-2 may be the same as or different from the material of the piezoelectric layer 24-1. For example, when the piezoelectric layer 24-1 includes AlScN, the piezoelectric layer 24-2 may include AlScN, with the atomic percentages of Al, sc, and N in the piezoelectric layer 24-2 being the same as the corresponding atomic percentages of Al, sc, and N in the piezoelectric layer 24-1. In another example, when the piezoelectric layer 24-1 includes AlScN, the piezoelectric layer 24-2 may include AlN or AlScN, with the atomic percentages of Al, sc, and N in the piezoelectric layer 24-2 being different from the corresponding atomic percentages of Al, sc, and N in the piezoelectric layer 24-1. According to some embodiments, the piezoelectric layer 24-2 is also referred to as AlScN layer 24-2 throughout the description. According to some embodiments, the AlScN layer 24-2 may have a thickness T4 of aboutAnd about->Within a range between.
According to some embodiments, after depositing the AlScN layer 24-2, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed to level the top surface of the AlScN layer 24-2. According to an alternative embodiment, the planarization process is not performed after depositing the AlScN layer 24-2.
Because both AlScN layer 24-1 and electrode 26-1 may be crystalline layers having a lattice structure, alScN layer 24-2 may be epitaxially grown from AlScN layer 24-1 and electrode 26-1. The process conditions may also be adjusted to ensure that epitaxy occurs. For example, the deposition rate of electrode layer 26-1 is controlled not to be too high so that epitaxial growth may occur. According to some embodiments, the temperature used to deposit AlScN layer 24-2 is the same as the deposition temperature used to deposit AlScN layer 24-1 and electrode layer 26-2. According to alternative embodiments, the temperature used to deposit AlScN layer 24-2 may be lower or higher than the deposition temperature used to deposit either of AlScN layer 24-1 and electrode layer 26-2.
In fig. 4, a dashed line 30 is drawn to show the location where the AlScN layer 24-2 connects with the AlScN layer 24-1, wherein the connection location may be at the same level as the bottom surface of the electrode layer 26-2. It should be appreciated that because the AlScN layer 24-2 is epitaxially grown from the AlScN layer 24-1, there may not be a distinguishable interface at the locations shown, especially when the AlScN layer 24-1 and the AlScN layer 24-2 have the same composition (same percentage of Al, sc, and N). In contrast, when AlScN layer 24-1 and AlScN layer 24-2 have different compositions, alScN layer 24-1 and AlScN layer 24-2 may be distinguishable from each other, and distinguishable interfaces 30 may be observed. For example, in the case where a first one of the AlScN layers 24-1 and 24-2 includes an element (such as Al) that is not located in a second one of the AlScN layers 24-1 and 24-2, the AlScN layers 24-1 and 24-2 may be distinguishable from each other by detecting the distribution of the element.
With further reference to fig. 4, electrode layer 26-2 is formed. The corresponding process is shown as process 212 in process flow 200 as shown in fig. 21. According to some embodiments, the material of electrode layer 26-1 is selected such that electrode layer 26-2 may also have a lattice structure. Furthermore, the lattice constant of electrode layer 26-2 may be as close as possible to the lattice constant of AlScN layer 24-2, such that in a subsequent deposition of the AlScN layer, a lattice structure with minimized defects is readily formed. According to some embodiments, electrode layer 26-2 comprises molybdenum or other suitable material having a lattice constant close to that of AlScN.
According to some embodiments, electrode layer 26-2 may be formed by PVD, CVD, or the like. According to some embodiments, the thickness T5 of the electrode layer 26-2 may be aboutAnd about->Within a range between.
The process conditions for depositing electrode layer 26-2 are also selected such that electrode layer 26-2 is formed as a single crystal layer. According to some embodiments, electrode layer 26-2 has a lattice constant similar to that of AlScN layer 24-2, and is therefore epitaxially grown from AlScN layer 24-2. For example, the deposition rate of electrode layer 26-1 is controlled not to be too high so that epitaxial growth may occur. According to some embodiments, the temperature used to deposit electrode layer 26-2 is the same as the deposition temperature used to deposit AlScN layer 24-2. According to alternative embodiments, the temperature used to deposit electrode layer 26-2 may be lower or higher than the deposition temperature used to deposit AlScN layer 24-2.
An etch mask 28-2 is then formed and patterned. According to some embodiments, etch mask 28-2 comprises photoresist. The etch mask 28-2 may be a single layer etch mask, a double layer etch mask, or a triple layer etch mask. According to some embodiments, the top view of the etch mask 28-2 may be similar to the pattern shown in fig. 20, wherein the etch mask 28-2 has a rectangular (such as square) top view shape with the openings 32-2 formed in the rectangle. The opening 32-2 may also have an "X" top view shape.
Next, the electrode layer 26-2 is patterned in an etching process, wherein the etching mask 28-2 is used to define a pattern of remaining electrodes, also referred to as (intermediate) electrodes 26-2. The corresponding process is shown as process 214 in process flow 200 as shown in fig. 21. The etching process may be selected from the same set of candidate processes used to etch electrode layer 26-1, and thus details are not repeated here. The etching gas/chemical solution is selected such that the AlScN layer 24-2 functions as an etch stop layer. After the etching process, the etch mask 28-2 is removed. The remaining structure is shown in fig. 5.
An exemplary top view of electrode 26-2 is shown in fig. 20. Electrode 26-2 has an opening 32-2, which may have the shape of an "X" in top view. The opening 32-2 may also at least partially or may completely overlap the opening 32-1 in the electrode 26-1. The electrode 26-2 has at least one (or more) portion(s) extending beyond the edge of the underlying electrode 26-1, which extension portion(s) are used to form a contact plug.
FIG. 5 also illustrates the formation of a piezoelectric layer 24-3 (also referred to as an AlScN layer) and an electrode 26-3 according to some embodiments. The corresponding processes are shown as processes 216, 218, and 220 in process flow 200 as shown in fig. 21. The materials, formation processes, and thicknesses of AlScN layer 24-3 and electrode 26-3 may be selected from the same candidate materials, formation processes, and thickness sets of underlying AlScN layers 24-1 and 24-2 and electrodes 26-1 and 26-2, respectively. So details are not repeated here. According to some embodiments, piezoelectric layer 24-3 includes openings 32-3 that overlap with underlying openings 32-2 in electrode 26-2 and openings 32-1 in electrode 26-1. Further, as shown in FIG. 20, openings 32-1, 32-2, and 32-3 are at least partially aligned. Alternatively, openings 32-1, 32-2, and 32-3 are fully aligned and the corresponding edges of electrodes 26-1, 26-2, and 26-3 are vertically aligned with each other.
According to some embodiments, alScN layer 24-3 and electrode 26-3 are epitaxially grown and may have the same or similar lattice constants as underlying AlScN layers 24-1 and 24-2 and electrodes 26-1 and 26-2. The dashed line 30-2 is shown marking the location where the AlScN layer 24-3 connects to the underlying AlScN layer 24-2. The connection line 32 between the AlScN layers 24-2 and 24-3 may or may not be distinguishable as a distinguishable interface due to the epitaxy of the AlScN layers 24-2 and 24-3.
Fig. 6 illustrates the formation of a piezoelectric layer 24-4 (also referred to as an AlScN layer) according to some embodiments. The corresponding process is shown as process 222 in process flow 200 as shown in fig. 21. The material, forming process and thickness of the AlScN layer 24-4 may be selected from the same candidate materials, forming processes and thickness sets of the underlying AlScN layers 24-1 and 24-2 and 24-3. AlScN layer 24-4 is formed as a blanket layer that completely covers electrode 26-3. A planarization process may (or may not) be performed to planarize the top surface of the AlScN layer 24-4.
According to some embodiments, alScN layer 24-4 is epitaxially grown and may have the same or similar lattice constant as underlying AlScN layer 24-3. Thus, the dashed line 30-3 is shown marking the location where the AlScN layer 24-4 connects to the underlying AlScN layer 24-3. The interface between the AlScN layers 24-3 and 24-4 may or may not be distinguishable due to the epitaxy of the AlScN layers 24-3 and 24-4.
According to some embodiments, alScN layers 24-1, 24-2, 24-3, and 24-4 are formed of the same material, such as AlScN, alN, and the like. Furthermore, the compositions (elements and corresponding atomic percentages of elements) of AlScN layers 24-1, 24-2, 24-3, and 24-4 may be the same as each other (but some of them may be different from each other). Thus, the AlScN layers 24-1, 24-2, 24-3, and 24-4 may collectively form a homogenous layer having a uniform composition without a distinguishable interface therebetween due to the epitaxial process and lattice structure. Throughout the description, alScN layers 24-1, 24-2, 24-3, and 24-4 are individually and collectively referred to as AlScN layer 24. Electrodes 26-1, 26-2, and 26-3 are also referred to individually and collectively as electrode 26.
Fig. 6 also shows the formation of a sacrificial layer 36-1 over the AlScN layer 24-4, wherein the sacrificial layer 36 is formed to assist in the formation of contact plugs in a later process. The corresponding process is shown as process 224 in process flow 200 as shown in fig. 21. According to some embodiments, the sacrificial layer 36-1 is formed of a material having a high etch selectivity with respect to the etching of the AlScN layer, so that the sacrificial layer 36-1 may be selectively removed without damaging the AlScN layer 24-4 in a subsequent process. According to some embodiments, sacrificial layer 36-1 comprises silicon oxide, silicon carbide, silicon oxycarbide, or the like.
Referring to fig. 7, contact openings 38-1, 38-2, and 38-3 are formed. The corresponding process is shown as process 226 in process flow 200 as shown in fig. 21. According to some embodiments, the formation of contact openings 38-1, 38-2, and 38-3 may include etching sacrificial layer 36 and AlScN layers 24-2, 24-3, and 24-4, for example, by an anisotropic etching process. The etching is stopped by electrodes 26-1, 26-2 and 26-3 acting as etch stop layers. According to some embodiments, alScN layer 24 uses H 3 PO 4 To etch, wherein a wet etch process is used. Similar to the etching used to form the via 42 (fig. 9), the wet etching may also form straight edges and sloped edges for the openings 38-1, 38-2, and 38-3 without causing side etching. According to other embodiments, the AlScN layer 24 may also be etched by a dry etching process.
Fig. 8 shows the formation of contact plugs 40-1, 40-2, and 40-3 that extend into contact openings 38-1, 38-2, and 38-3, respectively, to contact electrodes 26-1, 26-2, and 26-3, respectively. The corresponding process is shown as process 228 in process flow 200 as shown in fig. 21. According to some embodiments, the contact plugs 40-1, 40-2, and 40-3 are formed of a metal layer, which may be formed of or include aluminum copper (AlCu), aluminum, nickel, palladium, alloys thereof, and/or combinations thereof. The forming process may include a conformal deposition process and a subsequent patterning process. The patterning process may be performed by forming an etch mask to define the pattern and then etching the conformal metal layer.
According to some embodiments, an insulating dielectric layer (not shown) is formed to surround each of the contact plugs 40-1, 40-2, and 40-3, and to physically and electrically insulate the contact plugs 40-1, 40-2, and 40-3 from the AlScN layers 24-2, 24-3, and 24-4. The insulating dielectric layer is formed of a dielectric layer. The insulating dielectric layer (when formed) may prevent the contact plugs 40-1, 40-2, and 40-3 from being directly electrically connected to the AlScN layer 24. According to an alternative embodiment, the insulating dielectric layer is not formed.
Next, referring to fig. 9, a sacrificial layer 36-2 is deposited to cover the contact plugs 40-1, 40-2, and 40-3. According to some embodiments, sacrificial layer 36-2 is formed of the same material as sacrificial layer 36-1. For example, both sacrificial layers 36-1 and 36-2 may be formed of or include silicon oxide. Throughout the description, sacrificial layers 36-1 and 36-2 may be collectively and individually referred to as sacrificial layer 36.
Fig. 9 also illustrates the formation of a via 42, the via 42 penetrating the sacrificial layer 36 and the AlScN layer 24. The through hole 42 is also referred to as an acoustic hole 42 because it allows air flow to pass through when the resulting microphone is affected by acoustic waves. The corresponding process is shown as process 230 in process flow 200 as shown in fig. 21. Etching may stop on layer 22, layer 22 acting as an etch stop layer for the etching process.
According to some embodiments, to implement the etching process, a patterned etch mask 44 is formed, which may include photoresist, and may be a single layer etch mask, a double layer etch mask, a triple layer etch mask, or the like. Next, the sacrificial layer 36 is etched such that the AlScN layer 24-4 is exposed. The etching may be performed by a dry etching process, which may be anisotropic. The etching gas may include NF 3 And NH 3 Is a mixture of (1), HF and NH 3 And the like.
Next, an etching process 46 is performed to etch the AlScN layer 24, thereby forming the acoustic holes 42. According to some embodiments, the etching process 46 is performed by a wet etching process, while an isotropic dry etching process may also be performed.
According to some embodiments, the etching process 46 may use phosphoric acid (H 3 PO 4 ) The solution is applied. According to some embodiments, the etching chemistry may include about 60% to about 95% H 3 PO 4 . The temperature of the etching solution is raised to above about 100 ℃. Otherwise, H 3 PO 4 And H 2 The azeotropic effect of O is reduced and the etching chemistry may not be able to etch AlScN. According to some embodiments, the temperature of the etching solution is in a range between about 100 ℃ and about 150 ℃. During etching, ion Al is generated 3+ 、Ac 3+ 、OH - 、NH 4+ These ions are all dissolved in the etching liquid and can be removed together with the etching liquid.
Referring to fig. 17, the alscn layer 24 has point defect sites, which may be Al-N bonds and Sc-N bonds. H 3 PO 4 The solution reacts with the point defect sites to break the Al-N bonds and Sc-N bonds, which results in etching of the AlScN layer 24. For example, the bonds Al-N and Sc-N shown along the dashed line 43 break, and the sidewall of the AlScN layer 24 (FIG. 19) facing the resulting acoustic aperture 42 is straight and smooth. The resulting sidewall of the AlScN layer 24 has an inclination angle α (as shown in fig. 17, also as shown in fig. 9) in the range between about 57 degrees and about 63 degrees. According to some embodiments, the tilt angle α may also be equal to about 58.9 degrees.
Due to the lattice structure of the AlScN layer 24, the point defect sites are regularly arranged in a repeating pattern. Thus, as shown in fig. 9 and 19, the sloped side wall 42SW of the AlScN layer 24 facing the resulting acoustic aperture 42 is straight and smooth. The dimensions of the openings in patterned etch mask 44 are selected such that no electrodes 26-1, 26-2, and 26-3 are exposed to acoustic holes 42. Furthermore, with the tilt angle α known and fixed, the bottom width W1 (fig. 9) of the etch mask 44 (which is also the top width of the acoustic holes 42) may be designed such that the bottom width W2 of the acoustic holes 42 is within a selected range. The bottom width W2 is small so that air leakage through the acoustic holes 42 is minimized and signal loss is also minimized. According to some embodimentsThe bottom width W2 may be aboutAnd about->Within a range between. Thus, by employing an etching process to etch along the point defect sites, the top width W1 of the etch mask 44 need not be too small, but a smaller bottom width W2 may still be obtained. The etching process is easier. For example, the upper portion of the acoustic holes 42 may be larger and etching chemicals may more easily enter the acoustic holes 42, making etching more efficient.
In the etching of the AlScN layer 24 discussed above, the etching is performed by wet etching, and an anisotropic etching effect is generated using the lattice structure and the point defect sites. According to an alternative embodiment, the AlScN layer 24 is etched in an anisotropic etching process by dry etching, and a bias power and bias voltage are applied to create an anisotropic effect. Correspondingly, the sidewalls of the AlScN layer 24 may be more vertical than if wet etching were used.
With further reference to FIG. 9, acoustic port 42 is spaced from the nearest edges of electrodes 26-1, 26-2 and 26-3 by spaces S1, S2 and S3. The spacings S1, S2 and S3 cannot be too large otherwise the device performance is degraded due to the significant reduction in the size of the electrodes 26-1, 26-2 and 26-3. The intervals S1, S2 and S3 must not be too small either. Otherwise, electrodes 26-1, 26-2, and 26-3 may be exposed to acoustic port 42 when a process variation occurs. According to some embodiments, the intervals S1, S2, and S3 are less than aboutAnd can be at about->And about (f)Within a range between.
According to some embodiments, the edges of electrodes 26-1, 26-2, and 26-3 facing acoustic port 42 are vertically aligned. According to alternative embodiments, the edge of electrode 26-2 extends more toward the vertical centerline 42C of the via 42 than the upper electrode 26-3 and/or the edge of electrode 26-1 extends more toward the vertical centerline 42C of the via 42 than the upper electrode 26-2. In other words, the openings 32-1 (FIG. 3), 32-2 (FIG. 4) and 32-3 (FIG. 5, also referring to FIG. 20) may be larger and larger.
Fig. 20 shows a top view of an exemplary acoustic port 42. According to some embodiments, the acoustic port 42 has an "X" shape, although other shapes may be employed. The spacing S1, S2, and S3 between the acoustic port 42 and the nearest edges of the electrodes 26-1, 26-2, and 26-3 is marked. The spacing S1, S2, and S3 from different portions of acoustic port 42 to the corresponding nearest edges of electrodes 26-1, 26-2, and 26-3 may be uniform. Sidewall 26SW represents the sidewalls of electrodes 26-1, 26-2, and 26-3, wherein the sidewalls of each of electrodes 26-1, 26-2, and 26-3 form a full ring that surrounds acoustic port 42.
Referring to fig. 10, a back side grinding process is performed on the support substrate 20. The corresponding process is shown as process 232 in process flow 200 as shown in fig. 21. For example, the thickness T6 of the support substrate 20 may be reduced to a range between about 200 μm and about 500 μm. Next, as shown in fig. 11, the support substrate 20 is etched to form a cavity 52. The etching may be performed by a wet etching process or a dry etching process, and the etching process may be anisotropic or isotropic etching. Etching of the support substrate 20 may be performed using the layer 22 as an etch stop layer. According to some embodiments, etching may be performed using KOH as an etching chemistry.
The exposed portions of layer 22 are then removed to extend cavities 52 through layer 22. The resulting structure is shown in fig. 12. According to some embodiments, the etching process may be performed using HF vapor as an etching gas. The acoustic port 42 is thus exposed to the cavity 52 and is connected to the cavity 52. Thus forming MEMS device 54. The corresponding process is shown as process 234 in process flow 200 as shown in fig. 21. According to some embodiments, MEMS device 54 may function as a microphone. The sacrificial layer 36 (fig. 11) is then removed to expose the contact plugs 40-1, 40-2, and 40-3.
Fig. 13 illustrates the attachment of a MEMS device 54 to a package assembly 56 according to some embodiments. The corresponding process is shown as process 236 in process flow 200 as shown in fig. 21. The package assembly 56 may include a printed circuit board, a package substrate, and the like. According to some embodiments, MEMS device 54 is attached to package assembly 56 by an adhesive film (not shown). Further, the device die 58 may also be attached to the package assembly 56, for example, by a die attach film (not shown). The device die 58 may include circuitry for receiving and processing signals from the MEMS device 54. The package assembly 56 includes a through-hole 57, the through-hole 57 being connected to the acoustic port 42 and the cavity 52 and being vertically aligned with the acoustic port 42 and the cavity 52.
Fig. 14 illustrates the formation of electrical connections 60 for connecting the MEMS device 54 to the device die 58. The corresponding process is shown as process 238 in process flow 200 as shown in fig. 21. The electrical connection 60 may be formed by soldering, wire bonding, or the like. Thus, the electrical connection 60 may include bond wires, bond areas, bond balls, and the like.
Fig. 15 shows the attachment of a cover 62 to cover and protect the MEMS device 54 and electrical connections 60. The corresponding process is shown as process 240 in process flow 200 as shown in fig. 21.
In MEMS device 54, electrode 26 and AlScN layer 24 combine to form piezoelectric film 64. The electrodes 26-1, 26-2, and 26-3 function as bottom, middle, and top electrodes, respectively. The intermediate electrode 26-2 may be electrically grounded. During operation of MEMS device 54, a force (e.g., pressure from incident acoustic waves 66) may be applied to piezoelectric film 64. The force causes a voltage to be generated by the piezoelectric layer (AlScN layer) 24. The voltage is picked up by contact plugs 40-1, 40-2, and 40-3 and transferred to circuitry in device die 58. The device die 58 may include a digital signal processor that may convert the voltage to a digital signal.
It should be appreciated that by pre-patterning electrodes 26-1, 26-2, and 26-3 prior to etching AlScN layer 24 for forming acoustic holes 42, no electrodes 26-1, 26-2, and 26-3 will be exposed through acoustic holes 42. FIG. 18 shows an example of what happens if electrodes 26-1, 26-2, and 26-3 are exposed. For example, if electrodes 26-1, 26-2, and 26-3 were patterned in the same process used to etch AlScN layer 24, the sidewalls of acoustic holes 42 would not be smooth due to the difference in etch rates of AlScN layer 24 and electrodes 26-1, 26-2, and 26-3, as shown in FIG. 18. As the acoustic wave 66 passes through the acoustic port 42, turbulence is generated, resulting in signal noise and signal loss. In addition, due to the difference in etching rates of AlScN layer 24 and electrodes 26-1, 26-2, 26-3, it is difficult to control the etching process and the width of acoustic holes 42.
By comparison, as shown in fig. 19, because the electrodes 26-1, 26-2, and 26-3 are pre-patterned, etching of the homogenous AlScN layer 24 is easier to control in the formation of the acoustic holes 42, and the sidewalls 42SW of the acoustic holes 42 are straight and smooth. Turbulence and signal noise caused by the acoustic wave 66 are thus eliminated or reduced.
Embodiments of the present application have several advantageous features. By pre-patterning the electrodes such that the electrodes will not interfere with the etching of the piezoelectric layer, the acoustic holes have smooth sidewalls and the signal noise and signal loss is low. Further, the piezoelectric layer may be etched by wet etching, and the inclined side wall having a fixed inclination angle is generated, so that the size of the sound hole is reduced, and the gas leakage and the signal loss are further reduced.
According to some embodiments of the application, a method comprises: forming a film, comprising: depositing a first piezoelectric layer; depositing a first electrode layer over the first piezoelectric layer; patterning the first electrode layer to form a first electrode; depositing a second piezoelectric layer over the first electrode; depositing a second electrode layer over the second piezoelectric layer; patterning the second electrode layer to form a second electrode; and depositing a third piezoelectric layer over the second electrode; etching the third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer to form a via, wherein the via is laterally spaced apart from the first electrode and the second electrode; and forming a first contact plug and a second contact plug electrically connected to the first electrode and the second electrode, respectively.
In an embodiment, the third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer are etched by a wet etching process. In an embodiment, the wet etching process is performed using a phosphoric acid solution. In an embodiment, a wet etching process is performed such that the via has straight and sloped sidewalls. In an embodiment, the first piezoelectric layer, the second piezoelectric layer, and the third piezoelectric layer have a single crystal structure. In an embodiment, the first electrode layer and the second piezoelectric layer are deposited by epitaxy.
In an embodiment, the method further comprises: depositing a third electrode layer over the third piezoelectric layer; patterning the third electrode layer to form a third electrode; and forming a third contact plug electrically connected to the third electrode, wherein the second electrode is electrically grounded. In an embodiment, the method further comprises: attaching the film to the package assembly, wherein the package assembly includes additional through holes, and wherein the additional through holes are aligned with the through holes.
According to some embodiments of the application, the structure comprises: a film, comprising: a first piezoelectric layer; a first electrode located above the first piezoelectric layer; a second piezoelectric layer over the first electrode; a second electrode located above the second piezoelectric layer; and a third piezoelectric layer over the second electrode; and a through hole penetrating the first piezoelectric layer, the second piezoelectric layer, and the third piezoelectric layer, wherein the through hole is laterally spaced apart from the first electrode and the second electrode. In an embodiment, each of the first and second electrodes includes an edge forming a full ring, and wherein all portions of the full ring are spaced apart from respective nearest portions of the through hole. In an embodiment, the edges enclose an X-shaped region therein.
In an embodiment, the first piezoelectric layer, the second piezoelectric layer, and the third piezoelectric layer are continuously connected together to form a continuous layer without a distinguishable interface therebetween. In an embodiment, the first piezoelectric layer, the second piezoelectric layer, and the third piezoelectric layer have a crystal structure. In an embodiment, the crystal structure is a single crystal structure. In an embodiment, the through hole has a straight edge extending from the top to the bottom of the through hole. In an embodiment, the straight edge forms an oblique angle with the major bottom surface of the film, and wherein the oblique angle is in a range between about 57 degrees and about 63 degrees.
According to some embodiments of the application, a structure comprises: a film, comprising: a piezoelectric layer; a first electrode embedded in the piezoelectric layer; a second electrode embedded in the piezoelectric layer, wherein the second electrode is located above the first electrode; and a third electrode embedded in the piezoelectric layer, wherein the third electrode is located above the second electrode; and a through hole penetrating the piezoelectric layer, wherein the first electrode, the second electrode, and the third electrode include edges facing the through hole, and the edges are in contact with the piezoelectric layer. In an embodiment, the piezoelectric layer has a monocrystalline structure. In an embodiment, the through hole has a straight edge extending from the top surface to the bottom surface of the piezoelectric layer, and wherein the straight edge forms an oblique angle with the main bottom surface of the membrane, and wherein the oblique angle is in a range between about 57 degrees and about 63 degrees. In an embodiment, the piezoelectric layer comprises AlScN.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present application. Those skilled in the art will appreciate that they may readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the application, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the application.

Claims (10)

1. A method of forming a piezoelectric microelectromechanical system (MEMS) structure, comprising:
forming a film, comprising:
depositing a first piezoelectric layer;
depositing a first electrode layer over the first piezoelectric layer;
patterning the first electrode layer to form a first electrode;
depositing a second piezoelectric layer over the first electrode;
depositing a second electrode layer over the second piezoelectric layer;
patterning the second electrode layer to form a second electrode; and
depositing a third piezoelectric layer over the second electrode;
etching the third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer to form a via, wherein the via is laterally spaced apart from the first electrode and the second electrode; and
first and second contact plugs electrically connected to the first and second electrodes, respectively, are formed.
2. The method of claim 1, wherein the third piezoelectric layer, the second piezoelectric layer, and the first piezoelectric layer are etched by a wet etching process.
3. The method of claim 2, wherein the wet etching process is performed using a phosphoric acid solution.
4. The method of claim 2, wherein the wet etching process is performed such that the via has straight and sloped sidewalls.
5. The method of claim 1, wherein the first, second, and third piezoelectric layers have a single crystal structure.
6. The method of claim 1, wherein the first electrode layer and the second piezoelectric layer are deposited by epitaxy.
7. The method of claim 1, further comprising:
depositing a third electrode layer over the third piezoelectric layer;
patterning the third electrode layer to form a third electrode; and
forming a third contact plug electrically connected to the third electrode, wherein the second electrode is electrically grounded.
8. The method of claim 1, further comprising: attaching the film to a package assembly, wherein the package assembly includes an additional through hole, and wherein the additional through hole is aligned with the through hole.
9. A piezoelectric microelectromechanical system (MEMS) structure, comprising:
a film, comprising:
a first piezoelectric layer;
a first electrode located above the first piezoelectric layer;
a second piezoelectric layer located over the first electrode;
a second electrode located above the second piezoelectric layer; and
a third piezoelectric layer located over the second electrode; and
and a through hole penetrating the first, second and third piezoelectric layers, wherein the through hole is laterally spaced apart from the first and second electrodes.
10. A piezoelectric microelectromechanical system structure, comprising:
a film, comprising:
a piezoelectric layer;
a first electrode embedded in the piezoelectric layer;
a second electrode embedded in the piezoelectric layer, wherein the second electrode is located above the first electrode; and
a third electrode embedded in the piezoelectric layer, wherein the third electrode is located above the second electrode; and
a through hole penetrating the piezoelectric layer, wherein the first electrode, the second electrode, and the third electrode include edges facing the through hole, and the edges are in contact with the piezoelectric layer.
CN202310350634.9A 2022-05-03 2023-04-04 Piezoelectric microelectromechanical system (MEMS) structure and method of forming the same Pending CN116639645A (en)

Applications Claiming Priority (3)

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US63/364,038 2022-05-03
US17/811,109 US20230357000A1 (en) 2022-05-03 2022-07-07 Self-Aligned Acoustic Hole Formation in Piezoelectrical MEMS Microphone
US17/811,109 2022-07-07

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CN116639645A true CN116639645A (en) 2023-08-25

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