CN116627880B - PCIe Switch supporting RAID acceleration and RAID acceleration method thereof - Google Patents
PCIe Switch supporting RAID acceleration and RAID acceleration method thereof Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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Abstract
The invention provides a PCIES switch supporting RAID acceleration and a RAID acceleration method thereof, wherein the PCIES switch comprises an uplink port UP, a plurality of downlink ports DP, a virtual downlink port vDP and internal endpoint equipment iEP; the UP port UP is connected with the RC of the host server, the plurality of down ports DP are respectively connected with the downstream PCIe hard disk device, the virtual down port vDP is respectively connected with the UP port UP and the plurality of down ports DP, and is used for virtualizing the internal endpoint device iEP into DP port downstream devices, the internal endpoint device iEP includes a RAID acceleration engine and a DDR controller, the pci switch is connected with the internal DDR memory, and the RAID acceleration engine accesses the internal DDR memory through the DDR controller to perform RAID operation before storing data to be stored from the host server into the PCIe hard disk device. The scheme of the invention avoids PCIe bus bottleneck and host DDR bandwidth consumption caused by the traditional independent RAID accelerator card, effectively reduces the data flow of the server host RC and improves the PCIe bus efficiency.
Description
Technical Field
The invention belongs to the field of hard disk storage, and particularly relates to a PCIe Switch supporting RAID acceleration and a RAID acceleration method thereof.
Background
In the architecture of a server storage system, the high-speed serial bus PCIe gradually becomes a main stream interface for connection between a host and a peripheral device due to the advantages of high performance, scalability, small pin count, hot plug and the like, and is widely used for connection with server peripheral devices such as a video accelerator, a network card, SSD (solid state disk) storage and the like. PCIe switches are designed for expansion of the PCIe bus, limited by the number of PCIe ports of the server host CPU itself. In general, PCIe Switch supports multiple transmission rates and port widths, and can meet the diversified demands of system application scenarios in terms of functions and performance. FIG. 1 illustrates a scenario of a typical PCIe Switch expansion server host PCIe bus structure.
As shown in fig. 1, an UP Port (Upstream Port) of the PCIe Switch 101 and an RC (Root Complex) of a host server are connected through a PCIe x16 Port. PCIe Switch 101 is designed to integrate a large number of DP ports, and each port supports multiple link widths of x1, x2, x4, x8, x16, etc. The DP Port (Downstream Port) of the PCIe Switch 101 is interconnected with Downstream PCIe ep devices (PCIe Endpoint devices) such as 103, 104, 105. Multiple PCIe switches, such as PCIe Switch102 in fig. 1, extend the PCIe bus network in a cascaded fashion so that more PCIe ep devices downstream can be connected.
In order to improve the reliability of data storage and improve the performance of I/O transmission, the host server may also be connected to a RAID (Redundant Arrays of Independent Disks, redundant array of independent disks) accelerator card. RAID is a data storage virtualization technology that provides higher performance and data redundancy storage than a single hard disk by combining multiple physical hard disks into one or more logical hard disk array groups. FIG. 2 illustrates a prior art system connection structure for hardware assisted RAID. The RAID accelerator card 201 implements RAID-related operation acceleration with a proprietary integrated circuit, and is connected to the RC of the host through a high-speed bus such as PCIe. Common RAID standard levels include JBOD (just Bunch of disks), RAID0, RAID1, RAID5, RAID6, etc.
As shown in fig. 2, an NVMe (NVMExpress) SSD device 202 may be directly connected as an EP device to the DP of the RC, with NVMe SSDs 203, 204, 205, 206 extending downstream to the host through PCIe Switch 200. Because the RAID accelerator card 201 and each NVMe SSD device are located downstream of different DP ports of the RC, performing RAID service related to the NVMe SSD device downstream of the PCIe Switch200 must first read and store data stored by the downstream NVMe SSD device to the host DDR, and the data flow in the whole process is as follows: and the host system software reads the service data stored in the NVMe SSD device to the DDR through the hard disk I/O command. The host system software controls the RAID accelerator card 201 to read traffic data from within the DDR and implement RAID operations. The RAID accelerator card 201 stores the result of the RAID operation to the DDR. The host system software writes the RAID operation completed data into the NVMe SSD device through the hard disk I/O command.
It can be seen that the PCIe bus 207 and DDR of the RC downstream ports become critical paths for the data flow throughout the data storage process. Under the high concurrency and data-intensive business scenarios, they easily become bottlenecks of the whole system, affecting the throughput rate of the system. Also, frequent DDR access may occupy too much DDR bandwidth, which may impact the performance of other access DDR traffic on the host, resulting in reduced host performance.
Disclosure of Invention
The invention aims to provide a PCIe Switch supporting RAID acceleration and a RAID acceleration method thereof, which aim to solve the problems of PCIe bus bottleneck and host DDR bandwidth consumption caused by RAID acceleration operation.
According to a first aspect of the present invention, there is provided a PCIe Switch supporting RAID acceleration, the PCIe Switch including an UP port UP, a plurality of down ports DP, a virtual down port vDP, and an internal endpoint device iEP; the UP port UP is connected with an RC of the host server, the plurality of down ports DP are respectively connected with a downstream PCIe hard disk device, the virtual down port vDP is respectively connected with the UP port UP and the plurality of down ports DP, and is used for virtualizing the internal endpoint device iEP into a DP port downstream device, the internal endpoint device iEP includes a RAID acceleration engine and a DDR controller, the PCIe Switch is connected with an internal DDR memory, and the RAID acceleration engine is used for accessing the internal DDR memory through the DDR controller, so as to perform RAID operation before storing data to be stored from the host server into the PCIe hard disk device.
Preferably, the UP port UP, the plurality of downstream ports DP and the virtual downstream port vDP establish internal interconnection through corresponding virtual PCI bridges respectively.
Preferably, the RAID acceleration engine includes a plurality of RAID engine instances for performing RAID calculations in parallel.
Preferably, when performing the RAID operation, a direct point-to-point mode transmission is performed between the PCIe hard disk device and the internal endpoint device iEP.
Preferably, the internal DDR memory is configured to cache the data to be stored obtained by RC of the host server before performing the RAID operation.
According to a second aspect of the present invention, there is provided a RAID acceleration method based on PCIe Switch of the first aspect, including:
judging whether the current working mode of the PCIe Switch is a classical Switch mode or a RAID acceleration mode;
if the current working mode is a RAID acceleration mode, putting a RAID engine in the PCIe Switch into an active state, and caching data to be stored, which are acquired from a host server, by a memory;
and reading the data stored in the internal DDR memory, executing multi-path RAID calculation in parallel through a plurality of RAID engine instances, and storing the calculated result data in PCIe hard disk equipment at the downstream of the PCIe Switch.
Preferably, the method further comprises: if the current working mode is a classical Switch mode, putting a RAID engine in the PCIe Switch into a dormant state;
and directly storing the data to be stored of the host server in the PCIe hard disk device through a path between the PCIe Switch and the RC of the host server.
Preferably, the performing multiple RAID computations in parallel by multiple RAID engine instances further comprises:
the PCIe hard disk device is controlled to transmit hard disk storage data participating in RAID operation to the internal DDR memory through a hard disk I/O command, and point-to-point mode transmission is adopted between the PCIe hard disk device and the DDR memory;
reading the hard disk storage data from the internal DDR memory and the data to be stored received from the host server, performing a predefined type of RAID operation through the plurality of RAID engine instances.
Preferably, the storing the result data after the operation in the PCIe hard disk device downstream of the PCIe Switch further includes:
storing RAID operation results to a designated address of the internal DDR memory;
and controlling the PCIe hard disk device to read the RAID operation result from the specified address through a hard disk I/O command and storing the RAID operation result in the PCIe hard disk device.
Preferably, the PCIe hard disk device is an NVMe SSD device.
Compared with the prior art, the scheme of the invention fully utilizes the point-to-point transmission mode supported by the PCIe Switch, and the RAID acceleration engine integrated in the PCIe Switch is directly communicated with the downstream NVMe SSD device, so that the participation of a host RC is reduced, the data flow of the server host RC is effectively reduced, the efficiency of a PCIe bus is improved, and the requirements of multi-virtual machine and multi-task concurrency of the host are met. The DDR module integrated in the PCIe Switch relieves the pressure of RAID service access host DDR, releases the memory bandwidth of a host server and remarkably improves the performance of the whole system.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure and process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a PCIe Switch expansion server host PCIe bus structure in accordance with the prior art.
FIG. 2 is a schematic diagram of a system connection structure according to a hardware assisted RAID in the prior art.
FIG. 3 is a schematic diagram of the PCIe Switch internal structure with RAID acceleration according to the present invention.
FIG. 4 is a schematic diagram of a data path for a PCIe Switch in the classical Switch mode in accordance with the present invention.
FIG. 5 is a schematic diagram of the data path of a PCIe Switch in RAID acceleration mode according to the present invention.
FIG. 6 is a general flow chart of a RAID acceleration method of a PCIe Switch in accordance with the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which are derived by a person skilled in the art from the embodiments according to the invention without creative efforts, fall within the protection scope of the invention.
According to RAID implementations, it is generally classified into software RAID, full hardware RAID, and hardware assisted RAID. The software RAID is based on the software implementation of a host operating system, and more CPU computing resources are required to complete RAID-related operations. However, the software RAID occupies large host CPU resources and has low performance, and is generally deployed in an application scene with low requirements on storage performance. The full-hardware RAID is equipped with an independent special RAID card, generally called RoC (RAIDon chip, hardware RAID controller), which is used as an interface between a host and a hard disk array and is responsible for managing the whole hard disk array, implementing RAID operations, I/O processing and other tasks, and does not occupy CPU resources of the host. All-hardware RAID is more suitable for a storage array formed by traditional mechanical hard disks, such as SAS or SATA disks, due to potential I/O processing capability bottlenecks, high hardware cost and the like. While the hardware-assisted RAID offloads the intensive RAID operation function to the special hardware operation acceleration engine, the host operating system software is still responsible for the I/O related processing task, and occupies a small amount of CPU processing resources. The hardware-assisted RAID combines the powerful I/O processing capability of a host CPU and a RAID operation hardware acceleration engine, is suitable for AFA (AllFlash Array) full flash memory array application adopting SSD equipment, and meets the requirements of high concurrency, low delay and high IOPS (I/OOperation PerSeconds, read/write times per second) of a system.
Based on the summary of the conventional technology, the invention provides a design scheme of PCIe Switch with RAID acceleration function, and by integrating a special RAID acceleration engine and DDR module in the PCIe Switch, the hardware-assisted RAID acceleration operation function is realized, and the PCIe bus bottleneck and the host DDR bandwidth consumption caused by the conventional independent RAID acceleration card are avoided. The invention fully utilizes the point-to-point transmission mode supported by the PCIe Switch, and the RAID acceleration engine integrated in the PCIe Switch is directly communicated with the downstream NVMe SSD device, thereby reducing the participation of the host RC, effectively reducing the data flow of the server host RC and improving the efficiency of the PCIe bus. Multiple RAID engine examples support multiple paths of RAID parallel operation, improve RAID operation efficiency, and meet the concurrent demands of multiple virtual machines and multiple tasks of a host. The DDR module integrated in the Switch relieves the pressure of RAID business access to the DDR of the host, releases the memory bandwidth of the host server, and remarkably improves the performance of the whole system.
The present invention provides in a first aspect a PCIe Switch supporting RAID acceleration. FIG. 3 illustrates an exemplary embodiment of a PCIe Switch with RAID acceleration functionality of the present invention.
As shown in fig. 3, PCIe Switch contains at least one UP301, multiple DPs 303, 304, 305, vDP302, and iEP 306. The UP301 is connected to the RC 300 of the host via a PCIe bus. The DPs 303, 304, 305 are connected downstream to pcie ep devices, such as NVMe SSDs 310, 311, 312. Inside the PCIe Switch is also provided vDP (Virtual Downstream Port ) 302, which internal endpoint device iEP is connected to the PCIe bus network by means of vDP as a DP port downstream device. The UP301, DP303, 304, 305, vDP302 establish internal interconnections through corresponding virtual PCI bridges (PCI-PCI bridges), respectively. The iEP (Internal Endpoint), internal endpoint device) 306 conforms to the EP device functions defined by the PCIe protocol. The iEP further includes multiple RAID acceleration engine 307 instances and one DDR controller 308. Multiple engine instances may perform RAID computations in parallel and access the memory space of DDR309 through DDR controller 308. The DDR controller 308 is used to provide an interface for each RAID engine instance to access the PCIe Switch-specific DDR 309. The PCIe Switch supports point-to-point mode transmission between downstream EPs (including NVMe SSDs 310, 311, 312) and ieps 306, and the data stream of the transmission does not pass through UP301. The host system may access the RAID acceleration engine and DDR space of iEP306 through an RC configuration.
Based on the connection structure of fig. 3, referring to the flowchart of fig. 6, the RAID acceleration method for PCIe Switch provided by the second aspect of the present invention includes:
step 101: whether the current working mode of the PCIe Switch is the classical Switch mode or the RAID acceleration mode is judged.
The PCIe Switch with RAID acceleration function provided by the invention can select two typical working modes, namely a classical Switch mode and a RAID acceleration mode in a configurable way by supporting software.
If the current working mode is the classical Switch mode, then RAID engine 407 is in a sleep state, and the PCIe Switch operates as a traditional PCIe Switch, primarily for expanding the host PCIe bus, solving the problem of insufficient port count of the server host RC. In this working mode, as shown in fig. 4, the downstream NVMe SSD device completes data read-write of the storage service by PCIe Switch and DDR of RC access host, and completes processing of the I/O task. The classical Switch mode is suitable for services such as JBOD, RAID0 and the like which do not need RAID operation types, and has the advantages of low delay, high concurrency and the like.
Step 102: and if the current working mode is a RAID acceleration mode, putting a RAID engine in the PCIe Switch into an active state, and caching data to be stored acquired from a host server by using the internal DDR memory.
In the RAID acceleration mode, data to be stored of the host server needs to be stored in a disk after performing RAID operation. As shown in fig. 5, RAID engine 507 transitions from a dormant state to an active state and multiple RAID engine instances may perform multiple RAID computations in parallel.
Referring to process (1) shown in fig. 5, first, the host system software instructs the RAID engine 507 to read data requiring a drop disk storage in the host DDR513 through vDP, UP501, RC500 paths, and store the data to the specified address A1 of the PCIe Switch proprietary DDR 509. After storing the data from the host DDR513 that needs to be dropped-disk stored into the PCIe Switch-dedicated DDR509, in process (2), the host system software may control the NVMe SSD510 to transfer the stored data participating in the RAID operation to the designated address A2 of the PCIe Switch-dedicated DDR509 through the NVMeI/O command, with point-to-point mode transmission between the NVMe SSD510 to the DDR 509.
Step 103: and reading data stored in the internal DDR509 memory, performing multi-path RAID calculation in parallel through a plurality of RAID engine instances, and storing the calculated result data in a hard disk device at the downstream of the PCIe Switch.
Referring to process (3) in fig. 5, the RAID engine reads data from addresses A1 and A2 of the DDR509, performs a predefined type of RAID operation, and stores the operation result to a specified address A3 of the DDR509 in process (4).
Finally, in process (5), the host system software controls the NVMe SSD510 to read the RAID operation result from address A3 of DDR509 and to drop the disk for storage through NVMeI/O commands.
Compared with the prior art, the RAID acceleration method of the PCIe Switch fully utilizes the point-to-point (Peer-to-Peer) transmission mode supported by the PCIe Switch, and the RAID acceleration engine integrated in the Switch directly communicates with the downstream NVMe SSD device, so that the participation of a host RC is reduced, the data flow of the server host RC is effectively reduced, and the efficiency of a PCIe bus is improved. Multiple RAID engine examples support multiple paths of RAID parallel operation, improve RAID operation efficiency, and meet the concurrent demands of multiple virtual machines and multiple tasks of a host. The DDR module integrated in the Switch relieves the pressure of RAID business access to the DDR of the host, releases the memory bandwidth of the host server, and remarkably improves the performance of the whole system. The technical scheme of the invention not only can meet the requirements of low delay and high concurrency in JBOD and RAID0 scenes, but also can effectively reduce the load of the RC port of the host in RAID operation process in RAID5, RAID6 and other scenes, release the bandwidth resource of the DDR of the host, obviously improve the overall performance of the AFA array and meet the diversified requirements of different product applications.
It will be appreciated that the types of hard disk devices, component topologies and numbers of ports described in the above embodiments are merely examples. Those skilled in the art may also readily devise combinations and adaptations of the structural features of the above embodiments or adjustments of the parameters or sequence of individual steps of the above method flows according to the needs of use without limiting the inventive concept to the specific structures and steps illustrated above.
While the invention has been described in detail with reference to the foregoing embodiments, it will be appreciated by those skilled in the art that variations may be made in the techniques described in the foregoing embodiments, or equivalents may be substituted for elements thereof; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. The RAID acceleration method of the PCIe Switch is characterized in that the PCIe Switch comprises an uplink port UP, a plurality of downlink ports DP, a virtual downlink port vDP and internal endpoint equipment iEP; the UP port UP is connected to an RC of the host server, the plurality of downstream ports DP are respectively connected to a downstream PCIe hard disk device, the virtual downstream port vDP is respectively connected to the UP port UP and the plurality of downstream ports DP, and is used for virtualizing the internal endpoint device iEP into a device downstream of the DP port, the internal endpoint device iEP includes a RAID acceleration engine and a DDR controller, the PCIe Switch is connected to an internal DDR memory, and the RAID acceleration engine is used for accessing the internal DDR memory through the DDR controller, so as to perform a RAID operation before storing data to be stored from the host server into the PCIe hard disk device, and the RAID acceleration method includes:
judging whether the current working mode of the PCIe Switch is a classical Switch mode or a RAID acceleration mode;
if the current working mode is a RAID acceleration mode, putting a RAID engine in the PCIe Switch into an active state, and caching data to be stored, which are acquired from a host server, by utilizing the internal DDR memory;
reading data stored in the internal DDR memory, executing multi-path RAID calculation in parallel through a plurality of RAID engine examples, and storing the calculated result data in PCIe hard disk equipment at the downstream of the PCIe Switch;
wherein, the UP port UP, the plurality of down ports DP and the virtual down port vDP establish internal interconnection through corresponding virtual PCI bridges respectively;
the RAID acceleration engine comprises a plurality of RAID engine instances for performing multiple RAID calculations in parallel;
when the RAID operation is executed, direct point-to-point mode transmission is carried out between the PCIe hard disk device and the internal endpoint device iEP;
the internal DDR memory is used for caching the data to be stored, which is acquired through RC of the host server, before the RAID operation is executed;
wherein the caching the data to be stored acquired from the host server by using the internal DDR memory further comprises:
the host system software instructs the RAID engine to read data which need to be stored in a drop disc in the host DDR through a virtual downlink port vDP, an uplink port UP and an RC access, and stores the read data to a first appointed address of the internal DDR memory;
and the host system software controls the PCIe hard disk device to transmit the storage data participating in RAID operation to a second designated address of the internal DDR memory through the NVMe I/O command, and the PCIe hard disk device adopts point-to-point mode transmission to the internal DDR memory.
2. The RAID acceleration method of PCIe Switch of claim 1, further comprising:
if the current working mode is a classical Switch mode, putting a RAID engine in the PCIe Switch into a dormant state;
and directly storing the data to be stored of the host server in the PCIe hard disk device through a path between the PCIe Switch and the RC of the host server.
3. The RAID acceleration method of PCIe Switch according to claim 2, wherein the performing multiple RAID computations in parallel through multiple RAID engine instances further comprises:
the PCIe hard disk device is controlled to transmit hard disk storage data participating in RAID operation to the internal DDR memory through a hard disk I/O command, and point-to-point mode transmission is adopted between the PCIe hard disk device and the DDR memory;
reading the hard disk storage data from the internal DDR memory and the data to be stored received from the host server, performing a predefined type of RAID operation through the plurality of RAID engine instances.
4. The RAID acceleration method of PCIe Switch according to claim 3, wherein the storing the result data after the operation in a PCIe hard disk device downstream of the PCIe Switch further comprises:
storing RAID operation results to a designated address of the internal DDR memory;
and controlling the PCIe hard disk device to read the RAID operation result from the specified address through a hard disk I/O command and storing the RAID operation result in the PCIe hard disk device.
5. The RAID acceleration method of PCIe Switch of claim 4, wherein the PCIe hard disk device is an NVMe SSD device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310590333.3A CN116627880B (en) | 2023-05-23 | 2023-05-23 | PCIe Switch supporting RAID acceleration and RAID acceleration method thereof |
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| CN202310590333.3A CN116627880B (en) | 2023-05-23 | 2023-05-23 | PCIe Switch supporting RAID acceleration and RAID acceleration method thereof |
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