CN103403667A - Data processing method and device - Google Patents
Data processing method and device Download PDFInfo
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- CN103403667A CN103403667A CN2012800032891A CN201280003289A CN103403667A CN 103403667 A CN103403667 A CN 103403667A CN 2012800032891 A CN2012800032891 A CN 2012800032891A CN 201280003289 A CN201280003289 A CN 201280003289A CN 103403667 A CN103403667 A CN 103403667A
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Abstract
The invention provides a data processing method and device. The data processing method comprises the steps that a data control chip acquires a first address information from a front-end port chip, wherein the first address information is used for expressing the address of the first data to be written or the address of the second data to be read; the data control chip obtains the second address information based on the first address information, wherein the second address information is used for expressing the position of the first address information in SSD, and the data control chip is connected to the SSD and the front-end port chip through a PCI-E port; the data control chip transmits a first data or a second data between the front-end port chip and the SSD corresponding to the second address information through the PCI-E port, so that the first data received from the front-end port chip can be written with SSD or the second data can be read from the SSD and transmitted to the front-end port chip. The invention can be suitable for the performance demand of a disk array composed of SSD.
Description
Technical field
The present invention relates to memory technology, relate in particular to a kind of data processing method and equipment.
Background technology
Array control unit is used for connecting service server and disk array, is responsible for service control server and disk array business data transmission before, is equivalent to the bridge between service server and disk array.Generally include front-end interface chip, rear end control chip etc. in this array control unit, described front-end interface chip is used for connecting service server, carry out transmission or the reception of business datum with service server, for example, to be sent to from the business datum that service server receives the rear end control chip, perhaps will be sent to service server from the business datum that the rear end control chip receives.Described rear end control chip be used for to connect disk array, can write disk array from the business datum that the transmission of front-end interface chip comes, and the business data transmission that perhaps will read from disk array is to the front-end interface chip.Described disk array is for example the storage array that mechanical hard disk forms.
Along with development and the maturation of storage medium, the disk array that the rear end control chip connects also changes to solid state hard disc from traditional mechanical hard disk, and (Solid State Disk is called for short: SSD).This SSD is than number of times (the Input/Output Operations Per Second of mechanical hard disk per second read-write operation, be called for short: IOPS) ability gets a promotion, for example, the SSD of 2.5 cun forms, IOPS is equivalent to 100～300 times of unidimensional traditional mechanical hard disk, makes the performance of disk array be largely increased.But, rear end control chip in array control unit is to design for traditional mechanical hard disk, IOPS is limited in one's ability, there is 2-4 piece SSD fashion to support in disk array, the follow-up SSD that increases again can't meet the performance requirement of the disk array of SSD composition, thereby has hindered the performance raising of whole disk array.
Summary of the invention
The invention provides a kind of data processing method and equipment, to adapt to the performance requirement of the disk array that SSD forms.
First aspect, provide a kind of data processing method, comprising:
The Data Control chip obtains the first address information from the front-end interface chip, and described the first address information is used for indicating to write the address of the first data or the address that will read the second data;
Described Data Control chip obtains the second address information according to described the first address information, described the second address information is for representing described the first address information in position corresponding to solid-state hard disk SSD, and described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by PCI Express (PCI-E) interface;
Described Data Control chip is by described PCI-E interface, described the first data of transmission or the second data between the described front-end interface chip SSD corresponding with described the second address information, so that will write from described the first data that described front-end interface chip receives described SSD or from described SSD, read described the second data transmission to described front-end interface chip.
in conjunction with first aspect, in the possible implementation of the first, described Data Control chip is by described PCI-E interface, described the first data of transmission or described the second data between the described front-end interface chip SSD corresponding with described the second address information, comprise: described Data Control chip is sent to described front-end interface chip with described the second address information, so that described front-end interface chip is by the PCI-E interface of described Data Control chip, with the direct memory access dma mode, SSD corresponding to described the second address information write described the first data or read described the second data.
in conjunction with first aspect, in the possible implementation of the second, described Data Control chip is by described PCI-E interface, described the first data of transmission or described the second data between the described front-end interface chip SSD corresponding with described the second address information, comprise: described Data Control chip obtains described the first data from the internal memory with described Data Control chip is connected, and according to described the second address information, described the first data are write corresponding described SSD, described the first data are that described front-end interface chip transfers to described internal memory by described Data Control chip, perhaps, described Data Control chip reads described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip, so that described front-end interface chip reads described the second data by described Data Control chip from described internal memory.
in conjunction with first aspect, the implementation that the first of first aspect is possible, the perhaps possible implementation of the second of first aspect, in the third possible implementation, described described the first data or the second data transmitted between the described front-end interface chip SSD corresponding with described the second address information, comprise: in the time writing the described Data Control chip of described first data transmission process of described SSD, described Data Control chip carries out image copying with described data, and the data of image copying are sent to the mirror image SSD that is connected with described Data Control chip.
In conjunction with the possible implementation of the first of first aspect, first aspect or the possible implementation of the second of first aspect, in the 4th kind of possible implementation, described described the first data or described the second data transmitted between the described front-end interface chip SSD corresponding with described the second address information, comprise: in the time writing the described Data Control chip of described first data transmission process of described SSD, described Data Control chip carries out check information to described data and calculates, and described check information is write verification SSD in described SSD.
Second aspect, provide a kind of Data Control chip, comprising:
Information receiving unit, be used for obtaining the first address information from the front-end interface chip, and described the first address information is used for indicating to write the address of the first data or the address that will read the second data;
Information process unit, be used for obtaining the second address information according to described the first address information, described the second address information is for representing described the first address information in position corresponding to solid-state hard disk SSD, and described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by PCI Express (PCI-E) interface;
Transmission control unit, be used for by described PCI-E interface, described the first data of transmission or the second data between the described front-end interface chip SSD corresponding with described the second address information, so that will write from described the first data that described front-end interface chip receives described SSD or from described SSD, read described the second data transmission to described front-end interface chip.
In conjunction with second aspect, in the possible implementation of the first, described transmission control unit, concrete being used for is sent to described front-end interface chip with described the second address information, so that described front-end interface chip, by the PCI-E interface of described Data Control chip, writes described the first data or reads described the second data SSD corresponding to described the second address information with the direct memory access dma mode.
In conjunction with second aspect, in the possible implementation of the second, described transmission control unit, concrete being used for obtained described the first data from the internal memory that is connected with described Data Control chip, and according to described the second address information, described the first data being write corresponding described SSD, described the first data are that described front-end interface chip transfers to described internal memory by described Data Control chip; Perhaps, read described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip, so that described front-end interface chip reads described the second data by described Data Control chip from described internal memory.
In conjunction with the possible implementation of the first of second aspect, second aspect or the possible implementation of the second of second aspect; in the third possible implementation; also comprise: the mirror image protected location; be used in the time writing the described Data Control chip of described first data transmission process of described SSD; described Data Control chip carries out image copying with described data, and the data of image copying are sent to the mirror image SSD that is connected with described Data Control chip.
In conjunction with the possible implementation of the first of second aspect, second aspect or the possible implementation of the second of second aspect; in the 4th kind of possible implementation; also comprise: the verification protected location; be used in the time writing the described Data Control chip of described first data transmission process of described SSD; described Data Control chip carries out check information to described data and calculates, and described check information is write verification SSD in described SSD.
The third aspect, provide a kind of array control unit, comprising: front-end interface chip, solid-state hard disk SSD and Data Control chip of the present invention; Described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by the PCI-E interface.
, in conjunction with the third aspect, in the possible implementation of the first, also comprise: mirror image SSD; Described Data Control chip is by PCI-E interface and described mirror image SSD communication connection; Described mirror image SSD, be used for from the data of described Data Control chip reception image copying.
, in conjunction with the third aspect, in the possible implementation of the second, also comprise: internal memory; Described Data Control chip is by PCI-E interface and described Memory linkage; Described internal memory, be used for receiving the first data from described front-end interface chip, so that described Data Control chip obtains described the first data from described internal memory, writes described SSD; Perhaps, receive the second data that read from described SSD from described Data Control chip, so that described front-end interface chip obtains described the second data from described internal memory.
Data processing method provided by the invention is connected technique effect and is with equipment: the Data Control chip is by adopting the PCI-E interface to be connected with the front-end interface chip communication with described SSD respectively, and by described PCI-E interface between the transmission of data, the IOPS ability of this PCI-E interface is higher, can adapt to the performance requirement of the disk array of SSD composition.
Description of drawings
Fig. 1 is the application structure schematic diagram of data processing method one embodiment of the present invention;
Fig. 2 is the schematic flow sheet of data processing method one embodiment of the present invention;
Fig. 3 is the application structure schematic diagram of another embodiment of data processing method of the present invention;
Fig. 4 is the unprotect schematic flow sheet of another embodiment of data processing method of the present invention;
Fig. 5 is the mirror image protection schematic flow sheet of another embodiment of data processing method of the present invention;
Fig. 6 is the verification protection schematic flow sheet of another embodiment of data processing method of the present invention;
Fig. 7 is the schematic flow sheet of the another embodiment of data processing method of the present invention;
Fig. 8 is the structural representation of Data Control chip one embodiment of the present invention;
Fig. 9 is the structural representation of another embodiment of Data Control chip of the present invention.
Embodiment
, for making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the specific embodiment of the invention is described in further detail.
Embodiment one
Fig. 1 is the application structure schematic diagram of data processing method one embodiment of the present invention, and Fig. 2 is the schematic flow sheet of data processing method one embodiment of the present invention.
As shown in Figure 1, this Data Control chip can be applied in the solid-state storage array control unit usually, this solid-state storage array control unit is used for connecting service server and disk array, and the storage array that the disk array of the present embodiment is comprised of SSD, wherein can comprise a plurality of SSD.Also comprise the front-end interface chip in the solid-state storage array control unit, this front-end interface chip is used for being connected with service server and carrying out data transmission, and the Data Control chip is used for being connected with the SSD array.
The solid-state storage array control unit is equivalent to the bridge between service server and SSD, for example, service server writes SSD with data, perhaps, service server is from the SSD reading out data, and this writes or the process of reading out data is all to control execution by array control unit.Write fashionablely, data will be passed through the front-end interface chip, the Data Control chip transfers to SSD; While reading, data will transfer to service server through Data Control chip, front-end interface chip from SSD.In the present embodiment, the connecting interface of Data Control chip and other equipment all adopts PCI-E (Peripheral Component Interconnect Express) interface, for example, by the PCI-E interface respectively with described SSD and front-end interface chip communication; Therefore, above-mentioned in the first data being write the process of SSD or read the process of the second data from SSD, the transmission in the Data Control chip is actually (have PCI-E interface be illustrated in chip internal be by the PCI-E channel transfer) by the PCI-E channel transfer.In addition, the Data Control chip SSD of the embodiment of the present invention can be for example the storage array of the SSD composition of PCI-E interface.
As shown in Figure 2, the main data of description control chip of the data processing method of the present embodiment is data transmission before service control server and SSD how; Can comprise:
201, the Data Control chip obtains the first address information from the front-end interface chip;
Wherein, described the first address information is used for indicating to write the address of the first data or the address that will read the second data, these first data will write solid-state hard disk SSD, the second data are to read from described SSD, this first address information comprises: be for example address and the length that will write, or the address that will read and length.Can to be service server will write or during the operation of reading out data this first address information, and this that data are corresponding the first address information is sent to the front-end interface chip, then by this front-end interface chip, transfers to the Data Control chip.
Need to prove, the Data Control chip in the present embodiment obtains the first address information from the front-end interface chip, can be that the Data Control chip directly obtains from the front-end interface chip, and this moment, the Data Control chip directly was connected with the front-end interface chip; Perhaps, can be also that the Data Control chip is obtained and got from the front-end interface chip chamber, this moment the Data Control chip with the front-end interface chip between for example by the PCI-E exchange chip, be connected, the first address information is to transfer to the PCI-E exchange chip by the front-end interface chip to transfer to the Data Control chip again in this case, and the PCI-E exchange chip is still by the PCI-E interface and is connected with the Data Control chip.
202, described Data Control chip obtains the second address information according to described the first address information, and described the second address information is used for representing that described the first address information is in position corresponding to solid-state hard disk SSD;
Wherein, the Data Control chip will be according to the first address information of obtaining in 201, calculate and receive the data that will write by any the part storage area on which SSD, perhaps calculate this and provide the data that will read by any the part storage area on which SSD, and obtaining these SSD and the second address information corresponding to storage area thereof, this second address information comprises: address and the length of the above-mentioned SSD that will write or read.By this step, the Data Control chip is actually and has obtained data being write which SSD or which SSD obtaining the data that will read from.
203, described Data Control chip, by described PCI-E interface, transmits described the first data or the second data between the described front-end interface chip SSD corresponding with described the second address information;
Wherein, described the transmission of data comprises: first data that will write and transmission second data that will read from described SSD to front-end interface chip of transmission from described front-end interface chip to SSD.
And, first data that will write of transmission or the second data that read, all can comprise dual mode: a kind of mode is, the Data Control chip is sent to the front-end interface chip with the second address information, directly the first data write SSD or directly from SSD, read the second data with the direct memory access dma mode by the front-end interface chip, the Data Control chip is equivalent to provide data transmission channel for this access.Another kind of mode is, by Data Control chip self, according to the second address information, the first data write SSD or from SSD, reads the second data, and these first data or the second data also transfer to the front-end interface chip by the Data Control chip.
Need to prove; carry out data transmission in the present embodiment between front-end interface chip and SSD; undertaken by the Data Control chip; if some data that relate in transmitting procedure are processed; the processing of the protection such as the related data such as data image, data check is also to be carried out by the Data Control chip.The processing of above-mentioned data transmission procedure and described data protection; by by the Data Control chip, being carried out; so just alleviated (the Central Processing Unit of the central processor CPU in the array control unit; be called for short: burden CPU) makes CPU can be used in the processing of other advanced features (such as snapshot, heavily delete etc.).
The data processing method of the present embodiment, the effect that realize to adapt to the performance requirement of the disk array that SSD forms is following principle: rear end control chip originally is owing to being for traditional mechanical hard disk design, the host-host protocol that its transmission interface and data transmission are followed all adapts to mechanical hard disk, IOPS is limited in one's ability, so can't meet the higher IOPS ability of SSD; And the Data Control chip in the present embodiment, by PCI-E interface and SSD and other devices communicatings, accordingly, the host-host protocol that data transmission is followed also can adopt the PCI-E agreement, be the Data Control chip from hardware on (PCI-E interface) and software (PCI-E agreement) all change into the PCI-E mode, the transmission IOPS ability of this PCI-E mode is higher, can meet the high IOPS performance of SSD fully, is conducive to give full play to the performance of SSD.
Embodiment two
The front-end interface chip that the Data Control chip transmits and the data between SSD may be to write the first data of SSD or may be also the second data that read from SSD.And, the mode of the transmission of data between front-end interface chip and SSD, the mode that namely is equivalent to front-end interface chip side access SSD, can be character device access mode or block device access mode, the Data Control chip of the embodiment of the present invention can be supported the access of this dual mode, namely supports the data of this dual mode to write or read.
The support of the main data of description control chip of the present embodiment to the character device access mode, be described in detail in the data transmission procedure between character device access mode lower front end interface chip and SSD.Under described character device access mode, the front-end interface chip can adopt direct memory access, and (Direct Memory Access, be called for short: DMA) mode is directly accessed SSD.
Fig. 3 is the application structure schematic diagram of another embodiment of data processing method of the present invention, and this structure is a kind of optional array control unit structure, and the Data Control chip of the embodiment of the present invention is arranged in this array control unit.The Data Control chip is supported a plurality of PCI-E interfaces: for example, by a PCI-E interface, with CPU, be connected, as the data exchange channels of CPU and this Data Control chip.Be connected with the front-end interface chip by one or more PCI-E interfaces, (business datum will write SSD or from SSD, read as the passage of business datum, management data, management data is by the CPU storage, can be for example that service server passes through the Data Control chip to the CPU transmission).Be connected with the data image control chip by a PCI-E interface, transmission channel as the image copying data, the purpose of the data image passage that this data image control chip connects is for the data that service server is write to SSD are saved on a plurality of array control units, to eliminate the Single Point of Faliure of array control unit; Be shown in Figure 3 be the structure of an array control unit, this data image control chip is to be connected to another array control unit, is responsible for carrying out the transmission of image copying data to carry out the mirror image data protection between array control unit.Connect the SSD array of a plurality of SSD compositions of rear end by a plurality of PCI-E interfaces, the interface of these SSD is all the PCI-E interface.
Optionally, self can directly connect independent internal memory this Data Control chip, and the example internal memory of connection data control chip as shown in Figure 3, such as this internal memory being set when the block device access mode; And in the character device access mode of the present embodiment, because the front-end interface chip can directly be accessed SSD by dma mode, therefore, the internal memory of described connection data control chip can not arrange.
The type of the SSD array that forms due to SSD also has a variety of, for example,, if according to the mode of data protection, divide, generally can be divided into three classes: unprotect, mirror image protection, verification protection; For example, RAID-0 belongs to the unprotect type; RAID-1, RAID-10 belong to mirror image protection type, namely by with many parts of data Replicas to different physical mediums such as different array control units provides data protection; RAID-5, RAID-6 belong to verification protection type, namely by the data check mode, provide data protection.Below will introduce respectively under the data protection mode of above-mentioned three types; the Data Control chip is how to control data transmission between front-end interface chip and SSD; 401,402 etc. only be used for each processing is distinguished in description, its execution sequence do not limited.
Fig. 4 is the unprotect schematic flow sheet of another embodiment of data processing method of the present invention, as shown in Figure 4, can comprise:
401, the front-end interface chip obtains data and the first corresponding address information that will write SSD from service server, and this first address information is sent to the Data Control chip;
Wherein, between front-end interface chip and service server, generally by SCSI (Small Computer System Interface, small computer system interface, being kind of an interface bus, possessing with polytype peripheral hardware and communicate) agreement carries out data interaction; The front-end interface chip receives the business datum that will write SSD after handling protocol interaction with service server from service server, these data are called the first data; This front-end interface chip also receives the first address information corresponding to this business datum, described the first address information is used for expression will write the address of the described business datum of solid-state hard disk SSD, this first address information for example comprises start address and the length that will write, such as the start address of wanting data writing is 120, length is 8; This 120 is signs of the sector on SSD, and described 88 sectors of expression, namely start data writing from the sector that sign is 120, and write continuously 8 sectors.
The front-end interface chip can be sent to the Data Control chip with this first address information.
402, the Data Control chip obtains the second address information according to the first address information, and described the second address information is used for representing that described the first address information is in position corresponding to solid-state hard disk SSD;
Wherein, the Data Control chip can, according to described the first address information, obtain be used for corresponding with described the first address information and store the second address information of the SSD of described data; For example, for the SSD array that is comprised of a plurality of SSD, it is to be positioned on which SSD that this second address information is actually 8 sectors since 120 described in expression above-mentioned 401, and is which position that is positioned at SSD.
Concrete, be provided with the striping rule in the Data Control chip, the storage space of a plurality of SSD in the SSD array can be divided into several bands according to this striping rule, each band is that the part by each SSD is combined to form, and the part of each SSD that described each band is included comprises again a plurality of sectors.The Data Control chip can be according to the first address information that obtains and this striping rule, and calculating this business datum that will write by which SSD be received, and is which the sector reception by this SSD.For example, the above-mentioned sector from sign is 120 starts data writing and writes continuously 8 sectors, namely be equivalent to and will write in these 8 sectors that sector mark is 120～127, it is first SSD that are arranged in the SSD array that the Data Control chip just can calculate these 8 sectors, and be to be arranged on first band of this first SSD, the positional information of this first SSD and first band just is called the second address information.
403, the Data Control chip is sent to described front-end interface chip with described the second address information;
Wherein, the second address information corresponding to SSD that is used for writing business datum that the Data Control chip will obtain, be sent to the front-end interface chip than the information such as particular location on SSD described above address and SSD.
404, the front-end interface chip writes described the first data with the direct memory access dma mode to SSD corresponding to described the second address information;
Wherein, what adopt due to the present embodiment is the character device access mode, thus the front-end interface chip after receiving the second address information that the Data Control chip sends, the business datum that will write directly writes in corresponding SSD.In this case, the Data Control chip can not arrange the internal memory that is connected.
In the present embodiment, be connected by the Data Control chip between front-end interface chip and SSD, even therefore the front-end interface chip is directly accessed SSD, the transmission of data still will be passed through the Data Control chip; And data are to transmit by the PCI-E passage in this chip by the transmission of Data Control chip, and the PCI-E interface of process Data Control chip enters chip, and through the PCI-E interface that is connected with SSD, transfers to SSD.
Above-mentioned step 401-404 is described the process that the first data write SSD, below by step 405-408, the process that reads the second data from SSD is described:
405, obtain from service server will be from the first address information corresponding to the second data that SSD reads for the front-end interface chip, and this first address information is sent to the Data Control chip;
Wherein, when service server will read business datum from SSD, can, with the first address information notice front-end interface chip of data, comprise address and the length of data; The front-end interface chip can be sent to the Data Control chip with this first address information.
406, the Data Control chip obtains the second address information according to the first address information, and described the second address information is used for representing that described the first address information is in position corresponding to solid-state hard disk SSD;
Wherein, the Data Control chip can, according to described the first address information, obtain be used for corresponding with described the first address information and store the second address information of the SSD of described data.Equally, the Data Control chip is also that calculating the business datum that will read be provided by which SSD, and obtains the address of these SSD and read position, can be called the second address information according to pre-stored striping rule and the first address information.
407, the Data Control chip is sent to described front-end interface chip with described the second address information;
408, the front-end interface chip is with the direct memory access dma mode, and corresponding SSD reads the second data from described the second address information;
Wherein, what adopt due to the present embodiment is the character device access mode, so the front-end interface chip will directly read described business datum and be passed to service server from the SSD of correspondence after receiving the second address information that the Data Control chip sends.
The character device access mode of the present embodiment,, owing to being that the front-end interface chip is directly accessed SSD, can reduce whole IO path greatly, also can promote the IOPS performance of this array control unit.
Fig. 5 is the mirror image protection schematic flow sheet of another embodiment of data processing method of the present invention, this Fig. 5 only shows the step that distinguishes with Fig. 4 flow process, and the difference with respect to step corresponding in Fig. 4 is illustrated to each step respectively, and for identical step, at Fig. 5, does not illustrate; Concrete:
501, in the time the first data will being write SSD, the Data Control chip, according to first address information corresponding to the first data that will write, obtains the second corresponding address information;
Wherein, the difference of this step and 402 steps is, the Data Control chip when calculating the second address information of SSD, can not count mirror image SSD, and SSD corresponding to the second address information that namely obtains can not be mirror image SSD.This mirror image SSD is the SSD that is connected with another array control unit of being connected of data image control chip in Fig. 3.
502, the front-end interface chip writes described the first data with the direct memory access dma mode to SSD corresponding to described the second address information; And the Data Control chip carries out image copying to described data, and the data of image copying are sent to mirror image SSD;
Wherein, the difference of this step and 404 steps is; in the time will writing the described Data Control chip of business datum process of SSD; in order to improve the safe reliability of data storages, can recover from mirror image data while guaranteeing therein a storage data fault, the Data Control chip will be according to pre-stored mirror image rule; described business datum is carried out image copying; be about to many parts of data Replicas, write respectively in mirror image SSD, thereby realize the mirror image defencive function.
503, in the time will reading the second data from SSD, the Data Control chip, according to first address information corresponding to the second data that will read, obtains the second corresponding address information;
Wherein, the difference of this step and 406 steps is, the Data Control chip when calculating the second address information of SSD, can count mirror image SSD, and SSD corresponding to the second address information that namely obtains is likely also mirror image SSD.For example, when the SSD that connects when this Data Control chip broke down, it can select a certain SSD in mirror image SSD that data are provided according to the mirror image rule, and the strategy of selection can be to select wherein relatively not busy SSD, can be also random selection.
504, the front-end interface chip is with the direct memory access dma mode, and corresponding SSD reads described the second data from described the second address information;
Wherein, the difference of this step and 408 steps is, if what the Data Control chip returned to the front-end interface chip in 503 is the second address information corresponding to mirror image SSD, the front-end interface chip in this step is directly from the mirror image SSD reading out data of correspondence with dma mode.
Fig. 6 is the verification protection schematic flow sheet of another embodiment of data processing method of the present invention, this Fig. 6 only shows the step that distinguishes with Fig. 4 flow process, and the difference with respect to step corresponding in Fig. 4 is illustrated to each step respectively, and for identical step, at Fig. 6, does not illustrate; Concrete:
601, in the time the first data will being write SSD, the front-end interface chip writes described data with the direct memory access dma mode to SSD corresponding to described the second address information; And the Data Control chip carries out check information to described data and calculates, and check information is write verification SSD;
Wherein, the difference of this step and 404 steps is, in the time writing the described Data Control chip of described first data transmission process of described SSD, the Data Control chip will carry out check information to described the first data and calculate, obtain check information, and described check information is write verification SSD in described SSD; This verification SSD is used for the equipment of storage check information in the SSD array, thereby realizes the verification protection of the first data.
In addition,, because the data that will write can be divided exactly by the size of band, so do not exist, do not write the punishment phenomenon, direct calculation check and yet being fine, this verification and also referred to as check information.
602, in the time will reading the second data from SSD, the Data Control chip, according to first address information corresponding to the second data that will read, obtains the second corresponding address information;
Wherein, the difference of this step and 406 steps is, for example, when certain SSD in the SSD that this Data Control chip connects breaks down, if the second data that the Data Control chip is found to read are just on this SSD that breaks down, this moment, the Data Control chip can, according to data or the information (for example check information) of all the other SSD storages that still work, just can recover second data that will read, and the second data that will recover be stored on certain normal SSD.Data Control chip forward end interface chip returns to SSD corresponding to the second address information and is the SSD of these recovery of stomge data.
Embodiment three
The support of the main data of description control chip of the present embodiment to the block device access mode, illustrate the data transmission procedure between block device access mode lower front end interface chip and SSD.In this manner, the data transmission flow process can be referring to the flow arrows shown in Fig. 3 (shown in Fig. 3 be to write flow process), this moment, the Data Control chip was to need to connect internal memory, be used for the buffer memory business datum, also can embed a Memory Controller Hub in the Data Control chip, be used for controlling the transmission of data to internal memory.
Fig. 7 is the schematic flow sheet of the another embodiment of data processing method of the present invention, the present embodiment is for the treatment scheme under the block device access mode, the step identical with treatment scheme under the character device access mode repeats no more, and different treatment steps only is described, comprising:
701, the front-end interface chip obtains the first data and the first corresponding address information that will write SSD from service server; And the first data transmission that the front-end interface chip will obtain to the internal memory with the Data Control chip is connected, is sent to the Data Control chip with the first address information;
Wherein, the front-end interface chip of the present embodiment can with the mode of DMA with first data transmission to the internal memory with the Data Control chip is connected, as shown in the arrow line of Fig. 3, these first data are also first by the PCI-E interface, to transfer to the Data Control chip, transfer to internal memory after the Data Control chip.
Optionally, if take the mirror image protection, when the first data process Data Control chip, the Data Control chip can carry out image copying to these the first data, and the first data of image copying is sent to the mirror image SSD of adjacent array control unit.
Optionally, if take the verification protection, when the first data process Data Control chip, the Data Control chip can carry out check information to these the first data and calculate, and obtains check information.
702, the Data Control chip, according to the first address information, obtains the second corresponding address information;
703, the Data Control chip obtains described the first data from the internal memory that is connected, and according to described the second address information, described the first data is write corresponding described SSD;
In the present embodiment, be, by Data Control chip oneself, the first data are write SSD, the Data Control chip also will carry out relevant treatment such as band fractionation etc. to these the first data.
Optionally, if take the verification protection, the Data Control chip also will be sent to the check information that calculates check SSD in this step.
704, the first data of buffer memory in Data Control chip deletion internal memory;
Wherein, the Data Control chip after the first data integrity is write SSD, data cached in the internal memory that the Data Control chip is connected deletion;
Optionally; if take the mirror image protection; the Data Control chip can first send a command to the adjacent array controller that is connected with the data image control chip in this step; the first data of buffer memory in this adjacent array controller of indication deletion, and then delete data cached in local direct-connected internal memory.
705, obtain from service server will be from the first address information corresponding to the second data that SSD reads for the front-end interface chip, and this first address information is sent to the Data Control chip;
706, the Data Control chip, according to the first address information, obtains the second corresponding address information;
707, the Data Control chip reads described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip;
708, the front-end interface chip, with the direct memory access dma mode, reads described the second data by described Data Control chip from described internal memory.
Embodiment four
Fig. 8 is the structural representation of Data Control chip one embodiment of the present invention, this Data Control chip can be carried out the method for any embodiment of the present invention, as shown in Figure 8, this Data Control chip can comprise: information receiving unit 81, information process unit 82 and transmission control unit 83; Wherein,
Further, described transmission control unit 83, concrete being used for is sent to described front-end interface chip with described the second address information, so that described front-end interface chip, by the PCI-E interface of described Data Control chip, writes described the first data or reads described the second data SSD corresponding to described the second address information with the direct memory access dma mode.
Further, described transmission control unit 83, concrete being used for obtained described the first data from the internal memory that is connected with described Data Control chip, and according to described the second address information, described the first data being write corresponding described SSD, described the first data are that described front-end interface chip transfers to described internal memory by described Data Control chip; Perhaps, read described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip, so that described front-end interface chip reads described the second data by described Data Control chip from described internal memory.
Fig. 9 is the structural representation of another embodiment of Data Control chip of the present invention, and as shown in Figure 9, on the basis of structure shown in Figure 8, the Data Control chip of the present embodiment can also comprise:
Mirror image protected location 84; be used in the time writing the described Data Control chip of described first data transmission process of described SSD; described Data Control chip carries out image copying with described data, and the data of image copying are sent to the mirror image SSD that is connected with described Data Control chip.
Further; can also comprise: verification protected location 85; be used at the described first data transmission that will write described SSD during through described Data Control chip, described Data Control chip carries out check information to described data and calculates, and described check information is write verification SSD in described SSD.
The structure of above data processing method to the embodiment of the present invention and Data Control chip is illustrated; therefrom can see; the Data Control integrated chip of the embodiment of the present invention functions processed of PCI-E exchange and RAID data; for example as above; it is to be connected by the PCI-E interface that this Data Control chip is connected with SSD with the front-end interface chip, and this chip can also carry out the processing such as address translation, data protection between the first address information and the second address information.
After the function of the exchange of the PCI-E with above-mentioned and the processing of RAID data was integrated in the Data Control chip, this two parts function was mutually to support in concrete enforcement; Such as, after the RAID Data processing relates to the processing such as address translation or data image, to carry out data transmission according to the address result after conversion or the data after mirror image, the functional module that the RAID data are processed can be with the functional module of its result notice PCI-E exchange, the address result by the functional module of PCI-E exchange after according to above-mentioned conversion or the data after mirror image are transmitted in the PCI-E mode.
And the function that PCI-E exchange and RAID data are processed is integrated in the Data Control chip, has following many benefits:
For example, all be positioned at the inside of Data Control chip due to functional module and the functional module of RAID data processing of PCI-E exchange, belong to the communication of chip internal, just can communicate alternately by privately owned host-host protocol between the two, communication efficiency is higher; And, compare the function that mode that two kinds of functional modules lay respectively at two chips can not take the PCI-E exchange yet, make the PCI-E function of exchange all for the data transmission between front-end interface chip and SSD, (two kinds of functional modules lay respectively in the mode of two chips to help to improve data transmission efficiency, described two chips must pass through the PCI-E protocol communication, the function of exchange that this will consume PCI-E major part, make the data transmission efficiency between front-end interface chip and SSD descend).
Again for example, the function that PCI-E exchange and RAID data are processed is integrated in the Data Control chip, just can share some functions or storage unit etc., such as, data buffer storage unit, data computing function, debug function etc., namely in this Data Control chip, a data buffer unit just can be set, both can be used for the buffer memory of PCI-E exchange, also can be used for the buffer memory of RAID Data processing.The aspects such as the cost of this Data Control chip, hardware arrangement, power consumption, heat radiation have obtained saving and have descended like this.
Again for example, the function that PCI-E exchange and RAID data are processed is integrated in the Data Control chip, also improved the Function Extension ability of this Data Control chip, the problem that makes this Data Control chip may run in the application facet of the SSD for the PCI-E interface provides the chance that solves; Such as, the SSD of PCI-E interface is when running into the violence hot plug, the operation if the Data Control chip abends, can improve this problem that solves by the function that the RAID data are processed; But suppose that this chip only has the PCI-E function of exchange, the problems referred to above just can't solve, and have a strong impact on the normal operation of memory device.
Embodiment five
The present embodiment provides a kind of solid-state storage array control unit, comprising: any described Data Control chip of front-end interface chip, solid-state hard disk SSD and the present invention; Described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by the PCI-E interface.
For example,, referring to Fig. 3, be a kind of optional solid-state storage array control unit structure, this solid-state storage array control unit also comprises: mirror image SSD; Described Data Control chip is by PCI-E interface and described mirror image SSD communication connection; Described mirror image SSD, be used for from the data of described Data Control chip reception image copying.This solid-state storage array control unit also comprises: internal memory; Described Data Control chip is by PCI-E interface and described Memory linkage; Described internal memory, be used for receiving the first data from described front-end interface chip, so that described Data Control chip obtains described the first data from described internal memory, writes described SSD; Perhaps, receive the second data that read from described SSD from described Data Control chip, so that described front-end interface chip obtains described the second data from described internal memory.
Need to prove, Fig. 3 is a kind of optional solid-state storage array control unit structure, can change in concrete enforcement, for example, Data Control chip shown in Figure 3 is directly with the front-end interface chip, to be connected, can also a PCI-E exchange chip be set between Data Control chip and front-end interface chip, make the front-end interface chip be connected with the Data Control chip by this PCI-E exchange chip; In addition, this Data Control chip also can connect the structures such as a plurality of PCI-E exchange chips.
The solid-state storage array control unit of the present embodiment,, owing to having adopted the Data Control chip with PCI-E interface, improved the IOPS ability of this array control unit, adapted to the performance requirement of SSD array; And; with respect to traditional array control unit; the array control unit of the present embodiment with PCI-E function of exchange and ARRAY PROCESSING function for example data protection process that to be integrated in a chip be on the Data Control chip, simplified greatly the structure of array control unit, simplified the cost of array control unit.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be completed by the hardware that programmed instruction is correlated with, aforesaid program can be stored in a computer read/write memory medium, this program when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that finally: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to aforementioned each embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (13)
1. a data processing method, is characterized in that, comprising:
The Data Control chip obtains the first address information from the front-end interface chip, and described the first address information is used for indicating to write the address of the first data or the address that will read the second data;
Described Data Control chip obtains the second address information according to described the first address information, described the second address information is for representing described the first address information in position corresponding to solid-state hard disk SSD, and described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by PCI Express (PCI-E) interface;
Described Data Control chip is by described PCI-E interface, described the first data of transmission or the second data between the described front-end interface chip SSD corresponding with described the second address information, so that will write from described the first data that described front-end interface chip receives described SSD or from described SSD, read described the second data transmission to described front-end interface chip.
2. data processing method according to claim 1, it is characterized in that, described Data Control chip is by described PCI-E interface, and described the first data of transmission or described the second data between the described front-end interface chip SSD corresponding with described the second address information comprise:
Described Data Control chip is sent to described front-end interface chip with described the second address information, so that described front-end interface chip, by the PCI-E interface of described Data Control chip, writes described the first data or reads described the second data SSD corresponding to described the second address information with the direct memory access dma mode.
3. data processing method according to claim 1, it is characterized in that, described Data Control chip is by described PCI-E interface, and described the first data of transmission or described the second data between the described front-end interface chip SSD corresponding with described the second address information comprise:
Described Data Control chip obtains described the first data from the internal memory with described Data Control chip is connected, and according to described the second address information, described the first data being write corresponding described SSD, described the first data are that described front-end interface chip transfers to described internal memory by described Data Control chip;
Perhaps, described Data Control chip reads described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip, so that described front-end interface chip reads described the second data by described Data Control chip from described internal memory.
4. according to claim 1～3 arbitrary described methods, is characterized in that, described described the first data or the second data transmitted between the described front-end interface chip SSD corresponding with described the second address information comprise:
In the time writing the described Data Control chip of described first data transmission process of described SSD, described Data Control chip carries out image copying with described data, and the data of image copying are sent to the mirror image SSD that is connected with described Data Control chip.
5. according to claim 1～3 arbitrary described methods, is characterized in that, described described the first data or described the second data transmitted between the described front-end interface chip SSD corresponding with described the second address information comprise:
During through described Data Control chip, described Data Control chip carries out check information to described data and calculates at the described first data transmission that will write described SSD, and described check information is write verification SSD in described SSD.
6. a Data Control chip, is characterized in that, comprising:
Information receiving unit, be used for obtaining the first address information from the front-end interface chip, and described the first address information is used for indicating to write the address of the first data or the address that will read the second data;
Information process unit, be used for obtaining the second address information according to described the first address information, described the second address information is for representing described the first address information in position corresponding to solid-state hard disk SSD, and described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by PCI Express (PCI-E) interface;
Transmission control unit, be used for by described PCI-E interface, described the first data of transmission or the second data between the described front-end interface chip SSD corresponding with described the second address information, so that will write from described the first data that described front-end interface chip receives described SSD or from described SSD, read described the second data transmission to described front-end interface chip.
7. Data Control chip according to claim 6, is characterized in that,
Described transmission control unit, concrete being used for is sent to described front-end interface chip with described the second address information, so that described front-end interface chip, by the PCI-E interface of described Data Control chip, writes described the first data or reads described the second data SSD corresponding to described the second address information with the direct memory access dma mode.
8. Data Control chip according to claim 6, is characterized in that,
Described transmission control unit, concrete being used for obtained described the first data from the internal memory that is connected with described Data Control chip, and according to described the second address information, described the first data being write corresponding described SSD, described the first data are that described front-end interface chip transfers to described internal memory by described Data Control chip;
Perhaps, read described the second data according to described the second address information from the described SSD of correspondence, and with described the second data transmission to the internal memory that is connected with described Data Control chip, so that described front-end interface chip reads described the second data by described Data Control chip from described internal memory.
9. according to claim 6～8 arbitrary described Data Control chips, is characterized in that, also comprises:
The mirror image protected location; be used in the time writing the described Data Control chip of described first data transmission process of described SSD; described Data Control chip carries out image copying with described data, and the data of image copying are sent to the mirror image SSD that is connected with described Data Control chip.
10. according to claim 6～8 arbitrary described Data Control chips, is characterized in that, also comprises:
The verification protected location, be used at the described first data transmission that will write described SSD during through described Data Control chip, and described Data Control chip carries out check information to described data and calculates, and described check information is write verification SSD in described SSD.
11. a solid-state storage array control unit, is characterized in that, comprising: the arbitrary described Data Control chip of front-end interface chip, solid-state hard disk SSD and claim 6～10;
Described Data Control chip is connected with the front-end interface chip communication with described SSD respectively by the PCI-E interface.
12. solid-state storage array control unit according to claim 11, is characterized in that, also comprises: mirror image SSD; Described Data Control chip is by PCI-E interface and described mirror image SSD communication connection;
Described mirror image SSD, be used for from the data of described Data Control chip reception image copying.
13. solid-state storage array control unit according to claim 11, is characterized in that, also comprises: internal memory; Described Data Control chip is by PCI-E interface and described Memory linkage;
Described internal memory, be used for receiving the first data from described front-end interface chip, so that described Data Control chip obtains described the first data from described internal memory, writes described SSD; Perhaps, receive the second data that read from described SSD from described Data Control chip, so that described front-end interface chip obtains described the second data from described internal memory.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105975358A (en) * | 2016-05-03 | 2016-09-28 | 深圳市杉岩数据技术有限公司 | Fault-tolerant method and system based on SCSI equipment |
| CN106326138A (en) * | 2015-07-03 | 2017-01-11 | 比亚迪股份有限公司 | Flash memory and access control method for data in flash memory |
| CN108121600A (en) * | 2016-11-30 | 2018-06-05 | 中兴通讯股份有限公司 | Disk array controller, input and output I/O data processing method and processing device |
| WO2018137529A1 (en) * | 2017-01-26 | 2018-08-02 | 华为技术有限公司 | Data transmission method, device, apparatus, and system |
| CN109032513A (en) * | 2018-07-16 | 2018-12-18 | 山东大学 | Based on the RAID framework of SSD and HDD and its backup, method for reconstructing |
| CN109376104A (en) * | 2018-09-28 | 2019-02-22 | 阿里巴巴集团控股有限公司 | A kind of chip and the data processing method and device based on it |
| CN110209343A (en) * | 2018-07-23 | 2019-09-06 | 腾讯科技（深圳）有限公司 | Date storage method, device, server and storage medium |
| CN110928490A (en) * | 2019-10-28 | 2020-03-27 | 中国科学院上海微***与信息技术研究所 | Data storage method and device |
| CN111857580A (en) * | 2020-07-06 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Same writing method and device of distributed storage system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539894A (en) * | 2009-05-04 | 2009-09-23 | 成都市华为赛门铁克科技有限公司 | Method and device for accessing external equipment of computer into computer system |
| CN102591746A (en) * | 2011-12-29 | 2012-07-18 | 成都市华为赛门铁克科技有限公司 | Data reconstruction method and storage equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9128699B2 (en) * | 2008-12-22 | 2015-09-08 | Intel Corporation | Method and system for queuing transfers of multiple non-contiguous address ranges with a single command |
| CN102096560A (en) * | 2011-01-27 | 2011-06-15 | 浪潮电子信息产业股份有限公司 | Multi-path solid state disk acceleration method based on PCI-E interface |
| CN102360342A (en) * | 2011-10-11 | 2012-02-22 | 中国人民解放军国防科学技术大学 | Solid state disk for rapidly storing and displaying massive image data |
-
2012
- 2012-12-19 CN CN2012800032891A patent/CN103403667A/en active Pending
- 2012-12-19 WO PCT/CN2012/086928 patent/WO2014094250A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539894A (en) * | 2009-05-04 | 2009-09-23 | 成都市华为赛门铁克科技有限公司 | Method and device for accessing external equipment of computer into computer system |
| CN102591746A (en) * | 2011-12-29 | 2012-07-18 | 成都市华为赛门铁克科技有限公司 | Data reconstruction method and storage equipment |
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|---|---|---|---|---|
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| CN105975358B (en) * | 2016-05-03 | 2019-02-26 | 深圳市杉岩数据技术有限公司 | A kind of fault-tolerance approach and system based on scsi device |
| CN108121600A (en) * | 2016-11-30 | 2018-06-05 | 中兴通讯股份有限公司 | Disk array controller, input and output I/O data processing method and processing device |
| CN108121600B (en) * | 2016-11-30 | 2022-11-29 | 中兴通讯股份有限公司 | Disk array controller, input/output (IO) data processing method and device |
| WO2018137529A1 (en) * | 2017-01-26 | 2018-08-02 | 华为技术有限公司 | Data transmission method, device, apparatus, and system |
| US10810135B2 (en) | 2017-01-26 | 2020-10-20 | Huawei Technologies Co., Ltd. | Data transmission method, apparatus, device, and system |
| CN109032513A (en) * | 2018-07-16 | 2018-12-18 | 山东大学 | Based on the RAID framework of SSD and HDD and its backup, method for reconstructing |
| CN109032513B (en) * | 2018-07-16 | 2020-08-25 | 山东大学 | RAID (redundant array of independent disks) architecture based on SSD (solid State disk) and HDD (hard disk drive) and backup and reconstruction methods thereof |
| CN110209343A (en) * | 2018-07-23 | 2019-09-06 | 腾讯科技（深圳）有限公司 | Date storage method, device, server and storage medium |
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| CN109376104B (en) * | 2018-09-28 | 2021-12-07 | 创新先进技术有限公司 | Chip and data processing method and device based on chip |
| CN109376104A (en) * | 2018-09-28 | 2019-02-22 | 阿里巴巴集团控股有限公司 | A kind of chip and the data processing method and device based on it |
| CN110928490A (en) * | 2019-10-28 | 2020-03-27 | 中国科学院上海微***与信息技术研究所 | Data storage method and device |
| CN110928490B (en) * | 2019-10-28 | 2021-08-17 | 中国科学院上海微***与信息技术研究所 | Data storage method and device |
| CN111857580A (en) * | 2020-07-06 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Same writing method and device of distributed storage system |
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