CN116594461A

CN116594461A - LDO regulating circuit, power management chip and LDO regulating method

Info

Publication number: CN116594461A
Application number: CN202310501241.3A
Authority: CN
Inventors: 李光强; 王红义
Original assignee: Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co ltd
Priority date: 2023-05-05
Filing date: 2023-05-05
Publication date: 2023-08-15

Abstract

The application discloses an LDO regulating circuit, a power management chip and an LDO regulating method, wherein the LDO regulating circuit comprises a power tube module, an error amplifying module, a buffer and a compensation module, the buffer is connected between a power end and a grounding end, the input end of the buffer is connected with the amplifying output end of the error amplifying module, the output end of the buffer is connected with the power tube module, the buffer is used for separating a primary pole and a secondary pole, the primary pole is arranged at a voltage output end, the secondary pole is arranged at the amplifying output end of the error amplifying module, the compensation module is connected with the amplifying output end of the error amplifying module, and the compensation module is used for adjusting the pole frequency of the secondary pole according to the magnitude of load current when the load current flowing through the power tube module is smaller than a current limiting threshold. In the design, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current so as to enable the pole frequency of the secondary pole to be far away from the pole frequency of the main pole, thereby improving the stability of the LDO loop.

Description

LDO regulating circuit, power management chip and LDO regulating method

Technical Field

The application relates to the technical field of low-voltage linear voltage regulators, in particular to an LDO (Low dropout regulator) regulating circuit, a power management chip and an LDO regulating method.

Background

LDOs (low dropout linear regulators, low Dropout Regulator) can operate to linearly step down in the range of several hundred millivolts between the input voltage and the output voltage.

LDOs are classified into two types, fully integrated and off-chip capacitors, and for LDOs with off-chip capacitors, the main pole point is usually set at the voltage output terminal and the secondary pole point is usually set at the output terminal of the error amplifier.

However, in the related art, under a heavy load condition, the main pole frequency of the LDO with the off-chip capacitor is close to the secondary pole frequency, which results in poor stability of the LDO with the off-chip capacitor, and if the stability of the LDO is improved by increasing the capacity of the off-chip capacitor, on one hand, the loop bandwidth is reduced, and on the other hand, the cost is increased. Therefore, how to effectively improve the stability of the LDO with off-chip capacitor under a heavy load condition has become a problem to be solved.

Disclosure of Invention

The embodiment of the application provides an LDO (low dropout regulator) regulating circuit, a power management chip and an LDO regulating method, which can solve the problem of poor stability of an LDO with an off-chip capacitor under the condition of heavy load in the related technology.

In a first aspect, an embodiment of the present application provides an LDO regulation circuit; the LDO regulating circuit comprises a power tube module, an error amplifying module, a buffer and a compensation module, wherein the power tube module is connected with a power end, the power tube module is provided with a voltage output end, the voltage output end is used for being connected with an external load, the error amplifying module is connected between the power end and a grounding end, the buffer is connected between the power end and the grounding end, the input end of the buffer is connected with an amplifying output end of the error amplifying module, the output end of the buffer is connected with the power tube module, the buffer is used for separating a primary pole point and a secondary pole point, the primary pole point is arranged at the voltage output end, the secondary pole point is arranged at the amplifying output end of the error amplifying module, the compensation module is connected with the amplifying output end of the error amplifying module, and the compensation module is used for adjusting the pole frequency of the secondary pole point according to the magnitude of a load current when the load current flowing through the power tube module is smaller than a current limiting threshold.

According to the LDO regulating circuit provided by the embodiment of the application, when the load current flowing through the power tube module is larger and smaller than the current limiting threshold value, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole is gradually far away from the pole frequency of the main pole, and the stability of an LDO loop is improved.

In a second aspect, an embodiment of the present application provides a power management chip, where the circuit management chip includes the LDO regulator circuit described above.

Based on the power management chip provided with the LDO regulating circuit, when the load current flowing through the power tube module is larger and smaller than the current limiting threshold value, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current so as to gradually keep the pole frequency of the secondary pole away from the pole frequency of the main pole, thereby improving the stability of an LDO loop and improving the working stability of the power management chip when the load current is overlarge.

In a third aspect, an embodiment of the present application provides an LDO adjustment method applied to the LDO adjustment circuit of the first aspect and any implementation manner thereof, where the LDO adjustment method includes:

When the load current flowing through the power tube module is smaller than the current limiting threshold value, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current.

According to the LDO regulating method provided by the embodiment of the application, when the load current flowing through the power tube module is larger and smaller than the current limiting threshold value, the compensation module can regulate the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole is gradually far away from the pole frequency of the primary pole, and the stability of an LDO loop is improved.

In a fourth aspect, an embodiment of the present application provides a circuit board, on which an off-chip capacitor and a power management chip are soldered, and the off-chip capacitor is connected to a voltage output terminal of the power management chip.

Based on the circuit board provided with the power management chip, when the load current flowing through the power tube module is larger and smaller than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current so as to gradually keep the pole frequency of the secondary pole away from the pole frequency of the main pole, thereby improving the stability of the LDO loop, and further improving the working stability of the circuit board when the load current is overlarge.

In a fifth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a housing and the circuit board, and the housing has a receiving cavity, and the circuit board is disposed in the receiving cavity.

According to the electronic equipment provided with the circuit board, when the load current flowing through the power tube module is larger and smaller than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the load current, so that the pole frequency of the secondary pole is gradually far away from the pole frequency of the main pole, the stability of an LDO loop is improved, and the working stability of the electronic equipment when the load current is overlarge is improved.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application and that other drawings may be obtained from them without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an LDO regulating circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an LDO regulating circuit according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a LDO regulating circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a portion of the LDO regulating circuit in FIG. 3;

FIG. 5 is a schematic diagram of a structural framework of an LDO regulating circuit according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a structural framework of an LDO regulating circuit according to another embodiment of the present application;

FIG. 7 is a schematic diagram of the rest of the LDO regulating circuit in FIG. 3;

FIG. 8 is a flow chart of an LDO adjustment method according to an embodiment of the application.

Reference numerals: 10. a power tube module; MP, the first power tube; MS, the second power tube; 20. error ofAn amplifying module; EA. An error amplifier; 21. a flow-limiting element; buffer, buffer; 30. a compensation module; 40. a current limiting module; 50. a feedback module; r is R _F1 A first feedback resistor; r is R _F2 A second feedback resistor; MP1, a first PMOS tube; MP2, the second PMOS tube; MP3, third PMOS tube; MP4, a fourth PMOS tube; MP5, a fifth PMOS tube; MP6, sixth PMOS tube; MP7, seventh PMOS tube; MP8, eighth PMOS tube; MP9 and a ninth PMOS tube; MP10, tenth PMOS tube; MP11 and eleventh PMOS tube; MP12, twelfth PMOS tube; MN1, a first NMOS tube; MN2, a second NMOS tube; MN3, a third NMOS tube; MN4, a fourth NMOS tube; MN5, a fifth NMOS tube; MN6, a sixth NMOS tube; MN7, a seventh NMOS tube; MN8, eighth NMOS transistor; MN9, ninth NMOS transistor; MN10, tenth NMOS transistor; MN11, eleventh NMOS transistor; MN12, twelfth NMOS transistor; MN13, thirteenth NMOS transistor; r is R ₁ A first resistor; r is R ₂ A second resistor; r is R ₃ A third resistor; c (C) ₁ A first capacitor; c (C) _L An off-chip capacitance; r is R _L Load resistance; r is R _S A first current limiting resistor; r is R _EF A second current limiting resistor; COMP, comparator; l (L) ₁ A first node; l (L) ₂ A second node; l (L) ₃ A third node; l (L) ₄ A fourth node; l (L) ₅ A fifth node; v (V) _OUT A voltage output terminal; v (V) _ref A reference voltage; i _D A current source; v (V) _DD A power supply end; GND, the ground terminal; p (P) ₁ A main pole point; p (P) ₂ Secondary pole points; p (P) ₃ Another pole.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Referring to fig. 1, a first aspect of the present application provides an LDO regulator circuit, which can effectively improve the stability of an LDO loop.

The LDO regulating circuit comprises a power tube module 10 and an error amplifying circuitModule 20, buffer and compensation module 30; power tube module 10 and power source terminal V _DD In connection, the power tube module 10 has a voltage output terminal V _OUT Voltage output terminal V _OUT For connecting an external load; the error amplifying module 20 is connected to the power terminal V _DD And the ground GND; the Buffer is connected to the power terminal V _DD Between the Buffer and the ground GND, the input end of the Buffer is connected with the amplifying output end of the error amplifying module 20, the output end of the Buffer is connected with the power tube module 10, and the Buffer is used for separating the main pole P ₁ And a secondary point P ₂ Main pole point P ₁ Is arranged at the voltage output terminal V _OUT Secondary point P ₂ An amplification output end of the error amplification module 20; the compensation module 30 is connected to the amplifying output end of the error amplifying module 20, and the compensation module 30 is configured to adjust the secondary pole P according to the magnitude of the load current when the load current flowing through the power tube module 10 is less than the current limiting threshold ₂ Pole frequency of (c).

The following describes the specific circuit structure of the LDO regulator circuit in conjunction with fig. 1-7.

As shown in fig. 1, the LDO regulator circuit includes a power tube module 10, an error amplifying module 20, a Buffer and a compensation module 30.

The power tube module 10 serves as a circuit structure for connecting with an external load to supply an output voltage to the external load.

The power tube module 10 has a voltage input terminal and a voltage output terminal V _OUT . The voltage input end of the power tube module 10 is a port of the power tube module 10 for inputting voltage, and the voltage input end of the power tube module 10 and the power supply end V _DD Is connected to receive an input voltage from an external power source. Voltage output V of power tube module 10 _OUT "is the port for the output voltage to be output out of the power tube module 10, the voltage output end V of the power tube module 10 _OUT For connecting an external load to provide an output voltage to the external load.

The LDO regulation circuit further includes a feedback module 50, where the feedback module 50 is capable of generating a feedback voltage according to the output voltage.

One end of the feedback module 50 is connected with the voltage output end V of the power tube module 10 _OUT The other end of the feedback module 50 is connected to the ground GND, i.e. the feedback module 50 is connected in series with the power tube module 10 and connected to the power supply terminal V _DD And the ground GND.

The feedback module 50 has a feedback output for outputting a feedback voltage. As shown in fig. 2, in particular, the feedback module 50 may include a first feedback resistor R _F1 And a second feedback resistor R _F2 A first feedback resistor R _F1 And the voltage output terminal V of the power tube module 10 _OUT A first feedback resistor R connected to _F1 And a second feedback resistor R _F2 A first end of the second feedback resistor R _F2 A second end of the resistor is connected with the ground end GND, and a first feedback resistor R _F1 And a second feedback resistor R _F2 The node formed between the first ends of (a) may serve as a feedback output. The feedback voltage is the output voltage at the first feedback resistor R _F1 And a second feedback resistor R _F2 And partial pressure.

As shown in fig. 1, the error amplifying module 20 is configured to convert the feedback voltage to a reference voltage V _ref A comparison is made and a corresponding error signal is generated. The error amplifying module 20 is connected to the power terminal V _DD And the ground GND. The specific circuit configuration of the error amplification module 20 will be described below.

The error amplification module 20 has a first amplification input, a second amplification input, and an amplification output.

A first amplifying input terminal for accessing a reference voltage V _ref The second amplification input end is connected with the feedback output end to be connected with the feedback voltage. The error amplifying module 20 combines the feedback voltage with the reference voltage V _ref The comparison generates an error signal, the error amplifying module 20 amplifies the error signal, and the amplified error signal is output from the amplifying output terminal.

The Buffer is capable of processing the amplified error signal and delivering the processed error signal to the power tube module 10. Buffering mechanism The Buffer of the flushing device is connected with a power supply end V _DD And the ground GND.

The input end of the Buffer is connected to the amplifying output end of the error amplifying module 20 (and connected to the first node L ₁ ) The output end of the Buffer is connected with the power tube module 10. The amplified error signal enters from the input end of the Buffer, is processed by the Buffer, is output from the output end of the Buffer and is transmitted to the power tube module 10, and the power tube module 10 adjusts the voltage output end V according to the error signal _OUT Thereby forming a negative feedback loop.

Specifically, as shown in fig. 3, the Buffer may include a third resistor R ₃ An eleventh PMOS tube MP11 and a twelfth PMOS tube MP12; third resistor R ₃ A third resistor R connected to the power supply terminal VDD ₃ The second end of the eleventh PMOS tube MP11 is connected with the source electrode of the eleventh PMOS tube MP11, the drain electrode of the eleventh PMOS tube MP11 is connected with the ground end GND, the grid electrode of the eleventh PMOS tube MP11 is used as the input end of the Buffer and is connected with the first node L ₁ Connecting; the drain electrode of the twelfth PMOS tube MP12 is short-circuited with the grid electrode of the twelfth PMOS tube MP12, and the source electrode of the twelfth PMOS tube MP12 is connected with the power supply end V _DD The drain electrode of the twelfth PMOS tube MP12 is connected with the third resistor R ₃ Is connected with the second end of the first connecting piece; the grid electrode of the twelfth PMOS tube MP12 is used as the output end of the Buffer and is connected with the grid electrode of the first power tube MP.

Buffer for separating main pole P of LDO regulating circuit ₁ And a secondary point P ₂ Main pole point P ₁ Is arranged at the voltage output terminal V _OUT Secondary point P ₂ Is provided at the amplified output of the error amplification module 20.

The voltage output terminal V _OUT As the main pole point P of the LDO regulating circuit ₁ When the load current flowing through the power tube module 10 is small, the dominant pole P ₁ The pole frequencies of (2) satisfy:

P ₁ ＝1/2π(R _F1 +R _F2 ||R _L )C _L - - - - -equation 1

Wherein R is _L Representing loadResistor R _L ，C _L Representing off-chip capacitance C _L 。

In order to meet the low power consumption design requirement of the LDO regulating circuit, a designer can pre-select the first feedback resistor R according to the requirement _F1 And a second feedback resistor R _F2 The resistance of (2) is designed to be very large. As the load current increases, the load resistance R _L Gradually decrease, when the load current is too large, the load resistance R _L Becomes very small and the load resistance R _L A first feedback resistor R _F1 And a second feedback resistor R _F2 The method meets the following conditions:

R _F1 +R _F2 >>R _L equation 2

By substituting the above "formula 2" into the above "formula 1", the following can be simplified:

P ₁ ’≈1/2πR _L C _L equation 3

By comparing the above-mentioned "formula 1" and the above-mentioned "formula 3", it can be derived that the main pole point P when the load current is excessive ₁ The pole frequency of (c) is pushed higher.

It can be appreciated that when the load current is too large, the dominant pole P ₁ When the pole frequency of (2) is increased, the main pole P ₁ The pole frequency of (2) gradually approaches the secondary pole P ₂ And the main pole P ₁ Pole frequency and secondary pole P of (2) ₂ The close pole frequency of (c) may reduce the stability of the LDO loop.

The compensation module 30 adjusts the secondary pole P according to the magnitude of the load current ₂ The compensation module 30 is connected with the amplifying output end of the error amplifying module 20. The specific circuit configuration of the compensation module 30 will be described below.

The compensation module 30 is configured to adjust the secondary pole P according to the magnitude of the load current when the load current flowing through the power tube module 10 is less than the current limiting threshold ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And thus improves the stability of the LDO loop.

It is necessary to say thatIt is clear that the specific value of the current limiting threshold is not limited here, the current limiting threshold is set according to the specific application condition of the LDO regulating circuit, and a designer can set different values according to different application conditions. It should be noted that, when the load current flowing through the power tube module 10 is less than the current limiting threshold, the compensation module 30 adjusts the secondary pole P according to the magnitude of the load current ₂ The pole frequency of (c) will extend throughout the operation of the voltage loop.

According to the LDO regulating circuit in the embodiment of the application, when the load current flowing through the power tube module 10 is larger and smaller than the current limiting threshold, the compensation module 30 can adjust the secondary pole P according to the magnitude of the load current ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And thus improves the stability of the LDO loop. It should be noted that at the voltage output terminal V _OUT Connecting piece outer capacitance C _L When the chip external capacitor C _L It can also improve the stability of LDO loop, and the off-chip capacitor C _L The greater the capacity of the LDO loop, the greater the stability of the LDO loop, and since the compensation module 30 of the present application can also be used to improve the stability of the LDO loop, the present application is applied to the voltage output terminal V _OUT Connected off-chip capacitor C _L Is smaller (i.e. off-chip capacitance C _L ) Through compensation module 30 and voltage output terminal V _OUT Connected off-chip capacitor C _L The stability of the LDO loop is ensured through the cooperation of the LDO loop and the LDO loop; thus compared with the related art, the voltage output terminal V _OUT Connecting a large-capacity off-chip capacitor C _L It is also possible to reduce off-chip capacitance C _L And reduces the overall size of the power management chip.

Further, as shown in FIGS. 3-4, it will be appreciated that E _{Total (S)} ＝E ₁ *E ₂ *[gm*(R _L ||R _F1 +R _F2 )]Wherein E is _{Total (S)} For the total gain of the LDO loop, E ₁ Gain of error amplifying module 20, E ₂ For the gain of the Buffer, gm is the transconductance of the first power tube MP (described below) of the power tube module 10, due to R _F1 +R _F2 ＞＞R _L Therefore E _{Total (S)} ≈E ₁ *E ₂ *(gm*R _L ). Considering that the load resistance RL is smaller when the load current is larger, this results in the total gain E of the LDO loop _{Total (S)} And (3) lowering. Total gain E of LDO loop _{Total (S)} Reducing the overall gain E of the LDO loop, although the stability of the LDO loop can be improved _{Total (S)} The positive effect of the reduction is not enough to cancel the dominant pole P ₁ And a secondary point P ₂ The phase lag of (2) causes a negative impact of the reduced loop phase margin, so the overall stability of the LDO loop is still reduced. To enable the compensation module 30 to adjust the secondary pole P according to the magnitude of the load current when the load current is large and less than the current limit threshold ₂ To the pole frequency of the secondary pole point P ₂ Is far from the main pole P ₁ And thus improves the stability of the LDO loop. Therefore, in some embodiments, the compensation module 30 includes a first PMOS tube MP1 and a first resistor R ₁ The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the first PMOS tube MP1 is short-circuited with the grid electrode of the first PMOS tube MP1, and the source electrode of the first PMOS tube MP1 is connected with the power supply end V _DD Connecting; first resistor R ₁ A first end of the first resistor R is connected with the drain electrode of the first PMOS tube MP1 ₁ Is connected to the amplified output of the error amplifying module 20 (and is connected to the first node L ₁ )。

It can be appreciated that the amplified output of the error amplifying module 20 is used as the secondary point P of the LDO regulating circuit ₂ Without designing the first PMOS tube MP1 and the first resistor R ₁ At this time, the secondary pole P ₂ The pole frequencies of (2) satisfy:

P ₂ ＝1/2π(r _on,MP3 ||r _on,MN3 )C _L1 equation 4

Wherein r is _on,MP3 Representing the small signal impedance, r, of MP3 (a subcomponent of error amplifier module 20, described below) _on,MN3 Representing the impedance of MN3 (another sub-component of the error amplification block 20, described below), C _L1 Representing the first node L ₁ Is a parasitic capacitance of (a) in the capacitor.

According to the above "formula 3" and the above "formulaIt can be seen from FIG. 4 that when the load current is too large, the dominant pole P ₁ When the pole frequency of (2) is increased, the main pole P ₁ The pole frequency of (2) gradually approaches the secondary pole P ₂ Pole frequency (i.e. P ₁ ’≈P ₂ ) And the main pole point P ₁ Pole frequency and secondary pole P of (2) ₂ The close pole frequency of (c) may reduce the stability of the LDO loop.

However, the first PMOS transistor MP1 and the first resistor R are designed ₁ Then, at this time, the secondary pole P ₂ The pole frequencies of (2) satisfy:

P ₂ ＝1/2π(r _on,MP3 ||r _on,MN3 ||(1/g _m,MP1 +R ₁ ))C _L1 Equation 5

Wherein g _m,MP1 Represents the transconductance, R, of the first PMOS tube MP1 ₁ Representing the first resistance R ₁ 。

It should be noted that, in order to improve the stability of the LDO loop, a designer designs the LDO loop so that the impedance of MP3 is far greater than the reciprocal of the transconductance of the first PMOS transistor MP1 and the first resistor R ₁ Sum of the resistance values (i.e. r _on,MP3 ＞＞(1/g _m,MP1 +R ₁ ) A) is provided; and the impedance of MN3 is far greater than the reciprocal of the transconductance of the first PMOS transistor MP1 and the first resistor R ₁ Sum of the resistance values (i.e. r _on,MN3 ＞＞(1/g _m,MP1 +R ₁ ) A) is provided; therefore, the above "formula 5" can be simplified to obtain:

P ₂ ’＝1/2π(1/g _m,MP1 +R ₁ )C _L1 equation 6

By comparing the above formula 6 and the above formula 4, when the load current is too large and smaller than the current limiting threshold, the first PMOS transistor MP1 and the first resistor R are designed ₁ Secondary point P ₂ Is increased to make the secondary pole P ₂ Is far from the main pole P ₁ The pole frequency of the LDO loop is improved effectively.

Further, as shown in FIGS. 3-4, consider the total gain E of the loop _{Total (S)} The voltage output terminal V is caused to decrease _OUT To improve the voltage output terminalV _OUT Output accuracy of (a). Therefore, in some embodiments, the compensation module 30 further includes a second PMOS MP2, a first NMOS MN1, and a second NMOS MN2; source electrode and power supply end V of second PMOS tube MP2 _DD The grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the first PMOS tube MP 1; the drain electrode of the first NMOS tube MN1 is in short circuit with the grid electrode of the first NMOS tube MN1, the drain electrode of the first NMOS tube MN1 is connected with the drain electrode of the second PMOS tube MP2, and the source electrode of the first NMOS tube MN1 is connected with the grounding end GND; the drain of the second NMOS transistor MN2 is connected to the amplifying output terminal of the error amplifying module 20 (and connected to the first node L ₁ ) The source electrode of the second NMOS tube MN2 is connected with the ground end GND, and the grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the first NMOS tube MN 1.

In order to facilitate understanding, the first PMOS tube MP1 and the first resistor R are designed ₁ Then, the voltage output terminal V _OUT The specific circuit configuration of the error amplification module 20 will now be described in terms of the cause of the decrease in output accuracy. The error amplifying module 20 includes an error amplifier EA, where the error amplifier EA includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. Source electrode and power supply end V of third PMOS tube MP3 _DD The drain electrode of the third PMOS tube MP3 (i.e. the output end of the error amplifier EA) is connected with the first node L as the amplifying output end of the error amplifying module 20 ₁ Connecting; the drain electrode of the fourth PMOS tube MP4 is short-circuited with the grid electrode of the fourth PMOS tube MP4, and the source electrode of the fourth PMOS tube MP4 is connected with the power supply end V _DD The grid electrode of the fourth PMOS tube MP4 is connected with the grid electrode of the third PMOS tube MP 3; source electrode and power supply end V of fifth PMOS tube MP5 _DD Connecting; the drain electrode of the sixth PMOS tube MP6 is short-circuited with the grid electrode of the sixth PMOS tube MP6, and the source electrode of the sixth PMOS tube MP6 is connected with the power supply end V _DD The grid electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the fifth PMOS tube MP 5; the drain electrode of the third NMOS transistor MN3 and the first node L ₁ The source electrode of the third NMOS tube MN3 is connected with the ground end GND; the drain electrode of the fourth NMOS tube MN4 is in short circuit with the grid electrode of the fourth NMOS tube MN4, the drain electrode of the fourth NMOS tube MN4 is connected with the drain electrode of the sixth PMOS tube MP6, and the fourth NMOSThe source electrode of the transistor MN4 is connected with the ground end GND, and the grid electrode of the fourth NMOS transistor MN4 is connected with the grid electrode of the third NMOS transistor MN 3; the drain electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fourth PMOS tube MP4, and the grid electrode of the fifth NMOS tube MN5 (namely the positive input end of the error amplifier EA) is used as the second amplifying input end of the error amplifying module 20 to be connected with the feedback output end; the drain electrode of the sixth NMOS tube MN6 is connected with the drain electrode of the fifth PMOS tube MP5, and the grid electrode of the sixth NMOS tube MN6 (namely the inverting input end of the error amplifier EA) is used as the first amplifying input end of the error amplifying module 20 for accessing the reference voltage V _ref The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the seventh NMOS tube MN7 is connected with the source electrode of the fifth NMOS tube MN5 and the source electrode of the sixth NMOS tube MN6, and the source electrode of the seventh NMOS tube MN7 is connected with the ground end GND; the drain electrode of the eighth NMOS transistor MN8 is short-circuited with the gate electrode of the eighth NMOS transistor MN8, and the drain electrode of the eighth NMOS transistor MN8 is connected with the power supply end V _DD The source electrode of the eighth NMOS transistor MN8 is connected with the ground end GND, and the grid electrode of the eighth NMOS transistor MN8 is connected with the grid electrode of the seventh NMOS transistor MN 7.

It should be noted that, as shown in fig. 4, since the fourth PMOS transistor MP4 and the third PMOS transistor MP3 form a current mirror, the current flowing through the fourth PMOS transistor MP4 is equal to the current flowing through the third PMOS transistor MP3 (i.e. I _MP4 ＝I _MP3 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the fifth NMOS tube MN5 and the fourth PMOS tube MP4 are on the same branch, the current flowing through the fifth NMOS tube MN5 is equal to the current flowing through the fourth PMOS tube MP4 (i.e. I) _MN5 ＝I _MP4 ). Since the fourth NMOS transistor MN4 and the third NMOS transistor MN3 form a current mirror, the current flowing through the fourth NMOS transistor MN4 is equal to the current flowing through the third NMOS transistor MN3 (i.e., I _MN4 ＝I _MN3 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the sixth PMOS transistor MP6 and the fourth NMOS transistor MN4 are on the same branch, the current flowing through the sixth PMOS transistor MP6 is equal to the current flowing through the fourth NMOS transistor MN4 (i.e. I) _MP6 ＝I _MN4 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a current mirror, the current flowing through the fifth PMOS tube MP5 is equal to the current flowing through the sixth PMOS tube MP6 (i.e. I) _MP5 ＝I _MP6 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the sixth NMOS tube MN6 and the fifth PMOS tube MP5 are on the same branch, the current flowing through the sixth NMOS tube MN6 is equal to the current flowing through the fifth PMOS tube MP5 (i.e. I) _MN6 ＝I _MP5 )。

The first PMOS tube MP1 and the first resistor R are not designed ₁ Previously, for secondary pole P ₂ For example, the current flowing through the third PMOS MP3 is equal to the current flowing through the third NMOS MN3 (i.e.) _MP3 ＝I _MN3 ). From the above analysis, when the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is equal to the current flowing through the sixth NMOS transistor MN6 (i.e.) _MN5 ＝I _MN6 ) The transconductance of the fifth NMOS transistor MN5 is equal to the transconductance of the sixth NMOS transistor MN6 (i.e., g _m,MN5 ＝g _m,MN6 ) At this time, the gain of the LDO loop is stable, and the voltage output end V _OUT The output accuracy of (2) is high.

The first PMOS tube MP1 and the first resistor R are designed ₁ Then, the secondary pole P is aimed at before the second PMOS tube MP2, the first NMOS tube MN1 and the second NMOS tube MN2 are not designed ₂ For example, the sum of the current flowing through the third PMOS tube MP3 and the current flowing through the first PMOS tube MP1 is equal to the current flowing through the third NMOS tube MN3 (i.e. I _MP3 +I _MP1 ＝I _MN3 ) Because the current flowing through the first PMOS tube MP1 is not zero (i.e. I _MP1 Not equal to 0), the current flowing through the third PMOS transistor MP3 is not equal to the current flowing through the third NMOS transistor MN3 (i.e., I _MP3 ≠I _MN3 ). From the above analysis, when the current flowing through the third PMOS transistor MP3 is not equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is not equal to the current flowing through the sixth NMOS transistor MN6 (i.e.) _MN5 ≠I _MN6 ) The transconductance of the fifth NMOS transistor MN5 is not equal to the transconductance of the sixth NMOS transistor MN6 (i.e., g _m,MN5 ≠g _m,MN6 ) At this time, the gain of the LDO loop is reduced, and the voltage output terminal V _OUT The output accuracy of (a) is lowered.

After designing the second PMOS transistor MP2, the first NMOS transistor MN1 and the second NMOS transistor MN2, aiming at the secondary pole P ₂ For example, the sum of the current flowing through the first PMOS tube MP1, the current flowing through the second PMOS tube MP2 and the current flowing through the third PMOS tube MP3 is equal to the sum of the current flowing through the first NMOS tube MN1, the current flowing through the second NMOS tube MN2 and the current flowing through the third NMOS tube MN3 (i.e.) _MP1 +I _MP2 +I _MP3 ＝I _MN1 +I _MN2 +I _MN3 ). By designing the second PMOS transistor MP2, the first NMOS transistor MN1 and the second NMOS transistor MN2, it can be seen from fig. 4 that, since the second PMOS transistor MP2 and the first PMOS form a current mirror, the current flowing through the second PMOS transistor MP2 is equal to the current flowing through the first PMOS transistor MP1 (i.e. I _MP2 ＝I _MP1 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the first NMOS tube MN1 and the second PMOS tube MP2 are on the same branch, the current flowing through the first NMOS tube MN1 is equal to the current flowing through the second PMOS tube MP2 (i.e. I) _MN1 ＝I _MP2 ) The method comprises the steps of carrying out a first treatment on the surface of the Since the second NMOS transistor MN2 and the first NMOS transistor MN1 form a current mirror, the current flowing through the second NMOS transistor MN2 is equal to the current flowing through the first NMOS transistor MN1 (i.e. I _MN2 ＝I _MN1 ). At this time, it can be obtained that the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3 (i.e.) _MP3 ＝I _MN3 ) From the above analysis, when the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is equal to the current flowing through the sixth NMOS transistor MN6 (i.e.) _MN5 ＝I _MN6 ) The transconductance of the fifth NMOS transistor MN5 is equal to the transconductance of the sixth NMOS transistor MN6 (i.e., g _m,MN5 ＝g _m,MN6 ) At this time, the gain of the LDO loop is stable, and the voltage output end V _OUT The output accuracy of (a) is improved.

Further, as shown in fig. 3-4, the design of the second PMOS MP2 and the first NMOS MN1 may cause the compensation module 30 to generate a pole P different from the above-mentioned pole P ₂ Another secondary point P of (2) ₃ Due to the other secondary point P ₃ When the load current is too large, the dominant pole P is present ₁ When the pole frequency of (2) is increased, the main pole P ₁ The pole frequency of (a) also gradually approaches the other pole point P ₃ In turn, reduces the stability of the LDO loop to eliminate the other pole P ₃ The stability of the LDO loop is reduced. It is contemplated that in some embodiments, the compensation module 30 further includes a second resistor R ₂ And a first capacitor C ₁ The method comprises the steps of carrying out a first treatment on the surface of the Second resistor R ₂ A first end of the second resistor R is connected with the grid electrode of the first NMOS tube MN1 ₂ And a second end of (2)The grid electrode of the NMOS tube MN2 is connected; first capacitor C ₁ A first electrode plate of the second NMOS tube MN2 is connected with the grid electrode of the first capacitor C ₁ Is connected to the ground GND.

It can be understood that the node formed between the drain electrode of the second PMOS transistor MP2 and the drain electrode of the first NMOS transistor MN1 is the other pole P ₃ And the other secondary pole point P ₃ The pole frequency of (2) is:

P ₃ ＝1/2π(1/g _m,MN1 ||r _on,MP2 )C ₁ equation 7

Wherein r is _on,MP2 Represents the impedance g of the second PMOS tube MP2 _m,MN1 Representing the transconductance, C, of the first NMOS transistor MN1 ₁ The parasitic capacitance of the node formed between the drain of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1 is shown.

As can be seen from the above "equation 3" and the above "equation 7", when the load current is too large, the dominant pole P is caused ₁ When the pole frequency of (2) is increased, the main pole P ₁ The pole frequency of (a) gradually approaches the other pole point P ₃ Pole frequency (i.e. P ₁ ’≈P ₃ ) And the main pole point P ₁ And the other pole point P ₃ The close pole frequency of (c) may reduce the stability of the LDO loop.

However, in designing the second resistor R ₂ And the first capacitor C ₁ Then, a zero is introduced in the compensation module 30, and the pole frequency of the zero is:

Z _C ＝1/2πR ₂ C ₁ Equation 8

Wherein R is ₂ Representing a second resistance R ₂ ，C ₁ Representing the first capacitance C ₁ 。

By adjusting the parameter R according to the above "formula 7" and the above "formula 8 ₁ /C ₁ /g _m,MN1 /r _on,MP2 Make Z _C ≈P ₃ Thereby letting the zero point cancel the other pole P ₃ The stability of the LDO loop is reduced, so that the stability of the LDO loop is further improved.

As shown in fig. 5, consider that when the load current is greater than the above-described current limit threshold, there is a possibility that, for example, the LDO itself circuit and the post-stage circuit are burned out. To avoid damage to the LDO's own circuits and the subsequent circuits, it is necessary to limit the load current to a certain current when the load current is greater than the current limit threshold, so as to avoid the load current from increasing continuously. Therefore, in some embodiments, the LDO regulation circuit further includes a current limiting module 40, the current limiting module 40 and a power supply terminal V _DD The error amplifying module 20 is connected to the power tube module 10, and the current limiting module 40 is configured to limit the load current to the current limiting threshold when the load current is greater than the current limiting threshold. In the design, by designing the current limiting module 40, the current limiting module 40 can limit the load current to the current limiting threshold when the load current is greater than the current limiting threshold, so that damage to the LDO self circuit and the later-stage circuit is effectively avoided.

Specifically, the power tube module 10 includes a first power tube MP and a second power tube MS; the first connecting end of the first power tube MP is connected with the power supply end, and the second connecting end of the first power tube MP is connected with the voltage output end V _OUT The controlled end (grid) of the first power tube MP is connected with the output end of the Buffer; the first connection end of the second power tube MS is connected with the current limiting module 40, and the second connection end of the second power tube MS is connected with the voltage output end V _OUT And the controlled end (grid) of the second power tube MS is connected with the controlled end of the first power tube MP.

Further, as shown in fig. 6, to limit the load current to the current limit threshold when the load current is greater than the current limit threshold, the current limit module 40 is designed such that, in some embodiments, the error amplification module 20 further has an amplification controlled end; the current limiting module 40 includes a first current limiting resistor R _S A second current limiting resistor R _EF And a comparator COMP; first current limiting resistor R _S Is connected with the first end and the power supply end V _DD Connected with a first current-limiting resistor R _S And the first connection end of the second power tube MS (and connected to the second node L ₂ ) The method comprises the steps of carrying out a first treatment on the surface of the Second current limiting resistor R _EF Is connected with the first end and the power supply end V _DD Connecting; the non-inverting input terminal of the comparator COMP is connected to the first connection terminal of the second power tube MS (and connected to At the second node L ₂ ) An inverting input terminal of the comparator COMP and a second current limiting resistor R _EF The output end of the comparator COMP is connected to the amplification controlled end.

It will be appreciated that when the load current is greater than the current limit threshold, it may be that the current limit loop is active, and correspondingly the voltage loop is inactive; it is also possible that the current limiting loop and the voltage loop operate simultaneously.

When the current limiting loop works and the voltage loop does not work, the error amplifying module 20 also has an amplifying control end, and the error amplifying module 20 also comprises a current limiting element 21; the inverting input of the error amplifier EA is used as a first amplifying input for accessing the reference voltage V _ref The non-inverting input terminal of the error amplifier EA is used as a second amplifying input terminal and connected with the feedback voltage, and the output terminal of the error amplifier EA is used as an amplifying output terminal and connected with the input terminal of the Buffer (and connected with the first node L ₁ ) The method comprises the steps of carrying out a first treatment on the surface of the The first connection end of the current limiting element 21 is connected to the output end of the error amplifier EA, the second connection end of the current limiting element 21 is connected to the error amplifier EA (specifically, the drain electrode of the third NMOS transistor MN 3), and the controlled end of the current limiting element 21 is connected to the output end of the comparator COMP as an amplification controlled end.

When the load current is less than the current limiting threshold, the current limiting element 21 is in a conductive state, at which time the voltage loop is active and the current limiting loop is inactive. The load current gradually increases so that the load resistance R _L Gradually decrease, dominant pole P ₁ The pole frequency of (2) is gradually increased, and the compensation module 30 increases the secondary pole P according to the load current ₂ To the pole frequency of the secondary pole P ₂ Is far from the main pole P ₁ And thus ensures the stability of the LDO loop.

When the current is greater than the current limiting threshold, the current limiting element 21 is in an off state, at which time the voltage loop is inactive and the current limiting loop is active. The current limiting element 21 is used for adjusting an error signal at the output end of the error amplifier EA, and adjusting gate voltages of the first power tube MP and the second power tube MS through a Buffer, so as to limit the load current to a current limiting threshold value, thereby realizing a current limiting function.

It should be noted that, the current limiting element 21 has both a current limiting function and a switching function similar to a switch, wherein the switching function of the current limiting element 21 indicates that the current limiting element 21 has an on state and an off state, and the current limiting element 21 is one of a triode and a field effect transistor. For example, when the current limiting element 21 is embodied as a triode, the "on state" of the triode is a state when the collector and the emitter of the triode are on, whereas the "off state" of the triode is a state when the collector and the emitter of the triode are off.

Specifically, as shown in fig. 4, the current limiting element 21 is a thirteenth NMOS transistor MN13, and the drain of the thirteenth NMOS transistor MN13 and the first node L ₁ The source of the thirteenth NMOS transistor MN13 is connected with the drain of the third NMOS transistor MN3, and the gate of the thirteenth NMOS transistor MN13 is connected with the output end of the comparator COMP as an amplification controlled end.

It should be noted that, the current limiting loop uses load current sampling, so no great power consumption is caused, and when the current limiting loop works, the current limiting element 21 cuts off the voltage loop, so that the accuracy of the current limiting point and the stability of the current limiting loop can be improved.

When the current limiting loop and the voltage loop work simultaneously, the main difference between the current limiting loop and the voltage loop is that the thirteenth NMOS MN13 and the third NMOS MN3 are connected in different manners, specifically: the drain of the thirteenth NMOS transistor MN13 and the drain of the third NMOS transistor MN3 are connected to the first node L ₁ The source of the thirteenth NMOS transistor MN13 and the drain of the third NMOS transistor MN3 are connected to the ground GND, and the gate of the thirteenth NMOS transistor MN13 is connected to the output of the comparator COMP as an amplification controlled terminal, that is, the thirteenth NMOS transistor MN13 is connected in parallel to the third NMOS transistor MN 3.

As shown in fig. 3 and 7, the specific circuit structure of the current limiting module 40 will be described for the convenience of understanding the current limiting principle of the current limiting module 40 based on the fact that the current limiting loop is operated and the voltage loop is not operated when the load current is greater than the current limiting threshold. The current limiting module 40 includes the first current limiting resistor R _S The second current-limiting resistor R _EF On the upper partComparator COMP and current source I _D . The comparator COMP includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The source of the seventh PMOS tube MP7 is used as the inverting input end of the comparator COMP and connected with the first connecting end of the second power tube MS to the second node L ₂ The drain electrode of the seventh PMOS tube MP7 is used as the output end of the comparator COMP and the grid electrode of the thirteenth NMOS tube MN13 is connected with the third node L ₃ The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the eighth PMOS tube MP8 is in short circuit with the grid electrode of the eighth PMOS tube MP8, the source electrode of the eighth PMOS tube MP8 is connected with the source electrode of the seventh PMOS tube MP7, and the grid electrode of the eighth PMOS tube MP8 is connected with the grid electrode of the seventh PMOS tube MP 7; the source of the ninth PMOS tube MP9 is used as the non-inverting input end of the comparator COMP and the second current-limiting resistor R _EF Is connected to the fourth node L ₄ The drain electrode of the ninth PMOS tube MP9 is short-circuited with the gate electrode of the ninth PMOS tube MP9 and connected with the drain electrode of the eighth PMOS tube MP8 at a fifth node L ₅ The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the tenth PMOS tube MP10 is connected with the source electrode of the ninth PMOS tube MP9, and the grid electrode of the tenth PMOS tube MP10 is connected with the grid electrode of the ninth PMOS tube MP 9; drain electrode of ninth NMOS transistor MN9 and third node L ₃ The source electrode of the ninth NMOS tube MN9 is connected with the ground end GND; the drain electrode of the tenth NMOS tube MN10 is in short circuit with the grid electrode of the tenth NMOS tube MN10, the drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the tenth PMOS tube MP10, the source electrode of the tenth NMOS tube MN10 is connected with the grounding end GND, and the grid electrode of the tenth NMOS tube MN10 is connected with the grid electrode of the ninth NMOS tube MN 9; drain electrode of eleventh NMOS transistor MN11 and fifth node L ₅ The source electrode of the eleventh NMOS tube MN11 is connected with the ground end GND; the drain electrode of the twelfth NMOS transistor MN12 is short-circuited with the gate electrode of the twelfth NMOS transistor MN12, and the drain electrode of the twelfth NMOS transistor MN12 is connected with the current source I _D The source electrode of the twelfth NMOS tube MN12 is connected with the ground end GND, and the grid electrode of the twelfth NMOS tube MN12 is connected with the grid electrode of the eleventh NMOS tube MN 11; current source I _D Positive electrode of (d) and power supply terminal V _DD And (5) connection.

It should be noted that, as shown in fig. 7, since the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form a current mirror, the current flowing through the seventh PMOS transistor MP7Equal to the current flowing through the eighth PMOS tube MP8 (i.e. I _MP7 ＝I _MP8 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the ninth PMOS tube MP9 and the tenth PMOS tube MP10 form a current mirror, the current flowing through the ninth PMOS tube MP9 is equal to the current flowing through the tenth PMOS tube MP10 (i.e. I) _MP9 ＝I _MP10 ) The method comprises the steps of carrying out a first treatment on the surface of the Since the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 form a current mirror, the current flowing through the ninth NMOS transistor MN9 is equal to the current flowing through the tenth NMOS transistor MN10 (i.e., I _MN9 ＝I _MN10 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the ninth NMOS transistor MN9 and the seventh PMOS transistor MP7 are on the same branch, the current flowing through the ninth NMOS transistor MN9 is equal to the current flowing through the seventh PMOS transistor MP7 (i.e. I) _MN9 ＝I _MP7 ) The method comprises the steps of carrying out a first treatment on the surface of the Because the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are on the same branch, the current flowing through the tenth NMOS transistor MN10 is equal to the current flowing through the tenth PMOS transistor MP10 (i.e. I) _MN10 ＝I _MP10 ). Therefore, the sum of the current flowing through the eighth PMOS transistor MP8 and the current flowing through the ninth PMOS transistor MP9 is equal to the current (I) flowing through the eleventh NMOS transistor MN11 _MP8 +I _MP9 ＝I _MN11 ＝2*I _MP8 )。

Since the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 form a current mirror, the current flowing through the eleventh NMOS transistor MN11 is equal to the current flowing through the twelfth NMOS transistor MN12 (i.e., I _MN11 ＝I _MN12 ) The method comprises the steps of carrying out a first treatment on the surface of the Since the twelfth NMOS transistor MN12 is connected in series with the current source ID, the current flowing through the twelfth NMOS transistor MN12 is equal to the current of the current source ID (i.e.) _MN12 ＝I _D )。

Since the sum of the current flowing through the ninth PMOS transistor MP9 and the current flowing through the tenth PMOS transistor MP10 is equal to the current flowing through the second current limiting resistor REF (i.e.) _MP9 +I _MP10 ＝I _REF ) So as to flow through the second current-limiting resistor R _EF A current flowing through the eleventh NMOS transistor MN11, a current flowing through the twelfth NMOS transistor MN12, and a current source I _D Are all equal (i.e. I _REF ＝I _MN11 ＝I _MN12 ＝I _D )。

As can be seen from fig. 7, the sum of the current flowing through the second power tube MS and the current flowing through the seventh PMOS tube MP7 is equal to the current flowing through the first current limiting resistor R _S Current (i.e. I) _MS ＝I _MP7 +I _RS )。

When the load current is less than the current limit threshold, the voltage loop is operated and the current limit loop is not operated.

At this time, a first current limiting resistor R _S The voltage at two ends is smaller than the second current limiting resistor R _EF The voltage across (i.e. V _RS ＜V _REF ) Second node L ₂ Is greater than the fourth node L ₄ Voltage (i.e. V) _L2 ＞V _L4 ) Third node L ₃ The voltage of the (c) is pulled up so that the thirteenth NMOS transistor MN13 is in a conducting state, the thirteenth NMOS transistor MN13 is conducted, the voltage loop works normally, and the current limiting loop does not work.

When the load current is greater than the current limiting threshold, the current limiting loop is operated and the voltage loop is not operated.

At this time, a first current limiting resistor R _S The voltage at two ends is larger than that of the second current limiting resistor R _EF The voltage across (i.e. V _RS ＞V _REF ) Second node L ₂ Is smaller than the fourth node L ₄ Voltage (i.e. V) _L2 ＜V _L4 ) Third node L ₃ The voltage of the (c) is pulled down so that the thirteenth NMOS transistor MN13 is in an off state, the thirteenth NMOS transistor MN13 is turned off, the current limiting loop works normally, and the voltage loop does not work.

When the load current is greater than the current limiting threshold, the current limiting loop works and limits the load current to the current limiting threshold I at maximum _limit And a current limiting threshold I _limit The calculation mode of (2) is as follows:

V _L1 ＝V _DD -V _RS equation 9

V _L2 ＝V _DD -V _REF Equation 10

Wherein V is _RS ＝[I _MN11 +I _LOAD *N/(N+M)]*R _S Equation 11

V _REF ＝I _MN11 *R _EF Equation 12

Wherein M is the width-to-length ratio of the second power tube MS, N is the sum of the width-to-length ratios of the first power tube MP and the second power tube MS, the size ratio of the seventh PMOS tube MP7 to the eighth PMOS tube MP8 is 1:1, and the size ratio of the ninth PMOS tube MP9 to the tenth PMOS tube MP10 is 1:1;

when V is _L1 ＝V _L2 When there is a current limiting threshold I _limit At this time I _LOAD ＝I _limit And because of I _MN11 ＝I _MN12 ＝I _D Equation 13

Therefore, after the above "formula 13" is brought into the above "formula 11" and the above "formula 12", the arrangement can be obtained:

I _limit ＝I _LOAD ＝I _D *(R _EF /R _S -1) N/M-equation 14

A second aspect of the present application proposes a power management chip (not shown in the figures) comprising the LDO regulator circuit described above. In this design, the compensation module 30 can adjust the secondary pole P according to the magnitude of the load current when the load current flowing through the power tube module 10 is larger and smaller than the current limiting threshold ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And the pole frequency of the LDO loop is improved, so that the working stability of the power management chip when the load current is overlarge is improved.

Referring to fig. 8, a third aspect of the present application provides an LDO adjustment method applied to the LDO adjustment circuit shown in fig. 1-7, the LDO adjustment method comprising:

step S202, the compensation module 30 adjusts the secondary pole P according to the magnitude of the load current when the load current flowing through the power tube module 10 is less than the current limiting threshold ₂ Pole frequency of (c).

According to the LDO regulation method in the embodiment of the application, when the load current flowing through the power tube module 10 is larger and smaller than the current limiting threshold, the compensation module 30 can adjust the secondary pole P according to the magnitude of the load current ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And thus improves the stability of the LDO loop.

Fourth of the applicationIn aspects, a circuit board (not shown) is provided, on which an off-chip capacitor C is soldered _L And the power management chip and the off-chip capacitor C _L Voltage output terminal V of power management chip _OUT And (5) connection. In this design, the compensation module 30 can adjust the secondary pole P according to the magnitude of the load current when the load current flowing through the power tube module 10 is larger and smaller than the current limiting threshold value ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And the pole frequency of the LDO loop is improved, so that the working stability of the circuit board when the load current is overlarge is improved.

A fifth aspect of the present application provides an electronic device (not shown in the drawings), which includes a housing having a housing cavity and the above-described circuit board, and the circuit board is disposed in the housing cavity. The electronic device may include, but is not limited to, a mobile power supply, a charging plug, a balance car, a hand-held electric drill, and the like. In this design, when the load current flowing through the power tube module 10 is larger and smaller than the current limiting threshold, the compensation module 30 can adjust the secondary pole P according to the load current ₂ To the pole frequency of the secondary pole point P ₂ The pole frequency of (2) gradually gets away from the main pole P ₁ And the pole frequency of the LDO loop is improved, so that the working stability of the electronic equipment when the load current is overlarge is improved.

The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present application, it should be understood that, if there is an azimuth or positional relationship indicated by terms such as "upper", "lower", "left", "right", etc., based on the azimuth or positional relationship shown in the drawings, it is only for convenience of describing the present application and simplifying the description, but it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus terms describing the positional relationship in the drawings are merely illustrative and should not be construed as limitations of the present patent, and specific meanings of the terms described above may be understood by those skilled in the art according to specific circumstances.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims

1. An LDO regulation circuit, comprising:

the power tube module is connected with the power supply end and provided with a voltage output end, and the voltage output end is used for being connected with an external load;

the error amplifying module is connected between the power end and the grounding end;

the buffer is connected between the power end and the grounding end, the input end of the buffer is connected with the amplifying output end of the error amplifying module, the output end of the buffer is connected with the power tube module, the buffer is used for separating a main pole point and a secondary pole point, the main pole point is arranged at the voltage output end, and the secondary pole point is arranged at the amplifying output end of the error amplifying module;

and the compensation module is connected with the amplifying output end of the error amplifying module and is used for adjusting the pole frequency of the secondary pole according to the magnitude of the load current when the load current flowing through the power tube module is smaller than a current limiting threshold value.

2. The LDO regulation circuit of claim 1 wherein the compensation module includes:

the drain electrode of the first PMOS tube is in short circuit with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the power supply end;

the first end of the first resistor is connected with the drain electrode of the first PMOS tube, and the second end of the first resistor is connected with the amplifying output end of the error amplifying module.

3. The LDO regulation circuit of claim 2 wherein the compensation module further includes:

the source electrode of the second PMOS tube is connected with the power supply end, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube;

the drain electrode of the first NMOS tube is in short circuit with the grid electrode of the first NMOS tube, the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is connected with the grounding end;

the drain electrode of the second NMOS tube is connected with the amplifying output end of the error amplifying module, the source electrode of the second NMOS tube is connected with the grounding end, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube.

4. The LDO regulation circuit of claim 3 wherein the compensation module further includes:

the first end of the second resistor is connected with the grid electrode of the first NMOS tube, and the second end of the second resistor is connected with the grid electrode of the second NMOS tube;

and a first polar plate of the first capacitor is connected with the grid electrode of the second NMOS tube, and a second polar plate of the first capacitor is connected with the grounding end.

5. The LDO regulation circuit of any of claims 1-4, wherein the LDO regulation circuit further includes a current limiting module;

the current limiting module is connected with the power end, the error amplifying module and the power tube module, and is used for limiting the load current to the current limiting threshold value when the load current is larger than the current limiting threshold value.

6. The LDO regulation circuit of claim 5 wherein the power tube module includes:

the first power tube is connected with the power supply end at a first connecting end, the voltage output end at a second connecting end of the first power tube is connected with the voltage output end, and the output end of the buffer is connected with the controlled end of the first power tube;

The first connecting end of the second power tube is connected with the current limiting module, the second connecting end of the second power tube is connected with the voltage output end, and the controlled end of the second power tube is connected with the controlled end of the first power tube.

7. The LDO regulation circuit of claim 6 wherein the error amplification module has an amplification controlled end; the current limiting module includes:

the first end of the first current limiting resistor is connected with the power supply end, and the second end of the first current limiting resistor is connected with the first connecting end of the second power tube;

the first end of the second current limiting resistor is connected with the power supply end;

the positive input end of the comparator is connected with the first connecting end of the second power tube, the negative input end of the comparator is connected with the second end of the second current limiting resistor, and the output end of the comparator is connected with the amplifying controlled end.

8. The LDO regulation circuit of claim 7 wherein the error amplification module includes:

the inverting input end of the error amplifier is used for being connected with a reference voltage, the non-inverting input end of the error amplifier is used for being connected with a feedback voltage, and the output end of the error amplifier is used as the amplifying output end and is connected with the input end of the buffer;

The first connecting end of the current limiting element is connected with the output end of the error amplifier, the second connecting end of the current limiting element is connected with the error amplifier, and the controlled end of the current limiting element is used as the amplifying controlled end to be connected with the output end of the comparator.

9. A power management chip, comprising:

the LDO regulation circuit of any of claims 1-8.

10. An LDO regulation method applied to the LDO regulation circuit of any of claims 1-8, the LDO regulation method comprising:

and when the load current flowing through the power tube module is smaller than the current limiting threshold value, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current.