CN116593799A

CN116593799A - Offset voltage testing method and device for current detection amplifier and electronic equipment

Info

Publication number: CN116593799A
Application number: CN202310450078.2A
Authority: CN
Inventors: 章文旭; 郑高铭; 林雅文; 方俊博; 张亭亭; 盖昱升; 余波
Original assignee: CASIC Defense Technology Research and Test Center
Current assignee: CASIC Defense Technology Research and Test Center
Priority date: 2023-04-24
Filing date: 2023-04-24
Publication date: 2023-08-15

Abstract

The application provides a method, a device and electronic equipment for testing offset voltage of a current detection amplifier, which are used for adjusting the offset voltage of the input end of the current detection amplifier to be tested, so that the output voltage can be in the allowable range of the current detection amplifier to be tested, the offset voltage of the input end after adjustment is further obtained, then the offset voltage adjustment value and the offset voltage error are removed from the offset voltage of the input end after adjustment, and finally an offset voltage test result is obtained.

Description

Offset voltage testing method and device for current detection amplifier and electronic equipment

Technical Field

The present application relates to the field of integrated circuit testing technologies, and in particular, to a method and an apparatus for testing offset voltage of a current detection amplifier, and an electronic device.

Background

The current sense amplifier, also known as a current shunt monitor, is a specialized differential amplifier. Offset voltage is a differential dc error at the input of the current sense amplifier, typically due to imbalance between the positive and negative inputs of the current sense amplifier. The offset voltage of the input end generates error voltage at the output end after the offset voltage of the input end is amplified by the gain of the current detection amplifier, and when the error voltage magnitude is similar to the actual detection output voltage magnitude, the detection precision can be seriously affected. Therefore, offset voltage is also one of the important performance parameters of the current sense amplifier.

For a single-power-supply current detection amplifier, due to the limitation of the output swing characteristic, the error voltage of the low enough offset voltage (usually in the micro-volt level and below) amplified by the gain of the current detection amplifier cannot exceed the lower limit of the output voltage of the single-power-supply current detection amplifier.

The partial type single power supply current detection amplifier is provided with an internal reference or an external reference, output voltage bias is realized, direct test of offset voltage can be realized by avoiding limitation of output swing characteristics, however, the dynamic range of the current detection amplifier can be reduced by adopting the mode, the method is only suitable for offset voltage test of the single power supply current detection amplifier with the internal reference or the external reference end, and the problem that the low offset voltage test of the single power supply current detection amplifier without the internal reference or the external reference end still faces limitation of lower limit of output voltage and cannot be tested due to too small offset voltage is still caused.

Disclosure of Invention

Therefore, the present application is directed to a method and apparatus for testing offset voltage of a current sense amplifier, and an electronic device, which are used for solving or partially solving the above technical problems.

Based on the above object, a first aspect of the present application provides a method for testing offset voltage of a current sense amplifier, including:

Acquiring an offset voltage adjustment value of a current detection amplifier to be detected and an offset voltage error of a test circuit where the current detection amplifier to be detected is positioned;

adjusting the offset voltage of the input end of the current detection amplifier to be detected to obtain the offset voltage of the input end after adjustment;

and removing the offset voltage adjustment value and the offset voltage error from the offset voltage of the adjusted input end to obtain an offset voltage test result.

Optionally, the input end of the current detection amplifier to be detected is connected with a preselected offset voltage adjusting resistor;

the step of adjusting the offset voltage of the input end of the current detection amplifier to be detected to obtain the adjusted offset voltage of the input end comprises the following steps:

and increasing the offset voltage of the input end of the current detection amplifier to be detected through the offset voltage adjusting resistor to obtain the offset voltage of the input end after adjustment.

Optionally, the selecting process of the offset voltage adjustment resistor includes:

selecting any test resistor, and obtaining characteristic parameters of the selected any test resistor, wherein the characteristic parameters comprise an accuracy resistance value, a temperature drift resistance value and a theoretical resistance value;

performing error calculation of an actual resistance value and a theoretical resistance value under a preset temperature condition according to the precision resistance value, the temperature drift resistance value and the theoretical resistance value of any selected test resistor, and determining the maximum error of the actual resistance value and the theoretical resistance value of any selected test resistor;

Obtaining bias current, actual gain, lower limit of output voltage, measurement range of voltage value of output end, maximum measurement error of offset voltage and theoretical offset voltage of a current detection amplifier to be detected;

judging whether any selected test resistor meets a preset offset voltage adjustment resistor constraint condition according to the bias current, the actual gain, the theoretical offset voltage, the offset voltage maximum measurement error, the theoretical resistance and the maximum error, wherein the preset offset voltage adjustment resistor constraint condition is specifically as follows:

V _OL ＜R _adj ×I _br ×G _r ＜V _range

R _error ×I _br ≤V _os ×E％

wherein ,R_error Representing the maximum error between the actual resistance and the theoretical resistance of any selected test resistor, R _adj Represented as the resistance of any selected test resistor, R _pre Expressed as the precision resistance value of any selected test resistor, R _tse The temperature drift resistance value of any selected test resistor is shown, vrange is shown as the output end voltage value measuring range of the current detection amplifier to be measured, E% is shown as the offset voltage maximum measuring error of the current detection amplifier to be measured, and V _OL Represented as the lower limit of the output voltage of the current sense amplifier under test, I _br Expressed as bias current, G _r Representing the actual gain, V, of the current sense amplifier under test _os The theoretical offset voltage is expressed as a current detection amplifier to be detected;

and taking the test resistor meeting the constraint condition of the preset offset voltage adjusting resistor as the offset voltage adjusting resistor.

Optionally, the step of increasing the offset voltage of the input end of the current detection amplifier to be detected through the offset voltage adjustment resistor, to obtain the adjusted offset voltage of the input end, includes:

acquiring the actual gain of the current detection amplifier to be detected;

the offset voltage of the input end of the current detection amplifier to be detected is increased by using the offset voltage adjusting resistor, and a corresponding adjusted output voltage value is detected at the output end of the current detection amplifier to be detected;

and calculating the ratio of the adjusted output voltage value to the actual gain to obtain the offset voltage of the adjusted input end.

Optionally, the obtaining the actual gain of the current detection amplifier to be detected includes:

obtaining multiple groups of differential input voltages of the current detection amplifier to be detected, wherein each group of differential input voltages comprises a first differential input voltage and a second differential input voltage, adjacent groups of differential input voltages meet a first arithmetic condition, and the formula of the first arithmetic condition is as follows:

wherein ,expressed as a first differential input voltage of the n-th set of differential input voltages, ">Expressed as a second differential input voltage of the n-th set of differential input voltages, ">The first differential input voltage, denoted as n+1th group differential input voltage, ">A second differential input voltage represented as an n+1th group differential input voltage;

acquiring the lower limit of the output voltage and the upper limit of the output voltage and the theoretical gain of the current detection amplifier to be detected;

the output voltage lower limit, the output voltage upper limit and the theoretical gain of any differential input voltage and the current detection amplifier to be detected meet differential input voltage constraint conditions, and the differential input voltage constraint conditions specifically are as follows:

V _OL ＜V _d ×G＜V _OH

wherein ,V_OL Represented as the lower limit of the output voltage of the current sense amplifier under test, V _OH Is expressed as waiting forThe upper limit of the output voltage of the current detection amplifier is measured, G is expressed as the theoretical gain of the current detection amplifier to be measured, V _d Represented as any one of any set of differential input voltages;

the following is performed for each set of differential input voltages:

applying a first differential input voltage to the current detection amplifier to be detected, and detecting a corresponding first output voltage at an output end of the current detection amplifier to be detected;

Applying a second differential input voltage to the current detection amplifier to be detected, and detecting a corresponding second output voltage value at the output end of the current detection amplifier to be detected;

performing difference calculation based on the first output voltage and the second output voltage to obtain a first difference result;

performing difference calculation on the first differential input voltage and the second differential input voltage to obtain a second difference result;

calculating a ratio by using the first difference result and the second difference result to obtain an actual gain corresponding to the current group of differential input voltages;

and carrying out average calculation on the actual gain corresponding to each group of differential input voltage to obtain the actual gain.

Optionally, the obtaining the offset voltage adjustment value of the current detection amplifier to be detected includes:

acquiring bias current of the current detection amplifier to be detected;

and performing product calculation by using the bias current and the resistance value of the offset voltage adjusting resistor to obtain the offset voltage adjusting value.

Optionally, the obtaining the bias current of the current detection amplifier to be detected includes:

obtaining a plurality of arithmetic resistances, wherein each arithmetic resistance meets a second arithmetic condition, and the formula of the second arithmetic condition is specifically as follows:

wherein ,expressed as mth arithmetic resistance, ">Expressed as the mth-1 arithmetic resistance value +.>The resistance value of the arithmetic resistor is expressed as m+1th arithmetic resistor;

obtaining a bias current typical value, an offset voltage maximum value, an actual gain, an output voltage lower limit and an output voltage upper limit of the current detection amplifier to be detected;

the mth arithmetic resistance value and the bias current typical value, the offset voltage maximum value, the actual gain, the output voltage lower limit and the output voltage upper limit meet resistance constraint conditions, and the resistance constraint conditions are specifically expressed in the following formulas:

wherein ,expressed as mth arithmetic resistance value, I _BTYP Representative value of bias current, V, expressed as a current sense amplifier under test _OSMAX Expressed as offset voltage maximum of current sense amplifier, V _OL Expressed as the lower limit of the output voltage of the current sense amplifier to be measured, G _r Expressed as measured gain of current sense amplifier to be measured, V _OH An upper limit of the output voltage, denoted as current sense amplifier to be measured;

the following is performed for each arithmetic resistor:

connecting any equidifference resistor with the current detection amplifier to be detected in series, and detecting a corresponding voltage test result at the output end of the current detection amplifier to be detected;

Performing difference calculation on the voltage test results corresponding to each adjacent arithmetic resistor to obtain a plurality of voltage test result difference values;

carrying out difference calculation on the resistance value of each adjacent arithmetic resistor to obtain a plurality of resistance difference values;

performing product calculation by using the actual gain of the current detection amplifier to be detected and each resistance difference value to obtain a product calculation result;

performing ratio calculation on each voltage test result difference value and a corresponding product calculation result to obtain a plurality of ratio calculation results;

and carrying out average calculation on each ratio calculation result to obtain the bias current.

Optionally, the obtaining the offset voltage error of the test line where the current detection amplifier to be tested is located includes:

acquiring the contact resistance value of a test circuit where the current detection amplifier to be detected is located;

and carrying out product calculation based on the contact resistance value and the bias current to obtain the offset voltage error.

A second aspect of the present application provides a current sense amplifier offset voltage testing apparatus, comprising:

the acquisition module is configured to acquire an offset voltage adjustment value of a current detection amplifier to be detected and an offset voltage error of a test circuit where the current detection amplifier to be detected is positioned;

The adjusting module is configured to adjust the offset voltage of the input end of the current detection amplifier to be detected, and acquire the offset voltage of the input end after adjustment;

and the removing module is configured to remove the offset voltage adjustment value and the offset voltage error from the offset voltage of the adjusted input end to obtain an offset voltage test result.

A third aspect of the application provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of the first aspect when executing the program.

As can be seen from the above, according to the offset voltage testing method, device and electronic equipment for the current detection amplifier provided by the application, the offset voltage of the input end of the current detection amplifier to be tested is adjusted, so that the output voltage can be within the allowable range of the current detection amplifier to be tested, the offset voltage of the adjusted input end is further obtained, the offset voltage adjustment value and the offset voltage error are removed from the offset voltage of the adjusted input end, and finally the offset voltage testing result is obtained.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a flow chart of a method for testing offset voltage of a current sense amplifier according to an embodiment of the application;

FIG. 2 is a schematic diagram of offset voltage testing of a single power supply current sense amplifier according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a current sense amplifier offset voltage testing apparatus according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present application;

wherein, in the figure:

2-1, a switch; 2-11, a first switch; 2-12, a second switch; 2-13, a third switch;

2-2, adjusting resistance of offset voltage;

2-3, a current detection amplifier to be detected;

2-4, an input end; 2-41, positive input end; 2-42, negative input;

2-5, the output end.

Detailed Description

The present application will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

In the related art, for a current detection amplifier powered by a single power supply, due to the limitation of the output swing characteristic, the error voltage of the offset voltage (usually in the micro-volt level or below) which is low enough after the gain amplification of the current detection amplifier cannot exceed the lower limit of the output voltage of the current detection amplifier of the single power supply, so that the offset voltage cannot be directly tested.

The single power supply current detection amplifier of partial type has internal reference or external reference, realizes output voltage bias, can avoid the limitation of output swing characteristic to realize direct test of offset voltage, however, the dynamic range of the current detection amplifier can be reduced by the mode, and the current detection amplifier is only suitable for offset voltage test of the single power supply current detection amplifier with the internal reference or external reference end, and when the single power supply current detection amplifier without the internal reference or external reference end is used for low offset voltage test, the lower limit of output voltage is still faced, so that the problem that the test cannot be carried out due to the fact that the offset voltage is too small is caused, and the error of the reference can also lead to the error of offset voltage test result, so that the precision requirement on the reference is higher.

According to the offset voltage testing method for the current detection amplifier, the output voltage can be in the allowable output range of the current detection amplifier to be tested by utilizing the offset voltage adjusting mode of the input end of the current detection amplifier to be tested, so that the problem that the current detection amplifier cannot be tested due to too small offset voltage is avoided, and as shown in fig. 1, the offset voltage testing method comprises the following steps:

step 101, obtaining an offset voltage adjustment value of a current detection amplifier to be detected and an offset voltage error of a test circuit where the current detection amplifier to be detected is located.

In this step, the offset voltage adjustment value represents an adjustment value introduced by an electronic component, which may be at least one of:

resistors, capacitors, inductors, potentiometers, electron tubes, heat sinks, electromechanical elements, connectors, and the like.

The offset voltage error is indicative of an error introduced by an electrical control device connected in the test line, which may be at least one of:

relay, test seat, fuse, transformer, circuit breaker, isolator etc..

Step 102, adjusting the offset voltage of the input end of the current detection amplifier to be detected, and obtaining the offset voltage of the input end after adjustment.

In the step, the offset voltage of the input end of the current detection amplifier to be detected is adjusted, so that the output voltage of the output end of the current detection amplifier to be detected can be within the allowable range of the current detection amplifier to be detected, and the offset voltage of the input end after adjustment is obtained.

And step 103, removing the offset voltage adjustment value and the offset voltage error from the offset voltage of the adjusted input end to obtain an offset voltage test result.

In this step, in order to eliminate errors in the test line, error compensation is implemented by removing offset voltage adjustment values and offset voltage errors from the offset voltage of the adjusted input end, and an offset voltage test result is obtained, so that an offset voltage test for a current detection amplifier powered by a single power supply is implemented, which can be expressed as:

V _osr ＝V _ostotal -V _osadj -V _ose

wherein ,V_osr Expressed as offset voltage test result, V _ostotal Expressed as offset voltage of input end after adjustment, V _osadj Expressed as offset voltage adjustment value, V _ose Represented as offset voltage errors.

Through the scheme, the offset voltage of the input end of the current detection amplifier to be detected is adjusted, so that the output voltage can be in the allowable range of the current detection amplifier to be detected, the offset voltage of the adjusted input end is obtained, the offset voltage adjustment value and the offset voltage error are removed from the offset voltage of the adjusted input end, and finally an offset voltage test result is obtained.

In some embodiments, in step 101, the obtaining the offset voltage adjustment value of the current detection amplifier to be measured includes:

and A1, obtaining the bias current of the current detection amplifier to be detected.

And A2, performing product calculation by using the bias current and the resistance value of the offset voltage adjusting resistor to obtain the offset voltage adjusting value.

In the above scheme, the product calculation is performed by using the resistance value of the offset voltage adjusting resistor and the bias current selected in advance, so as to obtain the offset voltage adjusting value introduced by the offset voltage adjusting resistor, which can be expressed as:

wherein ,V_osadj Expressed as offset voltage adjustment value, R is expressed as resistance value of a preselected offset voltage adjustment resistor, I _br Represented as the bias current of the current sense amplifier under test.

In some embodiments, step A1 comprises:

step A11, obtaining a plurality of arithmetic resistors, wherein each arithmetic resistor meets a second arithmetic condition, and the formula of the second arithmetic condition is specifically as follows:

wherein ,expressed as mth arithmetic resistance, ">Expressed as the mth-1 arithmetic resistance value +.>Expressed as the m+1th arithmetic resistance value.

And step A12, obtaining a typical bias current value, a maximum offset voltage value, an actual gain, a lower output voltage limit and an upper output voltage limit of the current detection amplifier to be detected.

Step A13, the mth arithmetic resistance value and the bias current typical value, the offset voltage maximum value, the actual gain, the output voltage lower limit and the output voltage upper limit meet resistance constraint conditions, and the resistance constraint conditions are specifically expressed in the following formulas:

wherein ,expressed as mth arithmetic resistance value, I _BTYP Representative value of bias current, V, expressed as a current sense amplifier under test _OSMAX Expressed as offset voltage maximum of current sense amplifier, V _OL Expressed as the lower limit of the output voltage of the current sense amplifier to be measured, G _r Expressed as measured gain of current sense amplifier to be measured, V _OH Represented as the upper output voltage limit of the current sense amplifier under test.

Step a14, the following operations are performed for each arithmetic resistor:

and connecting any equidifference resistor with the current detection amplifier to be detected in series, and detecting a corresponding voltage test result at the output end of the current detection amplifier to be detected.

And step A15, carrying out difference calculation on the voltage test results corresponding to each adjacent equal difference resistor to obtain a plurality of voltage test result difference values.

And step A16, carrying out difference calculation on the resistance value of each adjacent arithmetic resistor to obtain a plurality of resistance difference values.

And step A17, performing product calculation by using the actual gain of the current detection amplifier to be detected and each resistance difference value to obtain a product calculation result.

And step A18, carrying out ratio calculation on each voltage test result difference value and the corresponding product calculation result to obtain a plurality of ratio calculation results.

And step A19, carrying out average calculation on each ratio calculation result to obtain the bias current.

In the above scheme, as shown in fig. 2, the function of the test circuit is switched to the bias current test, the switching mode is to close the K2 switch 2-12 in the switch 2-1, and at this time, the test circuit is the bias current test circuit at the input end of the current detection amplifier powered by the single power supply, and the bias current test circuit is started.

For example, M arithmetic resistors are selected and connected in series with the input terminal 2-4 of the current detection amplifier 2-3 to be tested (only one arithmetic resistor is selected for connection in series at a time), and in addition, a preset common-mode input voltage can be applied between the positive input terminal 2-41 and the negative input terminal 2-42 of the single power current detection amplifier 2-3 to be tested (which can be set according to specific conditions, and the magnitude of the applied preset common-mode voltage is not limited in detail here), and the magnitude of the applied preset common-mode input voltage is unchanged.

Each arithmetic resistor satisfies a first arithmetic condition, which indicates that the selected resistors are all arithmetic relationships, for example, the m-th arithmetic resistor value, the m-1-th arithmetic resistor value and the m+1th arithmetic resistor value satisfy:

wherein ,expressed as mth arithmetic resistance, " >Expressed as the mth-1 arithmetic resistance value +.>The resistance value of the arithmetic resistor is expressed as m+1th arithmetic resistor;

and the selected bias current typical value of any one of M arithmetic resistance values and the current detection amplifier 2-3 to be detected, the offset voltage maximum value of the current detection amplifier 2-3 to be detected, the actual gain of the current detection amplifier 2-3 to be detected, the lower limit of the output voltage of the current detection amplifier 2-3 to be detected and the upper limit of the output voltage of the current detection amplifier 2-3 to be detected meet the resistance constraint condition, and the formula of the resistance constraint condition is as follows:

wherein ,expressed as mth arithmetic resistance value, I _BTYP Representative value of bias current, V, represented as current sense amplifier under test 2-3 _OSMAX Represented as offset voltage maximum, V, of current sense amplifier 2-3 _OL Represented as the lower limit of the output voltage of the current sense amplifier 2-3 to be measured, G _r Represented as measured gain, V, of the current sense amplifier 2-3 under test _OH An upper limit of the output voltage denoted as current sense amplifier 2-3 to be measured;

then, the following operations are performed for each arithmetic resistor, for example, for the mth arithmetic resistorThe mth arithmetic resistance +.>Is connected in series with the current detection amplifier 2-3 to be detected, and the output end of the current detection amplifier 2-3 to be detected detects the corresponding voltage test result +. >

And when all the M arithmetic resistors finish the operation process, obtaining a set of voltage test results.

Then, carrying out difference calculation on the voltage test results corresponding to each adjacent arithmetic resistor to obtain a plurality of voltage test result difference values;

performing product calculation by using the actual gain of the current detection amplifier 2-3 to be detected and the difference value of each resistor to obtain a product calculation result;

averaging the calculation result of each ratio to obtain a bias current, which can be expressed as:

wherein mean (·) represents taking the average value, m=1, 2, & gtis, M-1, G _r Represented as the actual gain of the current sense amplifier 2-3 under test, I _br Represented as the bias current of the current sense amplifier 2-3 under test,expressed as the voltage test result corresponding to the mth arithmetic resistor,/and>expressed as the voltage test result corresponding to the m+1st arithmetic resistor,/for>Expressed as mth arithmetic resistance, +.>Denoted as the m+1th arithmetic resistance.

In some embodiments, in step 101, the obtaining the offset voltage error of the test line where the current detection amplifier to be tested is located includes:

Step B1, obtaining the contact resistance value of a test circuit where the current detection amplifier to be detected is located;

and step B2, carrying out product calculation based on the contact resistance value and the bias current to obtain the offset voltage error.

In the above scheme, the main contact resistance in the test circuit where the current detection amplifier to be tested is located is derived from the electric control devices connected in the test circuit, such as a relay and a test socket, which usually have contact resistance values of tens or even hundreds of milliohms, and after superposition, the bias current of the current detection amplifier supplied by a single power supply easily generates a voltage drop error (i.e. offset voltage error) of a microvoltage level on the bias current, so that the offset voltage error needs to be known.

The manner of obtaining the resistance value of the contact resistor is as follows:

before welding a test circuit board, the electric control device with main contact resistance at milliohm level is used for measuring the contact resistance by using a high-precision digital multimeter based on a four-wire Kelvin resistance measurement method, so that the total contact resistance value is obtained.

Or reserving a test point in a test circuit where the current detection amplifier to be tested is located, and measuring the total contact resistance value in a circuit from the positive input end of the current detection amplifier to the offset voltage adjustment resistor by using a high-precision digital multimeter based on a four-wire Kelvin resistance measurement method.

And then, carrying out product calculation based on the acquired contact resistance value and the acquired bias current to obtain offset voltage errors, wherein the offset voltage errors can be expressed as:

V _ose ＝I _br ×R _c

wherein ,V_ose Expressed as offset voltage error, I _br Expressed as bias current, rc expressed as contact resistance.

In some embodiments, the input end of the current detection amplifier to be detected is connected with a preselected offset voltage adjusting resistor;

step 102, including:

and step C1, increasing the offset voltage of the input end of the current detection amplifier to be detected through the offset voltage adjusting resistor, and obtaining the offset voltage of the adjusted input end.

In the above-described scheme, as shown in fig. 2, the voltage output from the output terminal 2-5 of the current detection amplifier 2-3 to be measured is related to the voltage difference (offset current) between the positive input terminal 2-41 and the negative input terminal 2-42 and the gain of the current detection amplifier 2-3 to be measured.

When the voltage difference (offset current) between the positive input terminal 2-41 and the negative input terminal 2-42 of the current detection amplifier 2-3 to be detected is very low, the output swing characteristic of the current detection amplifier 2-3 to be detected supplied by a single power supply is limited, so that the offset voltage (usually in the microvolts level or below) which is low enough cannot exceed the lower limit of the output voltage of the current detection amplifier 2-3 to be detected supplied by the single power supply after the gain of the current detection amplifier is amplified.

Therefore, the pre-selected offset voltage adjusting resistor 2-2 is connected in series with the positive input end of the current detection amplifier 2-3 to be detected, and the offset current generates voltage on the pre-selected offset voltage adjusting resistor by utilizing the self characteristic of the current detection amplifier 2-3 to be detected, so that the offset voltage of the input end 2-4 of the current detection amplifier 2-3 to be detected is increased, and the corresponding output voltage can reach the output range of the current detection amplifier 2-3 to be detected.

In some embodiments, the process of selecting the offset voltage adjustment resistor includes:

and D1, selecting any test resistor, and obtaining characteristic parameters of the selected any test resistor, wherein the characteristic parameters comprise an accuracy resistance value, a temperature drift resistance value and a theoretical resistance value.

And D2, calculating the error of the actual resistance and the theoretical resistance under the preset temperature condition according to the precision resistance, the temperature drift resistance and the theoretical resistance of the selected any test resistor, and determining the maximum error of the actual resistance and the theoretical resistance of the selected any test resistor.

And D3, obtaining the bias current, the actual gain, the lower limit of the output voltage, the measurement range of the voltage value of the output end, the maximum measurement error of the offset voltage and the theoretical offset voltage of the current detection amplifier to be detected.

Step D4, judging whether any selected test resistor meets a preset offset voltage adjustment resistor constraint condition according to the bias current, the actual gain, the theoretical offset voltage, the offset voltage maximum measurement error, the theoretical resistance value and the maximum error, wherein the preset offset voltage adjustment resistor constraint condition is specifically as follows:

V _OL ＜R _adj ×I _br ×G _r ＜V _range

R _error ×I _br ≤V _os ×E％

wherein ,R_error Representing the maximum error between the actual resistance and the theoretical resistance of any selected test resistor, R _adj Represented as the resistance of any selected test resistor, R _pre Expressed as the precision resistance value of any selected test resistor, R _tse The temperature drift resistance value expressed as any selected test resistor, V _range The measurement range of the voltage value of the output end of the current detection amplifier to be measured is represented as E%, and the maximum measurement error of the offset voltage of the current detection amplifier to be measured is represented as V _OL Represented as the lower limit of the output voltage of the current sense amplifier under test, I _br Expressed as bias current, G _r Representing the actual gain, V, of the current sense amplifier under test _os Expressed as the theoretical offset voltage of the current sense amplifier under test.

And D5, taking the test resistor meeting the constraint condition of the preset offset voltage adjusting resistor as the offset voltage adjusting resistor.

In the above scheme, any one of the test resistors is selected, the resistance, the precision resistance and the temperature drift resistance of the test resistor are obtained, the precision resistance, the temperature drift resistance and the theoretical resistance of the test resistor are utilized to perform error calculation of the actual resistance and the theoretical resistance under the preset temperature condition (which can be set according to specific conditions and is not particularly limited here, preferably based on 25 ℃), specifically, the theoretical resistance and the precision resistance of the test resistor are utilized to perform product calculation to obtain a corresponding product result, then the theoretical resistance and the maximum variation value of the test environment temperature of the test resistor and the temperature drift resistance of the test resistor are utilized to perform product calculation to obtain a corresponding product result, and finally the two product results are added to obtain the maximum error of the actual resistance and the theoretical resistance of the test resistor, which can be expressed as follows:

R _error ＝R _adj ×R _pre +R _adj ×ΔT×R _tse

wherein ,R_error Representing the maximum error between the actual resistance and the theoretical resistance of any selected test resistor, R _adj Represented as the resistance of any selected test resistor, R _pre Expressed as the precision resistance value of any selected test resistor, R _tse The temperature drift resistance value of any selected test resistor is shown, and the delta T is shown as the maximum change value of the test environment temperature.

Judging whether the test resistor meets the preset offset voltage adjustment resistor constraint condition according to the bias current of the current detection amplifier to be detected, the actual gain of the current detection amplifier to be detected, the offset voltage maximum measurement error of the current detection amplifier to be detected, the theoretical resistance value of the selected test resistor and the actual resistance value and theoretical resistance value maximum error of the selected test resistor, so that the resistor is selected, and the test resistor meeting the preset offset voltage adjustment resistor constraint condition is used as the offset voltage adjustment resistor.

In some embodiments, step C1 comprises:

and step C11, obtaining the actual gain of the current detection amplifier to be detected.

And step C12, increasing the offset voltage of the input end of the current detection amplifier to be detected by using the offset voltage adjusting resistor, and detecting a corresponding adjusted output voltage value at the output end of the current detection amplifier to be detected.

And step C13, calculating the ratio of the adjusted output voltage value to the actual gain to obtain the offset voltage of the adjusted input end.

In the above scheme, as shown in fig. 2, the function of the test circuit is switched to the offset voltage test, the switching mode is to close the K3 switch 2-13 in the switch 2-1, and at this time, the test circuit is an offset voltage circuit at the input end 2-4 of the current detection amplifier 2-3 powered by a single power supply, and the offset voltage circuit is started.

The voltage output from the output terminal 2-5 of the current detection amplifier 2-3 to be measured is related to the voltage difference (offset current) between the positive input terminal 2-41 and the negative input terminal 2-42 and the gain of the current detection amplifier 2-3 to be measured, thereby obtaining the actual gain of the current detection amplifier 2-3 to be measured.

The offset voltage adjusting resistor 2-2 which is connected in series with the positive input end 2-41 and the negative input end 2-42 of the current detection amplifier 2-3 to be detected is utilized, the offset voltage adjusting resistor 2-2 is combined with the characteristic of the current detection amplifier 2-3 to be detected, the offset current generates voltage on the offset voltage adjusting resistor 2-2 to be detected, so that the offset voltage of the input end 2-4 of the current detection amplifier 2-3 to be detected is increased, the corresponding output voltage can reach the output range of the current detection amplifier 2-3 to be detected, the corresponding adjusted output voltage value is detected at the output end 2-5 of the current detection amplifier 2-3 to be detected at the moment, in addition, the preset common-mode input voltage can be applied between the positive input end 2-41 and the negative input end 2-42 of the single power current detection amplifier 2-3 to be detected before the adjusted output voltage value is detected (the preset common-mode input voltage can be set according to specific conditions, the applied preset common-mode voltage is not limited).

The adjusted output voltage value represents the voltage generated by gain amplification of the offset voltage of the input end at the output end 2-5 of the current detection amplifier 2-3 to be detected after adjustment.

And finally, calculating the ratio of the adjusted output voltage value to the actual gain to obtain the adjusted input end offset voltage, which can be expressed as:

wherein ,V_ostotal Expressed as offset voltage of input end after adjustment, V _ototal Expressed as the regulated output voltage value, G _r Represented as the actual gain of the current sense amplifier 2-3 to be measured.

In some embodiments, step C11 comprises:

step C111, obtaining multiple groups of differential input voltages of the current detection amplifier to be detected, where each group of differential input voltages includes a first differential input voltage and a second differential input voltage, and adjacent groups of differential input voltages satisfy a first arithmetic condition, where a formula of the first arithmetic condition is:

wherein ,expressed as a first differential input voltage of the n-th set of differential input voltages, ">Expressed as a second differential input voltage of the n-th set of differential input voltages, ">The first differential input voltage, denoted as n+1th group differential input voltage, ">Represented as a second differential input voltage of the n+1 th set of differential input voltages.

And step C112, obtaining the lower limit of the output voltage, the upper limit of the output voltage and the theoretical gain of the current detection amplifier to be detected.

Step C113, wherein the lower limit of the output voltage, the upper limit of the output voltage and the theoretical gain of the current detection amplifier to be detected meet the constraint condition of the differential input voltage, and the constraint condition of the differential input voltage is specifically:

V _OL ＜V _d ×G＜V _OH

wherein ,V_OL Represented as the lower limit of the output voltage of the current sense amplifier under test, V _OH Expressed as the upper limit of the output voltage of the current sense amplifier to be measured, and G expressed as the current to be measuredTheoretical gain of sense amplifier, V _d Represented as any one of any set of differential input voltages.

Step C114, performing the following operations for each set of differential input voltages:

step C1141, applying a first differential input voltage to the current detection amplifier to be detected, and detecting a corresponding first output voltage at an output terminal of the current detection amplifier to be detected.

And step C1142, applying a second differential input voltage to the current detection amplifier to be detected, and detecting a corresponding second output voltage value at the output end of the current detection amplifier to be detected.

And step C1143, performing a difference calculation based on the first output voltage and the second output voltage to obtain a first difference result.

And step C1144, performing a difference calculation on the first differential input voltage and the second differential input voltage to obtain a second difference result.

And step C1145, calculating a ratio by using the first difference result and the second difference result to obtain an actual gain corresponding to the current group of differential input voltages.

And step C115, carrying out average calculation on the actual gain corresponding to each group of differential input voltage to obtain the actual gain.

In the above scheme, as shown in fig. 2, the function of the test circuit is switched to the actual gain test, the switching mode is to close the K1 switch 2-11 in the switch 2-1, and at this time, the test circuit is a gain test circuit at the input end of the current detection amplifier powered by a single power supply, and the actual gain test circuit is started.

For example, N groups of different differential input voltages are selected, each group comprises two differential input voltages, the differential input voltages of adjacent groups meet the first arithmetic condition, which means that the differential input voltages of adjacent groups are equal difference, for example, the two differential input voltages of the nth group are respectively and />The two differential input voltages of the n+1-th group are respectively +.>And and />The method meets the following conditions:

wherein ,expressed as a first differential input voltage of the n-th set of differential input voltages, " >Expressed as a second differential input voltage of the n-th set of differential input voltages, ">The first differential input voltage, denoted as n+1th group differential input voltage, ">Represented as a second differential input voltage of the n+1 th set of differential input voltages.

Any one differential input voltage of the selected N groups of different differential input voltages, the lower limit of the output voltage of the current detection amplifier 2-3 to be detected, the upper limit of the output voltage of the current detection amplifier 2-3 to be detected and the theoretical gain of the current detection amplifier 2-3 to be detected meet the constraint condition of the differential input voltage, and the constraint condition of the differential input voltage is specifically as follows:

V _OL ＜V _d ×G＜V _OH

wherein ,V_OL Represented as the lower limit of the output voltage of the current sense amplifier 2-3 to be measured, V _OH Expressed as the upper limit of the output voltage of the current sense amplifier 2-3 to be measured, G expressed as the theoretical gain of the current sense amplifier 2-3 to be measured, V _d Represented as any one of any set of differential input voltages.

Then, for each set of differential input voltages, for example, for the nth set of differential input voltages, the differential input voltages between the positive input terminals 2-41 and the negative input terminals 2-42 of the single power supply current detection amplifier 2-3 to be tested are applied(i.e., the first differential input voltage), the output voltage value at this time is detected to be +. >(i.e., the first output voltage).

Changing the differential input voltage between the positive input terminal 2-41 and the negative input terminal 2-42 of the single power supply current detection amplifier 2-3 to be detected to(i.e., the second differential input voltage), the output voltage value at the time of detection by the current detection amplifier 2-3 to be detected is +.>(i.e., the second output voltage).

In addition, a predetermined common-mode input voltage (which may be set according to a specific case, and the magnitude of the predetermined common-mode voltage to be applied is not particularly limited here) may be applied in addition to the differential input voltage applied between the positive input terminal 2-41 and the negative input terminal 2-42 of the single power supply current detection amplifier 2-3 to be detected, and the magnitude of the predetermined common-mode input voltage to be applied is not changed.

performing difference calculation on the first differential input voltage and the second differential input voltage to obtain a second difference calculation result;

the ratio calculation is performed by using the first difference result and the second difference result, so as to obtain the actual gain corresponding to the current group of differential input voltages, which can be expressed as follows:

wherein ,denoted as the actual gain corresponding to the n-th set of differential input voltages, ">A first output voltage, denoted as n-th set of differential input voltages, " >A second output voltage, denoted as n-th set of differential input voltages, ">A first differential input voltage, denoted as the nth set of differential input voltages, ">Represented as a second differential input voltage corresponding to the nth set of differential input voltages.

When the N groups of differential input voltages all complete the operation process, a set of actual gains is obtained.

The actual gains (i.e. the set of actual gains) corresponding to each group of differential input voltages are averaged to obtain an actual gain, which can be expressed as:

wherein ,G_r Expressed as actual gain, mean (·) represents taking the average, n=1, 2, the contents of the terms, N,denoted as the nth set of measured gains.

It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.

It should be noted that the foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Based on the same inventive concept, the application also provides a device for testing offset voltage of the current detection amplifier, which corresponds to the method of any embodiment.

Referring to fig. 3, the offset voltage testing apparatus of the current sense amplifier includes:

the acquisition module 301 is configured to acquire an offset voltage adjustment value of a current detection amplifier to be detected and an offset voltage error of a test line where the current detection amplifier to be detected is located;

the adjusting module 302 is configured to adjust the offset voltage of the input end of the current detection amplifier to be detected, and obtain the offset voltage of the input end after adjustment;

and the removing module 303 is configured to remove the offset voltage adjustment value and the offset voltage error from the offset voltage of the adjusted input end, so as to obtain an offset voltage test result.

the adjustment module 302 is specifically configured to:

V _OL ＜R _adj ×I _br ×G _r ＜V _range

R _error ×I _br ≤V _os ×E％

wherein ,R_error Representing the maximum error between the actual resistance and the theoretical resistance of any selected test resistor, R _adj Represented as the resistance of any selected test resistor, R _pre Expressed as the precision resistance value of any selected test resistor, R _tse The temperature drift resistance value expressed as any selected test resistor, V _range The measurement range of the voltage value of the output end of the current detection amplifier to be measured is represented as E%, and the maximum measurement error of the offset voltage of the current detection amplifier to be measured is represented as V _OL Represented as the lower limit of the output voltage of the current sense amplifier under test, I _br Expressed as bias current, G _r Representing the actual gain, V, of the current sense amplifier under test _os The theoretical offset voltage is expressed as a current detection amplifier to be detected;

In some embodiments, the adjustment module 302 includes:

an actual gain acquisition unit configured to acquire an actual gain of the current detection amplifier to be measured;

the adjusting unit is configured to increase the offset voltage of the input end of the current detection amplifier to be detected by utilizing the offset voltage adjusting resistor, and a corresponding adjusted output voltage value is detected at the output end of the current detection amplifier to be detected;

and the ratio calculation unit is configured to perform ratio calculation on the adjusted output voltage value and the actual gain to obtain an adjusted input end offset voltage.

In some embodiments, the actual gain acquisition unit is specifically configured to:

V _OL ＜V _d ×G＜V _OH

wherein ,V_OL Represented as the lower limit of the output voltage of the current sense amplifier under test, V _OH Expressed as the upper limit of the output voltage of the current sense amplifier to be measured, G expressed as the theoretical gain of the current sense amplifier to be measured, V _d Represented as any one of any set of differential input voltages;

the following is performed for each set of differential input voltages:

In some embodiments, the acquisition module 301 includes:

A bias current obtaining unit configured to obtain a bias current of the current detection amplifier to be measured;

and the product calculation unit is configured to calculate the product by using the bias current and the resistance value of the offset voltage adjustment resistor to obtain the offset voltage adjustment value.

In some embodiments, the bias current acquisition unit is specifically configured to:

the following is performed for each arithmetic resistor:

In some embodiments, the acquisition module 301 is specifically configured to:

For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, the functions of each module may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.

The device of the above embodiment is used for implementing the offset voltage testing method of the corresponding current detection amplifier in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein again.

Based on the same inventive concept, the application also provides an electronic device corresponding to the method of any embodiment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the offset voltage testing method of the current detection amplifier according to any embodiment when executing the program.

Fig. 4 shows a more specific hardware architecture of an electronic device according to this embodiment, where the device may include: a processor 401, a memory 402, an input/output interface 403, a communication interface 404, and a bus 405. Wherein the processor 401, the memory 402, the input/output interface 403 and the communication interface 404 are in communication connection with each other inside the device via a bus 405.

The processor 401 may be implemented by a general purpose CPU (Central Processing Unit ), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.

The Memory 402 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 402 may store an operating system and other application programs, and when implementing the solutions provided by the embodiments of the present specification by software or firmware, the relevant program code is stored in memory 402 and invoked for execution by processor 401.

The input/output interface 403 is used to connect with an input/output module to realize information input and output. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.

The communication interface 404 is used to connect a communication module (not shown in the figure) to enable communication interaction between the present device and other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).

Bus 405 includes a path to transfer information between components of the device (e.g., processor 401, memory 402, input/output interface 403, and communication interface 404).

It should be noted that, although the above device only shows the processor 401, the memory 402, the input/output interface 403, the communication interface 404, and the bus 405, in the implementation, the device may further include other components necessary for realizing normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.

The electronic device of the foregoing embodiment is configured to implement the offset voltage testing method of the corresponding current detection amplifier in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein again.

Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to execute the current sense amplifier offset voltage testing method according to any of the embodiments.

The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

The storage medium of the foregoing embodiment stores computer instructions for causing the computer to execute the offset voltage testing method of the current detection amplifier according to any one of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described herein.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.

Claims

1. The offset voltage testing method for the current detection amplifier is characterized by comprising the following steps of:

2. The method of claim 1, wherein the input of the current sense amplifier under test is connected to a preselected offset voltage adjustment resistor;

3. The method of claim 2, wherein the step of selecting the offset voltage adjustment resistor comprises:

V _OL ＜R _adj ×I _br ×G _r ＜V _range

R _error ×I _br ≤V _os ×E％

wherein ,R_error Representing the maximum error between the actual resistance and the theoretical resistance of any selected test resistor, R _adj Represented as the resistance of any selected test resistor, R _pre Expressed as the precision resistance value of any selected test resistor, R _tse The temperature drift resistance value of any selected test resistor is shown, vrange is shown as the output end voltage value measuring range of the current detection amplifier to be measured, E% is shown as the offset voltage maximum measuring error of the current detection amplifier to be measured, and V _OL Expressed as the lower limit of the output voltage of the current sense amplifier under test, ibr expressed as the bias current, G _r Representing the actual gain, V, of the current sense amplifier under test _os The theoretical offset voltage is expressed as a current detection amplifier to be detected;

4. The method according to claim 2, wherein the step of increasing the offset voltage of the input terminal of the current sense amplifier to be measured through the offset voltage adjustment resistor to obtain the adjusted offset voltage of the input terminal comprises:

acquiring the actual gain of the current detection amplifier to be detected;

5. The method of claim 4, wherein the obtaining the actual gain of the current sense amplifier under test comprises:

wherein ,expressed as a first differential input voltage of the n-th set of differential input voltages, " >Expressed as a second differential input voltage of the n-th set of differential input voltages, ">Represented as a first differential input voltage of the n +1 th set of differential input voltages,a second differential input voltage represented as an n+1th group differential input voltage;

V _OL ＜V _d ×G＜V _OH

the following is performed for each set of differential input voltages:

6. The method of claim 1, wherein the obtaining the offset voltage adjustment value of the current sense amplifier under test comprises:

acquiring bias current of the current detection amplifier to be detected;

7. The method of claim 6, wherein the obtaining the bias current of the current sense amplifier under test comprises:

wherein ,expressed as mth arithmetic resistance value, I _BTYP Representative value of bias current, V, expressed as a current sense amplifier under test _OSMAX Represented as current detectionOffset voltage maximum value of sense amplifier, V _OL Expressed as the lower limit of the output voltage of the current sense amplifier to be measured, G _r Expressed as measured gain of current sense amplifier to be measured, V _OH An upper limit of the output voltage, denoted as current sense amplifier to be measured;

the following is performed for each arithmetic resistor:

8. The method of claim 6, wherein the obtaining the offset voltage error of the test circuit in which the current detection amplifier to be tested is located comprises:

9. The utility model provides a current sense amplifier offset voltage testing arrangement which characterized in that includes:

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 8 when the program is executed by the processor.