CN116545231A - Self-adaptive delay compensation current comparison circuit and switching power supply circuit - Google Patents

Self-adaptive delay compensation current comparison circuit and switching power supply circuit Download PDF

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Publication number
CN116545231A
CN116545231A CN202310532221.2A CN202310532221A CN116545231A CN 116545231 A CN116545231 A CN 116545231A CN 202310532221 A CN202310532221 A CN 202310532221A CN 116545231 A CN116545231 A CN 116545231A
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current
voltage
tube
current mirror
mos
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请求不公布姓名
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Shanghai Canrui Technology Co ltd
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Shanghai Canrui Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention provides a current comparison circuit capable of adaptively compensating delay, which comprises a first current mirror, a second current mirror, a current compensation module and a post-stage inverter, wherein the first current mirror is connected with the second current mirror; the low-voltage end of the first current mirror is connected with the high-voltage end of the second current mirror, the connection point is a comparison voltage output end, the comparison voltage output end is set to output comparison voltage, the other low-voltage end of the first current mirror receives sampling current, and the other high-voltage end of the second current mirror receives reference current; the current compensation module is arranged between the input voltage source and the comparison voltage output end and used for providing compensation current; the comparison voltage output end is connected with the input end of the back-stage inverter to output a logic control signal. The invention also provides a corresponding switching power supply circuit. According to the self-adaptive compensation delay current comparison circuit provided by the invention, the additional compensation current module is added to offset the current error problem caused by parasitic delay in the circuit system, so that the accurate inductance current without delay is obtained.

Description

Self-adaptive delay compensation current comparison circuit and switching power supply circuit
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a current comparison circuit capable of adaptively compensating delay.
Background
The current limiting control mode or the zero crossing detection mode is one mode for controlling a power tube in a switching power supply, and the principle is that the current of the power tube is sampled and compared with the internal reference current to control the on-off of the power tube, so that the inductance current is controlled. In the design of a traditional current comparison circuit, due to the existence of parasitic capacitance, response delay exists in the circuit, and then when the power tube is turned off, the sampling current is higher (or lower) than the reference current, so that the actual inductance current value is larger (or smaller) than the ideal inductance current, and the peak (valley) current of the power tube cannot be stabilized. For the current limiting control mode, inaccurate current limiting value can be output due to response delay, and the inductor is damaged due to overlarge current; for zero-crossing detection, if the flywheel is turned off too late, current flows backward, resulting in additional power loss, and if the flywheel is turned off too early, flywheel through the body diode also causes greater body diode power consumption.
As shown in fig. 1, taking a BOOST switching power circuit in peak current mode as an example, the switching power circuit includes an input voltage source Vin, a switching node SW connected to the input voltage source Vin through an energy storage inductor L, and an active switching tube S1 and a freewheeling tube S2 connected to the switching node SW, wherein one end of the freewheeling tube S2 away from the switching node SW is a voltage output end Vout, and the voltage output end Vout is grounded through an output capacitor C. One end of the active switching tube S1 far away from the switching node SW is grounded. A sampling drive tube current I is arranged between the drive switch tube S1 and the ground CS The current sampling module 201 samples the main tube current I CS But because the drive tube current I flowing through the drive tube when the drive switching tube S1 is on CS Equal to the inductor current, so both can be equivalent. The output end of the current sampling module 201 is connected with the input end of a current comparison circuit 202, and the other input end of the current comparison circuit 202 is arranged to receive a reference current I ref The output end of the current comparison circuit 202 is connected with the input end of a logic control module 203, and the two output ends of the logic control module 203 are respectively connected with the gates of the active switching tube S1 and the freewheel tube S2, so that the current comparison circuit 202 will reference the reference current I ref With drive tube current I CS The comparison result is compared and outputted to the logic control module 203 as a logic control signal PWM, so that the logic control module 203 controls the active switching tube S1 and the freewheel tube S2 to be turned on and off.
Common current comparator module as shown in fig. 2, the current comparator module comprises two PMOS transistors (i.e. a first MOS transistor MP1 and a second MOS transistor MP 2) forming a first current mirror, two NMOS transistors (i.e. a third MOS transistor MN1 and a fourth MOS transistor MN 2) forming a second current mirror, and the active transistor current I is conducted through the first current mirror and the second current mirror CS And reference current I ref Compare and convert to a comparison voltage V P Will compare the voltage V P The digital signal PWM is converted by the rear-stage inverter, and the rear-stage inverter is composed of a fifth MOS tube MP3 and a sixth MOS tube MN 3. However, in the circuit, there are many parasitic capacitances in the MOS transistor, such as the main parasitic capacitance including the gate-drain parasitic capacitance C of the second MOS transistor MP2 1 Gate-drain parasitic capacitor C of fourth MOS transistor MN2 2 Gate-drain parasitic capacitor C of sixth MOS transistor MN3 3 Etc., all parasitic capacitances can be equivalently equivalent to an equivalent parasitic capacitance C connected between the comparison voltage output terminal and ground X 。
According to the conventional switching power supply circuit structure as shown in FIG. 1, the inductor current I can be known L And supply voltage V in The relation among the size L of the energy storage inductor and the time t is as follows:
drive tube current I CS The external inductor current is reduced in equal proportion and can be expressed as I cs ＝k*I L Drive tube current I CS The amount of change over time can be expressed as:
as shown in FIG. 2, due to the equivalent parasitic capacitance C X Is present, the flip-flop threshold voltage V of the subsequent inverter TH Equivalent to current-equivalent parasitic capacitance C X Capacitor charging voltage of the subsequent inverter, therefore, flip threshold voltage V TH The method comprises the following steps:
ΔI represents due to equivalent parasitic capacitance C X Is equal to the main tube current I CS And reference current I ref Is a difference in (c). Reference current I in equation (3) ref The value of (2) may be any value, and is related to the specification index.
Therefore, due to the equivalent parasitic capacitance C X The error delay Δt caused is:
as can be seen in fig. 3, C due to parasitic capacitance X Leading to V during the comparison P The point voltage is relatively slowly varying, resulting in a reference current I ref And drive tube current I CS When comparing, the reference current I ref And drive tube current I CS After reaching equality, the voltage V is compared P After a delay of Δt, a period of overshoot will reach the inversion threshold voltage of the subsequent inverter, so that the PWM signal is inverted. Thus, an error is generated between the actual inductor current and the ideal inductor current, and the inductor current is inaccurate.
Disclosure of Invention
The invention aims at a current comparison circuit capable of adaptively compensating delay, so that delay on the structure of the current comparison circuit is avoided, and accurate inductance current without delay is obtained.
In order to achieve the above object, the present invention provides a current comparison circuit for adaptively compensating for delay, which includes a first current mirror, a second current mirror, a current compensation module, and a post-inverter; one of the low-voltage ends of the first current mirror is connected with one of the high-voltage ends of the second current mirror, the connection point is a comparison voltage output end, the comparison voltage output end is set to output comparison voltage, the other low-voltage end of the first current mirror is used as one input end of the current comparison circuit to receive sampling current, and the other high-voltage end of the second current mirror is used as the other input end of the current comparison circuit to receive reference current; the high-voltage end of the first current mirror is connected with an input voltage source, and the low-voltage end of the second current mirror is grounded; the current compensation module is connected between the input voltage source and the comparison voltage output end and is used for providing compensation current; the output end of the comparison voltage is connected with the input end of the rear-stage inverter, and the output end of the rear-stage inverter is set to output a logic control signal.
The first current mirror is composed of a first MOS tube and a second MOS tube, the grid electrodes of the first MOS tube and the second MOS tube are connected with each other, the grid electrodes and the drain electrodes of the first MOS tube are used as one low-voltage end of the first current mirror to be connected with sampling current, the drain electrodes of the second MOS tube are used as the low-voltage end of the first current mirror to be connected with a comparison voltage output end, and the source electrodes of the first MOS tube and the second MOS tube are used as the high-voltage end of the first current mirror to be connected with an input voltage source; the second current mirror is composed of a third MOS tube and a fourth MOS tube, the grid electrodes of the third MOS tube and the grid electrodes of the fourth MOS tube are connected with each other, the grid electrodes and the drain electrodes of the third MOS tube are used as one high-voltage end of the second current mirror to be connected with reference current, the drain electrodes of the fourth MOS tube are used as one high-voltage end of the second current mirror to be connected with a comparison voltage output end, and the source electrodes of the third MOS tube and the fourth MOS tube are used as the low-voltage end of the second current mirror to be grounded.
The grid-drain parasitic capacitor of the second MOS tube is arranged between the grid and the drain of the second MOS tube, and the grid-drain parasitic capacitor of the fourth MOS tube is arranged between the grid and the drain of the fourth MOS tube.
The rear-stage inverter consists of a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a PMOS tube, the sixth MOS tube is an NMOS tube, the grid electrodes of the fifth MOS tube and the sixth MOS tube are connected with each other and serve as input ends of the rear-stage inverter, and the drain electrodes of the fifth MOS tube and the sixth MOS tube are connected with each other and serve as output ends of the rear-stage inverter.
And a gate-drain parasitic capacitor of the sixth MOS transistor is arranged between the gate and the drain of the sixth MOS transistor.
The current compensation module comprises a first voltage dividing resistor and a second voltage dividing resistor which are connected in series between an input voltage source and the ground, wherein the connection point of the first voltage dividing resistor and the second voltage dividing resistor is connected with the positive input end of the amplifier, the negative input end of the amplifier is connected to one end of a third resistor and the source electrode of a seventh MOS tube, the other end of the third resistor is grounded, and the grid electrode of the seventh MOS tube is connected with the output end of the amplifier; the current compensation module further comprises a third current mirror and a fourth current mirror, the high-voltage ends of the third current mirror and the fourth current mirror are connected with an input voltage source, one low-voltage end of the third current mirror is connected with the drain electrode of the seventh MOS tube, one low-voltage end of the fourth current mirror is connected with a fixed bias current, and the other low-voltage end of the third current mirror and the other low-voltage end of the fourth current mirror are connected to serve as output ends of the current compensation module.
The third current mirror is composed of an eighth MOS tube and a ninth MOS tube, the grids of which are connected with each other, the fourth current mirror is composed of a tenth MOS tube and an eleventh MOS tube, the drain electrode and the grid electrode of the eighth MOS tube are used as one low-voltage end of the third current mirror to be connected with the drain electrode of the seventh MOS tube, the grid electrode and the drain electrode of the eleventh MOS tube are used as one low-voltage end of the fourth current mirror to be connected with fixed bias current, and the drain electrode of the ninth MOS tube which is used as one low-voltage end of the third current mirror is connected with the drain electrode of the tenth MOS tube which is used as one low-voltage end of the fourth current mirror; the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube are PMOS tubes, and the seventh MOS tube is NMOS tube.
The compensation current Δi is:
wherein R1 is the resistance of the first voltage dividing resistor, R2 is the resistance of the second voltage dividing resistor, R3 is the resistance of the third resistor, vin is the voltage of the input voltage source, I O Is a fixed bias current.
The invention provides a self-adaptive delay compensation switching power supply circuit which comprises an input voltage source, a switching node connected with the input voltage source through an energy storage inductor, an active switching tube and a follow current tube, wherein a drain electrode of the active switching tube is connected with the switching node, the active switching tube is an NMOS power tube, the follow current tube is a PMOS power tube, a source electrode of the active switching tube is grounded through a ground wire, a source electrode of the follow current tube is a voltage output end of the switching power supply circuit, and the voltage output end is grounded through an output capacitor; the source electrode of the active switching tube is connected with the input end of a current sampling module, the output end of the current sampling module is connected with one input end of a current comparison circuit according to the above to receive sampling current, the other input end of the current comparison circuit is set to receive reference current, the output end of the current comparison circuit is set to obtain logic control signals according to the comparison result of the reference current and the current of the active tube and output the logic control signals, the output end of the current comparison circuit is connected with the input end of the logic control module, the logic control module is provided with two output ends, and the two output ends of the logic control module are respectively connected with the grid electrodes of the active switching tube and the freewheeling tube.
According to the self-adaptive compensation delay current comparison circuit, the additional compensation current module is added to offset the current error problem caused by parasitic delay in the circuit system, so that delay caused by the existence of parasitic capacitance in the current comparison process is avoided, and the accurate inductance current without delay is obtained. By adopting the design method of the current comparator, the compensation current can be adaptively adjusted according to the change of the error, so that the actually generated inductance current is consistent with the ideal inductance current, and the accurate inductance current without delay is obtained.
Drawings
Fig. 1 is a schematic diagram of a conventional DC-DC boosted switching power supply circuit.
Fig. 2 is a schematic circuit diagram of a conventional current comparator.
Fig. 3 is a schematic diagram of current-voltage waveforms of nodes of a conventional current comparator.
Fig. 4 is a schematic diagram of a current compensation circuit for adaptively compensating for delay according to the present invention.
Fig. 5 is a schematic diagram of current-voltage waveforms at nodes of the current comparison circuit for adaptively compensating for delay according to the present invention.
Fig. 6 is a schematic circuit diagram of a current compensation circuit for adaptively compensating for delay according to the present invention.
Detailed Description
In order to make the objects, aspects and advantages of the present invention more apparent, the detailed working principles and the state of the present invention will be described in more detail below with reference to the accompanying drawings. The examples are presented for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
The following is provided to enable the public to make a more clear understanding of the invention, and is intended to enable the person skilled in the art to whom the invention pertains to make it clear that the invention is not set forth in detail below.
The current comparison circuit with self-adaptive compensation delay is suitable for a switching power supply circuit in a current limiting control mode or a zero-crossing detection mode for controlling the on and off of a switching tube in a current comparison mode, and is also suitable for any circuit needing accurate comparison of current, the circuit shown in the figure 1 is only used for explaining the invention, and the current comparison circuit with self-adaptive compensation delay is not limited to the switching power supply circuit.
According to the self-adaptive compensation delay current comparison circuit, the additional compensation current module is added to offset the current error problem caused by parasitic delay in the circuit system, so that delay on the structure of the current comparison circuit is avoided, and the accurate inductance current without delay is obtained.
The current comparison circuit of the adaptive compensation delay of the present invention can be applied to the switching power supply circuit shown in fig. 1, thereby obtaining the switching power supply circuit of the adaptive compensation delay of the present invention. As shown in fig. 1, the switching power supply circuit includes an input voltage source Vin, a switching node SW connected to the input voltage source Vin through an energy storage inductor L, and an active switching tube S1 and a freewheeling tube S2 with drains connected to the switching node SW, wherein the active switching tube S1 is an NMOS power tube, the freewheeling tube S2 is a PMOS power tube, and the freewheeling tube S2 has a body twoThe source electrode of the pole tube D and the active switching tube S1 is grounded through a ground wire, and the source electrode of the follow-up tube S2 is a voltage output end V of the switching power supply circuit out Voltage output terminal V out Through an output capacitor C to ground. The current comparing circuit 100 of the present invention is connected to a current sampling module 201, and when the current comparing circuit of the present invention is applied to the switching power supply circuit shown in fig. 1, the input terminal of the current sampling module 201 is connected to the source of the active switching tube S1 to receive the active tube current I CS The output terminal of the current sampling module 201 is connected to one of the input terminals of the current comparing circuit 100 of the present invention to receive the sampling current, while the other input terminal of the current comparing circuit 100 is arranged to receive the reference current I ref The output of the current comparison circuit 100 is arranged to be dependent on a reference current I ref With drive tube current I CS The comparison result of (a) obtains and outputs a logic control signal PWM, and the output end of the current comparison circuit is connected to the input end of the logic control module 203. The logic control module 203 is arranged to convert the logic control signal PWM into two non-overlapping clock signal outputs. In this embodiment, the logic control module 203 has two output ends, and the two output ends of the logic control module 203 are respectively connected to the gates of the active switching tube S1 and the freewheel tube S2. The current comparison circuit 100 of the present invention, which adaptively compensates for delay errors, is used to obtain accurate inductor current.
The current sampling module can be understood as a current mirror circuit with a gate connected with the S1 tube, but the number of parallel tubes is different, for example, S1 tube m=10000, and sampling tube m=1, so that the sampling current is equal to the current of the S1 tube divided by 10000. The specific ratio value is based on the actual index parameter.
As shown in fig. 4, the current comparing circuit 100 of the present invention is improved over the conventional current comparing circuit by adding a current compensating module 101 to compensate the reference current I ref (i.e. I) ref Subtracting a compensation current delta I from the current to obtain a current-compensated reference current I ref '). The current comparison circuit of the self-adaptive compensation delay100 comprises a first current mirror, a second current mirror, a current compensation module 101 and a post-stage inverter, wherein one of the low voltage ends of the first current mirror is connected with one of the high voltage ends of the second current mirror, and the connection point is a comparison voltage output end which is configured to output a comparison voltage V P The other low-voltage end of the first current mirror is connected with the current I of the driving tube CS (in other embodiments, the drive tube current I CS May be any sampling current), the other high-voltage end of the second current mirror is connected with the reference current I ref The method comprises the steps of carrying out a first treatment on the surface of the The high-voltage end of the first current mirror is connected with an input voltage source Vin, and the low-voltage end of the second current mirror is grounded.
In this embodiment, the first current mirror is composed of a first MOS tube MP1 and a second MOS tube MP2 with gates connected to each other, the first MOS tube MP1 and the second MOS tube MP2 are PMOS tubes, and the gate and the drain of the first MOS tube MP1 are used as a low-voltage end of the first current mirror to connect the current I of the driving tube CS The drain electrode of the second MOS tube MP2 is used as the low voltage end of the first current mirror to be connected with the comparison voltage output end, the source electrodes of the first MOS tube MP1 and the second MOS tube MP2 are used as the high voltage end of the first current mirror to be connected with the input voltage source Vin, and a gate-drain parasitic capacitor C of the second MOS tube MP2 is arranged between the gate electrode and the drain electrode of the second MOS tube MP2 1 。
Similarly, the second current mirror is composed of a third MOS tube MN1 and a fourth MOS tube MN2 with gates connected with each other, the third MOS tube MN1 and the fourth MOS tube MN2 are NMOS tubes, and the gate and the drain of the third MOS tube MN1 are used as a high-voltage end of the second current mirror to be connected with a reference current I ref The drain electrode of the fourth MOS tube MN2 is used as a high-voltage end of the second current mirror to be connected with the comparison voltage output end, the source electrodes of the third MOS tube MN1 and the fourth MOS tube MN2 are used as low-voltage ends of the second current mirror to be grounded, and a gate-drain parasitic capacitor C of the fourth MOS tube MN2 is arranged between the gate electrode and the drain electrode of the fourth MOS tube MN2 2 。
The current compensation module is connected with the input voltage source Vin and the comparison voltage output terminal (which provides the comparison voltage V P ) Is arranged to provide a compensation current deltai.
The output end of the comparison voltage is connected with the input end of the rear-stage inverter, and the output end of the rear-stage inverter is set to output a logic control signal PWM.
In this embodiment, the post-stage inverter is composed of a fifth MOS transistor MP3 and a sixth MOS transistor MN3, where the fifth MOS transistor is a PMOS transistor, and the sixth MOS transistor MN3 is an NMOS transistor. The gates of the fifth MOS transistor MP3 and the sixth MOS transistor MN3 are connected to each other and serve as the input terminal of the post-inverter. The drains of the fifth MOS transistor MP3 and the sixth MOS transistor MN3 are connected with each other and serve as the output end of the post-inverter. A gate-drain parasitic capacitor C of the sixth MOS tube MN3 is arranged between the gate and the drain of the sixth MOS tube MN3 3 。
There are many parasitic capacitances in the MOS transistor, such as the main parasitic capacitance including the gate-drain parasitic capacitance C of the second MOS transistor MP2 1 Gate-drain parasitic capacitor C of fourth MOS transistor MN2 2 Gate-drain parasitic capacitor C of sixth MOS transistor MN3 3 Etc., all parasitic capacitances can be equivalently equivalent to an equivalent parasitic capacitance C connected between the comparison voltage output terminal and ground X 。
Referring to fig. 5, a comparison diagram of voltage and current waveforms of each node in a conventional current comparison circuit and a current comparison circuit added with a current compensation module according to the present invention is shown. For the traditional current comparison circuit, the waveform output by the current comparison circuit passes through the reference current I ref And drive tube current I CS The comparison results in that, ideally, when the two currents at point a are equal, if there is no parasitic capacitance delay, the logic control signal PWM should be inverted at the corresponding point a, but the parasitic delay Δt causes the drive tube current I to exist CS When the current overshoots delta I, the logic control signal PWM turns over, so that the sampling current is inaccurate, and the corresponding inductance current is also inaccurate.
For the current comparison circuit added with the current compensation module, as shown in fig. 4, the current compensation module is added to compare the voltage V P Is compensated by a compensation current DeltaI, which is equivalent to the reference current I as shown in FIG. 5 ref The current is subtracted by a compensation current delta I to obtain a reference current I after current compensation ref ' then it is combined with the main tube current I CS The comparison results in a logic control signal PWM which is ideally at point c (i.e. the current compensated reference current I ref ' and drive tube current I CS Equal), but due to the parasitic delay deltat, the main tube current I should be reversed CS The compensation current delta I is also overshot to reach the inversion threshold voltage of the later-stage inverter so that the logic control signal PWM is inverted, and thus the inversion is just at the point a, and the main tube current I is obtained CS The ideal switching point of the logic control signal PWM is equivalent to that of the conventional current comparison circuit which is not improved. The method can also be regarded as that the delay caused by parasitic capacitance is counteracted, and accurate inductance current is obtained.
The compensation current ΔI is the sampling current error ΔI caused by the existence of the parasitic delay Δt CS 。
In the present embodiment, since the current comparison circuit of the present invention is applied to the switching power supply circuit shown in fig. 1, substituting equation (4) into equation (2) can obtain the sampling current error Δi caused by the existence of the parasitic delay Δt CS The relation of (2) is:
wherein k is the reduction multiple of inductance current, V TH C is the inversion threshold voltage of the back-stage inverter X And L is an energy storage inductance value, which is an equivalent parasitic capacitance, and the values are constant fixed values when the structure of the switching power supply circuit is fixed.
In other embodiments, the current comparison circuit is applicable to any place where accurate comparison of currents is required, and is not limited to a switching power supply circuit. Sampling current error ΔI in different circuits CS The formula of (c) may be specifically adjusted. The examples provided above are intended only to illustrate the invention.
The inventive adaptive delay-compensating current comparison circuit is applicable to any circuit requiring accurate current comparison by compensating for delay, but the formulas provided in the invention are all presented with reference to the switching power supply circuit, i.e. fig. 1, and the corresponding adaptive delay-compensating switching power supply circuit is only one embodiment of the invention.
The variation of the error current DeltaI is only related to the voltage of the input voltage source Vin and is proportional toBecause the input voltage source Vin has a certain application range, the exponential function can be obtained by adopting a linear approximation method on the basis of the input voltage source Vin for the convenience of design:
ΔI≈αVin+I O (6)
wherein alpha is the slope, I O For a fixed bias current, a slope α and a fixed bias current I O Are all constant, and the maximum voltage V of the input voltage source Vin is set within the application range of the power supply voltage INMAX And a minimum voltage value V of the input voltage source Vin INMIN Substituting into the formula (5) to obtain the corresponding maximum compensation current value I INMAX And a minimum compensation current value I INMIN Substituting it into formula (6) to obtain alpha and I O Values.
Based on this, the current compensation module is formed by the following steps as shown in fig. 6: the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series between the input voltage source Vin and the ground, and the connection point of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is connected with the positive input end V+ of the amplifier so as to divide the voltage of the input voltage source Vin in proportion and output the divided voltage to the positive end of the error amplifier. The negative input end V-of the amplifier is connected to one end of the third resistor R3 and the source electrode of the seventh MOS tube MN4, the other end of the third resistor R3 is grounded, the grid electrode of the seventh MOS tube MN4 is connected with the output end of the amplifier, and the seventh MOS tube MN4 is an NMOS tube. The current compensation module further comprises a third current mirror and a fourth current mirror, the high voltage ends of the third current mirror and the fourth current mirror are connected with the input voltage source Vin, one low voltage end of the third current mirror is connected with the drain electrode of the seventh MOS tube MN4, and one low voltage end of the fourth current mirror is connected with the fixed bias current I O Connected with the other low-voltage end of the third current mirror and the fourthThe other low voltage end of the current mirror is connected with the output end of the current compensation module, so that the compensation current which can be output by the output end of the current compensation module is the current of the input voltage source Vin and the fixed bias current I O And the current direction is shown by the arrows in fig. 6.
In this embodiment, the third current mirror is composed of an eighth MOS transistor MP4 and a ninth MOS transistor MP5 with gates connected to each other, the fourth current mirror is composed of a tenth MOS transistor MP6 and an eleventh MOS transistor MP7 with gates connected to each other, the drain electrode and gate electrode of the eighth MOS transistor MP4 are connected to the drain electrode of the seventh MOS transistor MN4 as one low voltage end of the third current mirror, and the gate electrode and drain electrode of the eleventh MOS transistor MP7 are connected to the fixed bias current I as one low voltage end of the fourth current mirror O The drain electrode of the ninth MOS transistor MP5 serving as one low-voltage end of the third current mirror is connected with the drain electrode of the tenth MOS transistor MP6 serving as one low-voltage end of the fourth current mirror. Thus, the current flowing through the seventh MOS transistor MN4 is equal to the current flowing through the ninth MOS transistor MP5, and the current flowing through the tenth MOS transistor MP6 is equal to the fixed bias current I O The current of the ninth MOS transistor MP5 and the current of the tenth MOS transistor MP6 are equal in magnitude, and the sum is delta I current.
In this embodiment, the eighth MOS transistor MP4, the ninth MOS transistor MP5, the tenth MOS transistor MP6, and the eleventh MOS transistor MP7 are PMOS transistors, and the seventh MOS transistor MN4 is an NMOS transistor. Therefore, the ninth MOS transistor MP5 and the tenth MOS transistor MP6 are used for generating equivalent parasitic capacitance C X And (5) charging.
Due toV+ is equal to V-, so the current I flowing through the seventh MOS transistor MN4 MN4 Can be represented by the following formula:
the obtained current I MN4 Fixed bias current I after mirror image and mirror image O The addition results in a compensation current Δi that is linear with the voltage of the input voltage source Vin.
The compensation current Δi is:
wherein the method comprises the steps ofEqual to the constant alpha, I in equation (6) O May be provided by a fixed bias current.
The current comparison circuit of the self-adaptive compensation delay adds a current compensation module to compare voltage V P The injection of the compensation current DeltaI corresponds to the reference current I as shown in FIG. 5 ref Subtracting a compensation current DeltaI to obtain a current-compensated reference current I ref ' the obtained reference current I after current compensation ref ' and drive tube current I CS In comparison, a delay of Δt is further passed where the two are equal, i.e. the main tube current I CS When a compensation current delta I is overshot, the inversion threshold voltage of the rear-stage inverter is reached, and the PWM signal is inverted. And the current I of the main pipe obtained at the moment CS It is the ideal sampling current value required before improvement, i.e. the ideal inductor current value in the application of fig. 1.
Then the compensation current DeltaI obtained above is injected into V as shown in FIG. 4 P The current compensation of the traditional structure can be realized, the influence of parasitic capacitance on circuit delay is counteracted, and the accurate inductance current without delay is obtained.
According to the self-adaptive compensation delay current comparison circuit, the additional compensation current module is added to offset the current error problem caused by parasitic delay in the circuit system, so that delay caused by the existence of parasitic capacitance in the current comparison process is avoided, and the accurate inductance current without delay is obtained.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the present invention can be applied to various circuits that need to cancel parasitic capacitance delay. All simple, equivalent changes and modifications made in accordance with the claims and the specification of this application fall within the scope of the patent claims. The present invention is not described in detail in the conventional art.

Claims (9)

1. The current comparison circuit is characterized by comprising a first current mirror, a second current mirror, a current compensation module and a post-stage inverter;
one of the low voltage ends of the first current mirror is connected with one of the high voltage ends of the second current mirror, the connection point is a comparison voltage output end, the comparison voltage output end is set to output comparison voltage, the other low voltage end of the first current mirror is used as one input end of the current comparison circuit to receive sampling current, and the other high voltage end of the second current mirror is used as the other input end of the current comparison circuit to receive reference current; the high-voltage end of the first current mirror is connected with an input voltage source, and the low-voltage end of the second current mirror is grounded;
the current compensation module is connected between the input voltage source and the comparison voltage output end and is used for providing compensation current;
the output end of the comparison voltage is connected with the input end of the rear-stage inverter, and the output end of the rear-stage inverter is set to output a logic control signal.
2. The current comparison circuit of self-adaptive compensation delay according to claim 1, wherein the first current mirror is composed of a first MOS tube and a second MOS tube, the grid electrodes of the first MOS tube and the second MOS tube are connected with each other, the first MOS tube and the second MOS tube are both PMOS tubes, the grid electrodes and the drain electrodes of the first MOS tube are used as one low-voltage end of the first current mirror to be connected with sampling current, the drain electrodes of the second MOS tube are used as the low-voltage end of the first current mirror to be connected with a comparison voltage output end, and the source electrodes of the first MOS tube and the second MOS tube are used as the high-voltage end of the first current mirror to be connected with an input voltage source;
the second current mirror is composed of a third MOS tube and a fourth MOS tube, the grid electrodes of the third MOS tube and the grid electrodes of the fourth MOS tube are connected with each other, the grid electrodes and the drain electrodes of the third MOS tube are used as one high-voltage end of the second current mirror to be connected with reference current, the drain electrodes of the fourth MOS tube are used as one high-voltage end of the second current mirror to be connected with a comparison voltage output end, and the source electrodes of the third MOS tube and the fourth MOS tube are used as the low-voltage end of the second current mirror to be grounded.
3. The adaptive delay-compensated current comparison circuit of claim 2 wherein a gate-drain parasitic capacitance of the second MOS transistor is provided between the gate and the drain of the second MOS transistor and a gate-drain parasitic capacitance of the fourth MOS transistor is provided between the gate and the drain of the fourth MOS transistor.
4. The adaptive delay-compensated current comparison circuit of claim 1, wherein the post-inverter is composed of a fifth MOS transistor and a sixth MOS transistor, the fifth MOS transistor is a PMOS transistor, the sixth MOS transistor is an NMOS transistor, gates of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as input terminals of the post-inverter, and drains of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as output terminals of the post-inverter.
5. The adaptive delay compensated current comparing circuit of claim 4 wherein a gate-drain parasitic capacitance of the sixth MOS transistor is provided between the gate and the drain of the sixth MOS transistor.
6. The current comparison circuit for adaptively compensating for delay according to claim 1, wherein the current compensation module comprises a first voltage dividing resistor and a second voltage dividing resistor which are connected in series between an input voltage source and ground, a connection point of the first voltage dividing resistor and the second voltage dividing resistor is connected with a positive input end of the amplifier, a negative input end of the amplifier is connected to one end of a third resistor and a source electrode of a seventh MOS tube, the other end of the third resistor is grounded, and a gate electrode of the seventh MOS tube is connected with an output end of the amplifier;
the current compensation module further comprises a third current mirror and a fourth current mirror, the high-voltage ends of the third current mirror and the fourth current mirror are connected with an input voltage source, one low-voltage end of the third current mirror is connected with the drain electrode of the seventh MOS tube, one low-voltage end of the fourth current mirror is connected with a fixed bias current, and the other low-voltage end of the third current mirror and the other low-voltage end of the fourth current mirror are connected to serve as output ends of the current compensation module.
7. The adaptive delay compensating current comparing circuit of claim 6, wherein the third current mirror is composed of an eighth MOS transistor and a ninth MOS transistor, the gates of which are connected to each other, the fourth current mirror is composed of a tenth MOS transistor and an eleventh MOS transistor, the drain and the gate of which are connected to the drain of the seventh MOS transistor as one low voltage end of the third current mirror, the gate and the drain of which are connected to the fixed bias current as one low voltage end of the fourth current mirror, and the drain of the ninth MOS transistor as one low voltage end of the third current mirror is connected to the drain of the tenth MOS transistor as one low voltage end of the fourth current mirror;
the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube are PMOS tubes, and the seventh MOS tube is NMOS tube.
8. The adaptive compensation delay current comparison circuit of claim 7 wherein the compensation current Δi is:
wherein R1 is the resistance of the first voltage dividing resistor, R2 is the resistance of the second voltage dividing resistor, R3 is the resistance of the third resistor, vin is the voltage of the input voltage source, I O Is a fixed bias current.
9. The self-adaptive delay compensation switching power supply circuit is characterized by comprising an input voltage source, a switching node connected with the input voltage source through an energy storage inductor, an active switching tube and a follow-up tube, wherein the drain electrode of the active switching tube is connected with the switching node, the active switching tube is an NMOS power tube, the follow-up tube is a PMOS power tube, the source electrode of the active switching tube is grounded through a ground wire, the source electrode of the follow-up tube is a voltage output end of the switching power supply circuit, and the voltage output end is grounded through an output capacitor;
the source electrode of the active switching tube is connected with the input end of a current sampling module, the output end of the current sampling module is connected with one input end of a current comparison circuit with adaptive compensation delay according to one of claims 1-8 to receive sampling current, the other input end of the current comparison circuit is set to receive reference current, the output end of the current comparison circuit is set to obtain logic control signals according to the comparison result of the reference current and the current of the active tube and output the logic control signals, the output end of the current comparison circuit is connected with the input end of the logic control module, the logic control module is provided with two output ends, and the two output ends of the logic control module are respectively connected with the grid electrodes of the active switching tube and the freewheel tube.
CN202310532221.2A 2023-05-11 2023-05-11 Self-adaptive delay compensation current comparison circuit and switching power supply circuit Pending CN116545231A (en)

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CN202310532221.2A CN116545231A (en) 2023-05-11 2023-05-11 Self-adaptive delay compensation current comparison circuit and switching power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310532221.2A CN116545231A (en) 2023-05-11 2023-05-11 Self-adaptive delay compensation current comparison circuit and switching power supply circuit

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CN116545231A true CN116545231A (en) 2023-08-04

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