CN116544122A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN116544122A
CN116544122A CN202310583960.4A CN202310583960A CN116544122A CN 116544122 A CN116544122 A CN 116544122A CN 202310583960 A CN202310583960 A CN 202310583960A CN 116544122 A CN116544122 A CN 116544122A
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CN
China
Prior art keywords
substrate
chip
semiconductor structure
manufacturing
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310583960.4A
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Chinese (zh)
Inventor
蔡泊廷
魏信兴
蔡昕宏
张竞扬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Mo'er Elite Microelectronics Technology Co ltd
Original Assignee
Wuxi Mo'er Elite Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Mo'er Elite Microelectronics Technology Co ltd filed Critical Wuxi Mo'er Elite Microelectronics Technology Co ltd
Priority to CN202310583960.4A priority Critical patent/CN116544122A/en
Publication of CN116544122A publication Critical patent/CN116544122A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
    • B23K26/3568—Modifying rugosity
    • B23K26/3576—Diminishing rugosity, e.g. grinding; Polishing; Smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Geometry (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor structure and a manufacturing method, wherein the method comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface, the first surface of the substrate is provided with a patch of a first chip and an I/O interface, the substrate and the first chip are subjected to injection molding to form a first packaging layer, and the first surface of the substrate, the I/O interface and the first chip are covered; and thinning the first packaging layer through a laser grinding process, and exposing the I/O interface and the first chip at the same time but not exposing the first chip. According to the invention, plastic package grinding is realized through a laser grinding process, and the surface flatness of the semiconductor material is improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
In the semiconductor manufacturing process, the polishing is required, however, the chemical mechanical polishing process is complex in flow and high in time cost, and meanwhile, the accuracy is also deficient, so that the surface integrity and flatness of the semiconductor material can be damaged.
Therefore, a semiconductor structure and a method for manufacturing the same are needed to improve the surface flatness of the semiconductor material after plastic package grinding.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which are used for solving the problem of complex grinding process of the semiconductor structure.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, including:
providing a substrate, wherein the substrate is provided with a first surface;
the method comprises the steps of performing surface mounting of a first chip and setting of an I/O interface on a first surface of a substrate;
forming a first packaging layer on the substrate and the first chip by injection molding, wherein the first packaging layer covers the first surface of the substrate, the I/O interface and the first chip; and
and thinning the first packaging layer through a laser grinding process, and exposing the I/O interface and the first chip at the same time but not exposing the first chip.
Further, the I/O interface adopts a copper column.
Further, the copper pillars are formed by an electroplating process.
Further, the substrate further comprises a second surface, and the second surface is opposite to the first surface; the method further comprises the steps of:
performing surface mounting of a second chip on the second surface of the substrate;
and forming a second packaging layer on the substrate and the second chip by injection molding, and covering the second surface of the substrate and the second chip.
Further, after the first surface of the substrate is subjected to the surface mounting of the first chip, the substrate and the first chip are subjected to injection molding; and after the second surface of the substrate is subjected to the second chip bonding, before the substrate and the second chip are subjected to injection molding, the method comprises the following steps: and conducting the chip with the substrate.
Further, the device also comprises a passive element arranged on the second surface of the substrate.
Further, the first packaging layer and the second packaging layer are both made of resin.
The invention also provides a semiconductor structure prepared by adopting the method of any one of the above.
Further, the semiconductor package comprises a first packaging layer, wherein the first packaging layer covers the first surface of the substrate and the first chip, copper columns are arranged on the first surface, and the copper columns are exposed out of the first packaging layer.
Further, the semiconductor device further comprises a second packaging layer, wherein the second packaging layer covers the second surface of the substrate, the second chip and the passive element.
Compared with the prior art, the invention has at least the following beneficial effects:
the plastic package grinding is realized through the laser grinding process, and the flatness of the surface of the semiconductor material after the plastic package grinding is improved. In addition, the invention adopts the copper column as the module I/O interface, so that the chip and the patch element on the back surface can be effectively avoided.
Drawings
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a substrate according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a second chip and a passive device formed on a substrate according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a second encapsulation layer formed according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a first chip and an I/O interface formed on a substrate according to an embodiment of the invention;
FIG. 6 is a schematic diagram illustrating a first encapsulation layer formed according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a semiconductor structure obtained after laser polishing according to an embodiment of the present invention.
Detailed Description
A semiconductor structure and method of manufacturing the same of the present invention will be described in more detail below with reference to the accompanying schematic drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1 and 2, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including:
s1, providing a substrate 10, wherein the substrate 10 is provided with a first surface;
s2, performing the placement of the first chip 40 and the I/O interface 50 on the first surface of the substrate 10;
s3, injection molding is performed on the substrate 10 and the first chip 40 to form a first packaging layer 60, and the first surface of the substrate 10, the I/O interface 50 and the first chip 40 are covered; and
s4, thinning the first packaging layer 40 through a laser grinding process, and exposing the I/O interface 50 while not exposing the first chip 40.
In a specific embodiment, in step S1, the first substrate 10 may be a monocrystalline silicon substrate, a polycrystalline silicon substrate, an SOI substrate, or a PCB board, and in addition, a conductive layer may be further disposed in the first substrate, and a buried layer, an ion implantation layer, and the like may be further disposed according to actual needs.
The substrate 10 has two opposite surfaces, i.e., a first surface and a second surface, for example, the first surface may be a back surface and the second surface may be a front surface, wherein the front surface and the back surface may be represented by the upper and lower surfaces of the substrate 10 shown in fig. 2.
In one embodiment, the front surface of the substrate 10 may be processed first, and then the back surface may be processed, and the processing sequence may be changed according to the actual process. The following description will be given by taking front-side processing as an example.
Referring to fig. 3, in one embodiment, the second chip 21 is mounted on the second surface.
Specifically, the second chip 21 is conducted with the substrate 10.
Specifically, the second chip 21 and the substrate 10 may be connected by a wafer bonding film, and the specific process may refer to the prior art, and the description thereof is omitted herein.
Preferably, a passive element 22 is mounted on said second surface.
Referring to fig. 4, in one embodiment, a second encapsulation layer 30 is formed on the substrate 10 and the second chip 21 by injection molding, and covers the second surface of the substrate 10 and the second chip 21.
Specifically, a second encapsulation layer 30 is formed by injection molding on the substrate 10 and the second chip 21, and covers the passive elements 22 mounted on the second surface.
The second encapsulation layer 30 mainly plays a role of protection, and typically, the second encapsulation layer 30 is made of a resin material.
Referring to fig. 5, in step S2, the first chip 40 and the I/O interface 50 are mounted on the back surface, i.e., the first surface, of the substrate 10.
Specifically, the first chip 40 is conducted with the substrate 10.
Specifically, the first chip 40 and the substrate 10 may be connected by a wafer bonding film, and the specific process may refer to the prior art, and the description thereof is omitted herein.
In one embodiment, the I/O interface 50 may be a copper pillar, which may be formed by an electroplating process, or may be formed by other processes, and those skilled in the art may choose the process according to actual needs.
The use of copper pillars as the I/O interface 50 effectively avoids back side elements and chips.
In step S3, referring to fig. 6, a first encapsulation layer 60 is formed on the substrate 10 and the first chip 40 by injection molding, and covers the first surface of the substrate 10, the I/O interface 50 and the first chip 40.
The first encapsulation layer 60 mainly plays a role of protection, and typically, the first encapsulation layer 60 is made of a resin material.
In step S4, referring to fig. 7, the first encapsulation layer 60 is thinned by a laser polishing process, and the I/O interface 50 is exposed while the first chip 40 is not exposed.
Through step S4, the surface of the product can be smoother, and the product can adapt to the requirements of different volumes. The laser grinding process has the advantages of high precision and high efficiency, and can maintain the surface integrity of the semiconductor material while grinding.
In addition, cutting may be performed to obtain the desired product.
With continued reference to fig. 7, in another embodiment, the present invention further provides a semiconductor structure that may be manufactured by the method described in the foregoing embodiments, or may be obtained independently of the foregoing method.
Specifically, the semiconductor structure includes a first encapsulation layer 60, the first encapsulation layer 60 covers the first surface of the substrate 10 and the first chip 40, the first surface is provided with copper pillars 50, and the first encapsulation layer 60 exposes the copper pillars 50.
Preferably, a second encapsulation layer 30 is further included, and the second encapsulation layer 30 covers the second surface of the substrate 10, the second chip 21 and the passive component 22.
In summary, according to the semiconductor structure and the manufacturing method thereof, plastic package grinding is realized through the laser grinding process, and the flatness of the surface of the semiconductor material after plastic package grinding is improved. In addition, the invention adopts the copper column as the module I/O interface, so that the chip and the patch element on the back surface can be effectively avoided.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first surface;
the method comprises the steps of performing surface mounting of a first chip and setting of an I/O interface on a first surface of a substrate;
forming a first packaging layer on the substrate and the first chip by injection molding, wherein the first packaging layer covers the first surface of the substrate, the I/O interface and the first chip; and
the first packaging layer is thinned through a laser grinding process, and the I/O interface is exposed but the first chip is not exposed.
2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the I/O interface is a copper pillar.
3. The method of manufacturing a semiconductor structure of claim 2, wherein the copper pillars are formed using an electroplating process.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the substrate further comprises a second surface, the second surface being disposed opposite the first surface; the method further comprises the steps of:
performing surface mounting of a second chip on the second surface of the substrate;
and forming a second packaging layer on the substrate and the second chip by injection molding, and covering the second surface of the substrate and the second chip.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein after the first surface of the substrate is bonded to the first chip, the substrate and the first chip are injection molded; and after the second surface of the substrate is subjected to the second chip bonding, before the substrate and the second chip are subjected to injection molding, the method comprises the following steps: and conducting the chip with the substrate.
6. The method of manufacturing a semiconductor structure of claim 4, further comprising mounting a passive component on the second surface of the substrate.
7. The method of manufacturing a semiconductor structure according to claim 4, wherein the first encapsulation layer and the second encapsulation layer are both made of resin.
8. A semiconductor structure prepared by the method of any one of claims 1 to 7.
9. The semiconductor structure of claim 8, comprising a first encapsulation layer covering the first surface of the substrate, the first chip, the first surface being provided with copper pillars, the first encapsulation layer exposing the copper pillars.
10. The semiconductor structure of claim 8, further comprising a second encapsulation layer covering the second surface of the substrate, the second chip, and the passive component.
CN202310583960.4A 2023-05-19 2023-05-19 Semiconductor structure and manufacturing method thereof Pending CN116544122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310583960.4A CN116544122A (en) 2023-05-19 2023-05-19 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310583960.4A CN116544122A (en) 2023-05-19 2023-05-19 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN116544122A true CN116544122A (en) 2023-08-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310583960.4A Pending CN116544122A (en) 2023-05-19 2023-05-19 Semiconductor structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN116544122A (en)

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