CN116525674A - LDMOS device - Google Patents
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- CN116525674A CN116525674A CN202210948466.9A CN202210948466A CN116525674A CN 116525674 A CN116525674 A CN 116525674A CN 202210948466 A CN202210948466 A CN 202210948466A CN 116525674 A CN116525674 A CN 116525674A
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- 238000009825 accumulation Methods 0.000 claims abstract description 49
- 210000000746 body region Anatomy 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000000694 effects Effects 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 description 12
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/107—Substrate region of field-effect devices
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Abstract
The embodiment of the application provides an LDMOS device, which comprises: an N-type substrate; a source region and a drain region; the arrangement direction of the source region and the drain region is the length direction of the LDMOS device, and the length extension direction of the drain region is the width direction of the LDMOS device; a body region formed under the source region; a drift region formed between the body region and the drain region; the drift region comprises N-type doped column regions and P-type doped column regions which are alternately arranged along the width direction of the LDMOS device; a grid electrode which is formed above the junction of the body region and the drift region in an insulating manner; the overlapping part of the grid electrode and the N-type doped column region is an N-type accumulation region so as to enhance the accumulation effect; the overlapping part of the grid electrode and the P-type doped column region is an extension region of P-type doping; the length of the overlapped part of the body region and the grid electrode is the effective channel length, and the length L of the N-type accumulation region N Greater than or equal to the effective channel length L G . The embodiment of the application solves the technical problems of large on-resistance and small saturation current of the traditional LDMOS device.
Description
Technical Field
The application relates to the technical field of semiconductor power devices, in particular to an LDMOS device.
Background
Current SiC three-port devices are mainly vertical MOS devices, limited by the thinning process, and difficult to thin and thus difficult to achieve lower voltage devices. The current SiC LDMOS device has low channel mobility, so that the on-resistance of the whole device is large, the saturation current is small, the efficiency of the SiC LDMOS device is far lower than that of a gallium nitride device in the field of lower voltage, and the gallium nitride device cannot be applied to the field of high frequency or wide bandwidth due to poor robustness of the material.
Therefore, the traditional LDMOS device has large on-resistance and small saturation current, and is a technical problem which needs to be solved by the technicians in the field.
The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the application provides an LDMOS device, which aims to solve the technical problems of large on-resistance and small saturation current of the traditional LDMOS device.
The embodiment of the application provides an LDMOS device, which comprises:
an N-type substrate;
the source region and the drain region are arranged at intervals and are formed above the N-type substrate; the arrangement direction of the source region and the drain region is the length direction of the LDMOS device, and the length extension direction of the drain region is the width direction of the LDMOS device;
a body region formed under the source region;
a drift region formed between the body region and the drain region, the drift region being connected to the body region; the drift region comprises N-type doped column regions and P-type doped column regions which are alternately arranged along the width direction of the LDMOS device;
a grid electrode which is formed above the junction of the body region and the drift region in an insulating manner;
wherein, the overlapped part of the grid electrode and the N-type doped column region is an N-type accumulation region so as to enhance the accumulation effect; the overlapped part of the grid electrode and the P-type doped column region is a P-type doped extension region which is used as an auxiliary depletion region of the N-type accumulation region so as to balance the charges of the N-type accumulation region; the length of the overlapped part of the body region and the grid electrode is the effective channel length, and the length L of the N-type accumulation region N Greater than or equal to the effective channel length L G 。
By adopting the technical scheme, the embodiment of the application has the following technical effects:
the effective channel is the overlapping part of the body region and the grid electrode, the overlapping part of the grid electrode and the N-type doped column region is an N-type accumulation region, and the length of the N-type accumulation region is greater than or equal to the length of the effective channel. When a positive voltage is applied to the grid electrode, the N-type accumulation area accumulates electrons, namely the N-type accumulation area enhances the electron accumulation effect, so that the on-state capacity of the LDMOS device is improved, the on-state resistance is reduced, the saturation current is improved, more importantly, the electron movement of the LDMOS device is mainly diffusion movement, the hot carrier injection effect at the edge of the grid electrode is reduced, the reliability of the LDMOS device is improved, the doping concentration of the drift area of the LDMOS device is conveniently further improved, and the on-state resistance is further reduced. The overlapping portion of the gate and the P-doped column region is a P-doped extension region that serves as an auxiliary depletion region for the N-type accumulation region to balance the charge of the N-type accumulation region. According to the LDMOS device, the length of the N-type accumulation region is larger than or equal to the length of the effective channel, so that the electron accumulation effect of the LDMOS device is strong, the on-resistance is low, and the hot carrier injection effect is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic cross-sectional view of an LDMOS device according to an embodiment of the present application;
fig. 2 is a top view of an LDMOS device according to an embodiment of the present application.
Reference numerals:
a gate 20, a gate insulating layer 21, a source region 22, a drain region 23, a body region 24, a body contact region 25,
drift region 26, n-doped column region 26-1, p-doped column region 26-2,
drift region buffer 27, n-type buffer 27-1, p-type buffer 27-2,
second via 28, first via 29, first layer metal 210-1, second layer metal 210-2, first deep via 211, p-type epitaxial layer 212, p-type buffer layer 213, substrate 214.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
Example 1
As shown in fig. 1 and 2, the LDMOS device in the embodiment of the application is a super junction LDMOS device. The LDMOS device of the embodiment of the application comprises:
an N-type substrate 214;
a source region 22 and a drain region 23 disposed at intervals, formed above the N-type substrate 214; the arrangement direction of the source region 22 and the drain region 23 is the length direction of the LDMOS device, and the extension direction of the drain region is the width direction of the LDMOS device;
a body region 24 formed under source region 22;
a drift region 26 formed between the body region 24 and the drain region 23, the drift region being connected to the body region 24; the drift region 26 includes alternately arranged N-type doped column regions 26-1 and P-type doped column regions 26-2 along the width direction of the LDMOS device;
a gate 20 insulated over the junction of the body region 24 and the drift region;
wherein the portion of the gate 20 overlapping the N-doped column region 26-1 is an N-type accumulation region to enhance the accumulation effect; the overlapping portion of gate 20 and P-doped column region 26-2 is an extension region of P-doping as an auxiliary depletion region for the N-type accumulation region to balance the charge of the N-type accumulation region; the length of the overlap of body region 24 and gate 20 is the effective channel length, the length L of the N-type accumulation region N Greater than or equal to the effective channel length L G 。
In the LDMOS device of the embodiment of the present application, the effective channel is the overlapping portion of the body region and the gate, the overlapping portion of the gate 20 and the N-type doped column region 26-1 is an N-type accumulation region, and the length of the N-type accumulation region is greater than or equal to the effective channel length. The N-type accumulation region is donor doped and contributes electrons, when the grid electrode applies voltage exceeding a threshold value, the surface of the channel is an electron layer, electrons are accumulated on the surface of the N-type accumulation region, but the depth of the electron accumulation layer of the N-type accumulation region is deeper, a wider channel is provided for electrons coming from the channel, on one hand, the electrons are not concentrated on the surface any more, so that the problem of hot carrier injection reliability is caused, and on the other hand, the resistance of the whole channel is smaller; also because of this, the N-type accumulation region is more effective than the channel length in the case where the total length between the source region and the drain region is the same. When positive voltage is applied to the grid electrode, the N-type accumulation region accumulates electrons, namely the N-type accumulation region enhances the electron accumulation effect, so that the on-state capacity of the LDMOS device is improved, the on-state resistance is reduced, and the saturation current is improved. More importantly, the electron movement of the LDMOS device is mainly diffusion movement, so that the hot carrier injection effect of the edge of the grid electrode is improved, the reliability of the LDMOS device is improved, the doping concentration of the drift region of the LDMOS device is conveniently further improved, and the on-resistance is further reduced. The overlapping portion of the gate and the P-doped column region is a P-doped extension region that serves as an auxiliary depletion region for the N-type accumulation region to balance the charge of the N-type accumulation region. According to the LDMOS device, the length of the N-type accumulation region is larger than or equal to the length of the effective channel, so that the electron accumulation effect of the LDMOS device is strong, the on-resistance is low, and the hot carrier injection effect is improved.
The drift region 26 is alternately arranged with the N-type doped column regions 26-1 and the P-type doped column regions 26-2 along the width direction of the LDMOS device, and the P/N super junction is utilized to assist in depletion, so that wavy electric field distribution is formed, the electric field of the drift region is balanced, the doping concentration of the drift region is increased, the capacitance is reduced, the saturation current is increased, the on-resistance is reduced, and the electric field is balanced. The requirements of different working voltages of the LDMOS device are met by controlling the size of the drift region in the length direction of the LDMOS device, and the LDMOS device is convenient to realize.
The DMOS device of the embodiment of the application has the advantages that the hot carrier injection effect is reduced due to the LDMOS device, the electric field distribution of the drift region is leveled by utilizing the mutual depletion characteristic of P and N in the N-type doped column region and the P-type doped column region of the drift region, so that the doping concentration of the drift region with higher concentration can be obtained, and the resistance of the drift region is reduced.
Specifically, as shown in fig. 1 and 2, the N-type substrate 214 is an N-type SiC substrate. That is, the LDMOS device in the embodiment of the application is a SiC super junction LDMOS device. The LDMOS is lateral double diffusion metal oxide semiconductor for short, and the Chinese is a lateral diffusion metal oxide semiconductor.
The SiC super junction LDMOS device can utilize the transverse length of the LDMOS device to adjust the working voltage of the device, and realize the high-performance LDMOS device from low voltage to high voltage.
By changing the lateral length of the LDMOS device and the length of the drift region, LDMOS devices with different voltages can be conveniently realized. Whereas for a vertical VDMOS device, low voltage devices can only be realized by thinning the thickness in the vertical direction, devices that are too thin are fragile to be realized.
The SiC super junction LDMOS device can utilize an N-type SiC substrate to manufacture the LDMOS device from low voltage to high voltage, reduces manufacturing cost, improves yield, and improves voltage and reliability of the device by utilizing the buffer layer.
Because of the process difficulty and the cost limitation, only N-type SiC substrates can be produced in mass at present. Whereas conventional LDMOS devices are implemented on P-type substrates. The present invention solves this problem conveniently over an N-type substrate by a P-type buffer layer 213 and a P-type epitaxial layer 212.
Specifically, as shown in fig. 1 and 2, the source region 22 and the drain region 23 are heavily doped N-type; body region 24 is lightly doped N-type; the drift region is lightly doped, specifically, the N-type doped column region 26-1 is lightly doped N-type, and the P-type doped column region 26-2 is lightly doped P-type.
Specifically, in fig. 1, the width direction of the LDMOS device is a direction perpendicular to the paper surface.
Specifically, as shown in fig. 1, source region 22 is located within body region 24, and a portion of the body region is located between source region 22 and drift region 26.
In practice, the gate electrode covers the area between the source and drain regions;
alternatively, the LDMOS device is a high withstand voltage LDMOS device, and the gate electrode must have a predetermined distance from the drain region in the length direction of the LDMOS device. I.e. in the length direction of the LDMOS device, a certain distance must be provided between the gate electrode and the edge of the drain region. If the distance between the gate and drain regions is too small, the breakdown voltage between the drain and source regions will be too small.
In practice, as shown in FIGS. 1 and 2, the length L of the N-type accumulation region N And effective channel length L G The ratio value range of (2) is more than or equal to 1 and less than or equal to 5;
length L of N-type accumulation region N The effective channel length L is the distance of the N-type accumulation region in the length direction of the LDMOS device G Is the distance of the effective channel in the length direction of the LDMOS device. Length L of N-type accumulation region N And effective channel length L G The ratio of (2) is greater than or equal to 1, the electron passage diffusion effect of the N-type accumulation region is enhanced, electrons are far away from the surface, the hot carrier injection effect is improved, and the passage resistance is reduced.
In practice, as shown in fig. 1 and 2, the ratio of the width of the N-type doped column region 26-1 to the width of the P-type doped column region ranges from 1 to 2;
the width of the N-doped column region 26-1 is the distance of the N-doped column region in the width direction of the LDMOS device, and the width of the P-doped column region 26-1 is the distance of the P-doped column region in the width direction of the LDMOS device.
In practice, as shown in fig. 1 and 2, the LDMOS device further comprises a drift region buffer region 27 formed under said drain region 23;
the drift region buffer region 27 comprises N-type buffer regions 27-1 and P-type buffer regions 27-2 which are alternately arranged along the width direction of the LDMOS device;
the N-type buffer area 27-1 is connected with the N-type doped column area 26-1, the P-type buffer area 27-2 is connected with the P-type doped column area 26-2, the P-type buffer area adopts N-type light doping, and the doping concentration of the P-type buffer area is one order of magnitude lower than that of the N-type doped drain area.
The electric field is balanced between the N-type doped column region 26-1 and the drain region through the N-type buffer region 27-1, and the electric field is balanced between the P-type doped column region 26-2 and the drain region through the P-type buffer region 27-2.
Is provided for N-type doped column region 26-1The N-type buffer region 27-1 connected with the P-type buffer region 27-2 is arranged for the P-type doped column region 26-2. The electric fields of the N-type buffer area 27-1 and the P-type buffer area 27-2 are flat drift regions, so that the robustness is enhanced 。 In the place of concentration mutation, according to Maxwell's equation, there is peak electric field, breakdown easily occurs here in operation, concentration is slowly changed, the peak electric field is eliminated, and robustness is improved. The N-type buffer areas 27-1 and the P-type buffer areas 27-2 which are alternately arranged along the width direction of the LDMOS device are arranged in the vertical direction of the LDMOS device, so that the space of the LDMOS device in the width direction is effectively utilized, and the thickness of the LDMOS device is also smaller.
In practice, as shown in FIGS. 1 and 2, the N-doped column region 26-1, the N-buffer region 27-1, and the N-doped drain region 23 are sequentially increased in doping concentration. In this way, the buffer is performed between the N-type doped column region 26-1 and the drain region by the N-type buffer region 27-1, thereby forming a graded concentration profile. Specifically, the N-doped drain region 23 is highly doped, the N-buffer region 27-1 is 1 to 1.5 orders of magnitude lower in concentration than the drain region 23, and the N-doped column region 26-1 is 1 to 1.5 orders of magnitude lower in concentration than the N-buffer region. I.e., from the N-doped column region 26-1, the N-buffer region 27-1 to the N-doped drain region 23, the doping concentration increases by 1 to 1.5 orders of magnitude in sequence.
The P-type doping concentration of the P-type doped column region 26-2, the N-type doping of the P-type buffer region 27-2, to the N-type doped drain region 23, increases in sequence, and increases in sequence by 1 to 1.5 orders of magnitude. In this way, the P-type doped column region 26-2 and the drain region are buffered by the P-type buffer region 27-2 to form a graded concentration profile.
In practice, as shown in fig. 1 and 2, the LDMOS device further comprises:
a P-type buffer layer 213 and a P-type epitaxial layer 212 sequentially disposed from the substrate upward;
the LDMOS device is formed by upwards arranging a substrate, wherein each layer is as follows:
an N-type substrate 214;
a P-type buffer layer 213; the doping concentrations of the P-type buffer layer 213 and the N-type substrate 214 are on the same order of magnitude; the N-type substrate 214 and the P-type buffer layer 213 are both heavily doped N-type;
the P-type epitaxial layer 212 is lightly doped P-type; the P-type epitaxial layer 212 has a doping concentration lower than that of the P-type buffer layer 213;
the N-type doped column region 26-1 of the drift region and the drift region buffer region are lightly doped with N type, and the P-type doped column region 26-2 of the drift region 26 is lightly doped with P type;
the drain region is heavily doped with N type;
wherein, in the vertical direction of the LDMOS device, the difference of doping concentration from the drain region, the drift buffer region, the P-type epitaxial layer 212 and the adjacent region of the P-type buffer layer 213 is less than or equal to an order of magnitude. I.e. in the vertical direction, a graded concentration profile is formed between the drain region and the N-bottom 214 by the drift region 26, the drift region buffer region 27, the P-type epitaxial layer 212 and the P-type buffer layer 213.
Therefore, due to the characteristic of gradual concentration change from the drain region of the LDMOS device to the substrate, good longitudinal gradual change junction surface distribution is formed in the vertical direction of the LDMOS device, and the vertical voltage resistance and the reliability of the LDMOS device are improved. According to Maxwell's equation, there is peak electric field at the place of concentration abrupt change, and the concentration distribution of slowly varying can avoid peak electric field, improves withstand voltage and robustness.
In the implementation, a gradual doping concentration distribution of a body region, a drift region buffer region and a drain region is formed from a source region to a drain region in the length direction of the LDMOS device. The peak electric field caused by concentration abrupt change is avoided. Namely in the length direction of the LDMOS device:
the doping concentration from the drift region 26, the drift region buffer region 27 to the drain region 23 increases sequentially and increases sequentially by 1 to 1.5 orders of magnitude. Specifically, the doping concentration of the drift region buffer region 27 is 1 to 1.5 orders of magnitude higher than that of the drift region 26, and the doping concentration of the drain region 23 is 1 to 1.5 orders of magnitude higher than that of the drift region buffer region 27;
the doping concentration increases sequentially from the drift region 26, the body region 24 to the source region 22, and increases sequentially by 1 to 1.5 orders of magnitude.
There is typically a doping concentration difference of more than 2 orders of magnitude between the drain region and the drift region, where the concentration may be abrupt. The doping concentration of the drift region buffer region is 1 to 1.5 orders of magnitude higher than that of the drift region, and 1 to 1.5 orders of magnitude lower than that of the drain region.
Specifically, as shown in fig. 1 and 2, the body region 24, the drift region 26, and the drift region buffer region 27 are disposed on the P-type buffer layer 213.
In practice, as shown in fig. 1 and 2, the LDMOS device further comprises:
a body contact region 25 which is located on the same layer as the body region 24 and is connected to the body region 24;
a gate insulating layer 21 formed under the gate electrode 20 to insulate the gate electrode;
a first metal layer 210-1, wherein the first metal layer 210-1 is connected to the drain region 23 through the first via 29;
a second layer of metal 210-2, the second layer of metal 210-2 being connected to the substrate through a first deep via 211 and to the source region 22 through a second via 28.
Specifically, the gate insulating layer 21 is a silicon oxide gate oxide layer.
The doping types of the various parts of the LDMOS device are listed below:
the source region 22 is heavily N-doped, the drain region 23 is heavily N-doped, the body region 24 is lightly N-doped,
the drift region is lightly doped: the N-type doped column region 26-1 is lightly doped N-type, the P-type doped column region 26-2 is lightly doped P-type,
the drift region buffer zone is lightly doped with N type, the N type buffer zone 27-1 is lightly doped with N type, and the P type buffer zone 27-2 is lightly doped with N type;
the P-type epitaxial layer 212 is lightly P-doped, the P-type buffer layer 213 is heavily P-doped,
the substrate 214 is heavily doped N-type.
In the description of the present application and its embodiments, it should be understood that the terms "top," "bottom," "height," and the like indicate an orientation or positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
In this application and in its embodiments, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed, unless otherwise explicitly stated and defined as such; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application and in its embodiments, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the present application. The components and arrangements of specific examples are described above in order to simplify the disclosure of this application. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. An LDMOS device, comprising:
an N-type substrate (214);
a source region (22) and a drain region (23) which are arranged at intervals and are formed above the N-type substrate (214); the arrangement direction of the source region (22) and the drain region (23) is the length direction of the LDMOS device, and the extension direction of the drain region is the width direction of the LDMOS device;
a body region (24) formed under the source region (22);
a drift region (26) formed between the body region (24) and the drain region (23), the drift region being connected to the body region (24); the drift region (26) comprises N-type doped column regions (26-1) and P-type doped column regions (26-2) which are alternately arranged along the width direction of the LDMOS device;
a gate electrode (20) formed above the junction of the body region (24) and the drift region in an insulating manner;
wherein the overlapping portion of the gate electrode (20) and the N-type doped column region (26-1) is an N-type accumulation region to enhance the accumulation effect; the overlapping part of the grid electrode (20) and the P-type doped column region (26-2) is a P-type doped extension region which is used as an auxiliary depletion region of the N-type accumulation region to balance the charges of the N-type accumulation region; the length of the overlapping part of the body region (24) and the gate electrode (20) is the effective channel length, and the length L of the N-type accumulation region N Greater than or equal to the effective channel length L G 。
2. The LDMOS device of claim 1, wherein the ratio of the length of the N-type accumulation region to the effective channel length ranges from 1 to 5;
the length of the N-type accumulation region is the distance of the N-type accumulation region in the length direction of the LDMOS device, and the effective channel length is the distance of the effective channel in the length direction of the LDMOS device.
3. The LDMOS device of claim 2, wherein the ratio of the width of the N-type doped column region (26-1) to the width of the P-type doped column region has a value in the range of 1 to 2;
the width of the N-type doped column region (26-1) is the distance of the N-type doped column region in the width direction of the LDMOS device, and the width of the P-type doped column region (26-2) is the distance of the P-type doped column region in the width direction of the LDMOS device.
4. The LDMOS device of claim 1, wherein the gate electrode covers an area between the source region and the drain region;
alternatively, the LDMOS device is a high-voltage-resistant LDMOS device, and the grid electrode is provided with a preset distance between the length direction of the LDMOS device and the drain region.
5. The LDMOS device of any of claims 1 to 4, further comprising a drift region buffer region (27) formed under said drain region (23);
the drift region buffer region (27) comprises N-type buffer regions (27-1) and P-type buffer regions (27-2) which are alternately arranged along the width direction of the LDMOS device;
the N-type buffer area (27-1) is connected with the N-type doped column area (26-1), and the P-type buffer area (27-2) is lightly doped with N-type impurities and is connected with the P-type doped column area (26-2).
6. The LDMOS device of claim 5, wherein the N-type buffer region (27-1) has a higher doping concentration than the N-type doped column region (26-1);
the N-type doping concentration of the P-type buffer region (27-2) is higher than that of the P-type doped column region (26-2).
7. The LDMOS device of claim 6, further comprising:
and the P-type buffer layer (213) and the P-type epitaxial layer (212) are sequentially arranged from the substrate upwards.
8. The LDMOS device of claim 7, wherein the LDMOS device is turned up from the substrate, each layer being:
-said N-type substrate (214);
-said P-type buffer layer (213); the doping concentrations of the P-type buffer layer (213) and the N-type substrate (214) are on the same order of magnitude;
the P-type epitaxial layer (212) is lightly doped with P-type materials; the doping concentration of the P-type epitaxial layer (212) is lower than that of the P-type buffer layer (213);
the N-type doped column region (26-1) of the drift region (26) and the drift region buffer region (27) are lightly doped with N type, and the P-type doped column region (26-2) of the drift region (26) is lightly doped with P type;
the drain region is heavily doped with N type;
wherein, in the vertical direction of the LDMOS device, the difference of doping concentration from the drain region, the drift buffer region, the P-type epitaxial layer (212) to the adjacent region of the P-type buffer layer (213) is less than or equal to an order of magnitude.
9. The LDMOS device of claim 8, wherein, in a length direction of the LDMOS device, wherein:
the doping concentration from the drift region (26) and the drift region buffer region (27) to the drain region (23) increases sequentially by 1 to 1.5 orders of magnitude;
the doping concentration increases from the drift region (26), the body region (24) to the source region (22) in sequence and increases by 1 to 1.5 orders of magnitude in sequence, the doping concentration at the interface of the drift region (26) and the body region (24) being comparable.
10. The LDMOS device of claim 9, further comprising:
a body contact region (25) which is located on the same layer as the body region (24) and is connected to the body region (24);
a gate insulating layer (21) formed under the gate electrode (20) to insulate the gate electrode;
a first layer of metal (210-1), the first layer of metal (210-1) being connected to the drain region (23) through a first via (29);
a second layer of metal (210-2), the second layer of metal (210-2) being connected to the substrate through the first deep via (211) and to the source region (22) through the second via (28).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210948466.9A CN116525674A (en) | 2022-08-09 | 2022-08-09 | LDMOS device |
| PCT/CN2023/108133 WO2024032337A1 (en) | 2022-08-09 | 2023-07-19 | Ldmos device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210948466.9A CN116525674A (en) | 2022-08-09 | 2022-08-09 | LDMOS device |
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| CN116525674A true CN116525674A (en) | 2023-08-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210948466.9A Pending CN116525674A (en) | 2022-08-09 | 2022-08-09 | LDMOS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7365402B2 (en) * | 2005-01-06 | 2008-04-29 | Infineon Technologies Ag | LDMOS transistor |
| CN103441147B (en) * | 2013-08-09 | 2016-01-20 | 电子科技大学 | A kind of horizontal SOI power semiconductor device |
| CN105789314A (en) * | 2016-03-18 | 2016-07-20 | 电子科技大学 | Transverse SOI power LDMOS |
| CN109935633B (en) * | 2017-12-15 | 2022-07-08 | 深圳尚阳通科技有限公司 | LDMOS device |
| CN114551595B (en) * | 2020-11-20 | 2023-10-31 | 苏州华太电子技术股份有限公司 | Channel doping modulation RFLDMOS device applied to radio frequency amplification and manufacturing method thereof |
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