CN116521595A - PCIe bus device, PCIe signal control method, PCIe signal control device and storage medium - Google Patents
PCIe bus device, PCIe signal control method, PCIe signal control device and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to the technical field of computers, and discloses PCIe bus equipment, a PCIe signal control method, a PCIe signal control device and a storage medium, wherein the PCIe bus equipment comprises: the system comprises a processor, a signal compensation chip, a logic power supply and a PCIe interface; the PCIe interface is connected with the signal compensation chip bus, and the signal compensation chip is connected with the processor bus; the PCIe interface is connected with a logic power supply; the logic power supply is connected with the signal compensation chip. The invention realizes the effect of reducing the power consumption of the signal compensation chip aiming at PCIe bus products.
Description
Technical Field
The invention relates to the technical field of computers, in particular to PCIe bus equipment, a PCIe signal control method, a PCIe signal control device and a storage medium.
Background
Along with the update iteration of the PCIe bus at present, the signal transmission speed is continuously increased, so that the loss on the PCB board is larger and larger, and the system design uses a signal compensation chip to perform signal enhancement in order to ensure the signal quality of the PCIe bus, so that PCIe interfaces (including a native PCIe slot and an SFF-8639 interface for plugging NVMe equipment based on the PCIe bus) designed on the computer motherboard all use the signal compensation chip to strengthen PCIe signals.
However, in actual use, the user does not have to insert an add-on card into the PCIe interface, but the designed signal compensation chip may remain in a standby state and consume power continuously, which may adversely affect the system power consumption.
Disclosure of Invention
In view of the above, the present invention provides a PCIe bus device, a PCIe signal control method, a PCIe signal control device, and a storage medium, so as to solve the problem that a signal compensation chip is kept in a standby state for a long time and continuously consumes power.
In a first aspect, the present invention provides a PCIe bus device comprising: the system comprises a processor, a signal compensation chip, a logic power supply and a PCIe interface; the PCIe interface is connected with the signal compensation chip bus, and the signal compensation chip is connected with the processor bus; the PCIe interface is connected with the logic power supply; the logic power supply is connected with the signal compensation chip.
In the embodiment, a logic power supply is deployed, and an in-place signal through a PCIe card machine is connected with a PCIe interface and a signal compensation chip. When the PCIe interface is inserted with the external card, the logic power supply can take the bit signal for detecting the insertion of the external card as an enabling signal, output voltage supplies power for the signal compensation chip, and meanwhile, the bit signal for detecting the insertion of the external card is taken as a power-off signal, and no output voltage supplies power for the signal compensation chip. By the mode, the signal compensation chip is prevented from being kept in a standby state for a long time and continuously consuming electricity, and the purpose of saving electric energy is achieved.
In an alternative embodiment, the logic power supply includes a complex programmable logic device and a power module, and the PCIe interface is an SFF-8639 interface; the complex programmable logic device is respectively connected with the processor, the PCIe interface and the power supply module; the power module is connected with the signal compensation chip.
Typically, the hot plug of the SFF-8639 interface NVME protocol device at power-on also requires configuration of the corresponding hot plug and hot remove procedures. According to the embodiment, whether the additional card is inserted into the SFF-8639 interface is detected through the on-site signal, when the additional card is not inserted into the SFF-8639 interface, the power supply module can be controlled by the complex programmable logic device to stop supplying power to the signal compensation chip, when the additional card is inserted into the SFF-8639 interface, the signal compensation chip can be controlled by the complex programmable logic device to be started by the power supply module, the time sequence of a power supply is ensured, and then a processor is informed to operate a hot plug-in program to establish communication connection with the PCIe interface, so that the inserted additional card is read. By the mode, the signal compensation chip is prevented from being kept in a standby state for a long time and continuously consuming electricity, and the purpose of saving electric energy is achieved. When the SFF-8639 interface pulls out the additional card, the complex programmable logic device firstly informs the processor to run the heat removing program, ensures that the process of pulling out the additional card is protected by the heat removing program, avoids faults caused by pulling out the additional card, and then sends a power-off signal to the power module so as to enable the power module to be closed, thereby achieving the purpose of saving electric energy.
In an alternative embodiment, the logic power supply is a dc-dc converter or a MOS transistor switching power supply.
The logic power supply provided in this embodiment is determined according to the current attribute of the upper power supply, and when the upper power supply is direct current, the logic power supply can be deployed as a dc-dc converter, so as to convert the voltage of the upper power supply into a voltage suitable for the signal compensation chip, and flexibly control the start and stop of the signal compensation chip. When the upper power supply is alternating current, the logic power supply can be deployed as an MOS tube switching power supply, so that the voltage of the upper power supply is converted into the voltage matched with the signal compensation chip, and the starting and stopping of the signal compensation chip are flexibly controlled.
In an alternative embodiment, the signal compensation chip is a Re-timer chip or a Re-driver chip.
The embodiment is based on the better effect of reducing physical loss of the Re-timer chip compared with the Re-driver chip and the low delay of the Re-driver chip, so that the signal compensation chip is flexibly selected according to the actual scene requirement of a user.
In a second aspect, the present invention provides a PCIe signal control method, which is characterized by being applied to a logic power supply, where the method includes: judging whether an external card is inserted into the PCIe interface through the in-place signal; when the in-place signal representation is not inserted into the externally added card, no voltage is output to a signal compensation chip; and outputting voltage to the signal compensation chip when the bit signal representation is inserted into the externally applied card.
In the embodiment, a logic power supply is deployed, and an in-place signal through a PCIe card machine is connected with a PCIe interface and a signal compensation chip. When the external card is inserted into the PCIe interface, the logic power supply can take the in-place signal for detecting the insertion of the external card as an enabling signal, output voltage supplies power for the signal compensation chip, and meanwhile, the in-place signal which changes after the external card is pulled out is taken as a power-off signal to inform the logic power supply that the voltage is not output to supply power for the signal compensation chip. By the mode, the signal compensation chip is prevented from being kept in a standby state for a long time and continuously consuming electricity, and the purpose of saving electric energy is achieved.
The logic power supply comprises a complex programmable logic device and a power supply module, the PCIe interface is an SFF-8639 interface, the method is applied to the complex programmable logic device, and when the bit signal characterization is not inserted into the externally added card, the method does not output voltage to a signal compensation chip and comprises the following steps: and when the in-place signal represents that the external card is not inserted, sending a power-off signal to a power module so as to enable the power module to be closed.
According to the embodiment, by arranging the complex programmable logic device, whether the additional card is inserted into the SFF-8639 interface connected with the complex programmable logic device or not is detected through the in-place signal, and when the additional card is not inserted into the SFF-8639 interface, the complex programmable logic device can control the power supply module to stop supplying power to the signal compensation chip, so that the purpose of saving electric energy is achieved.
In an alternative embodiment, said outputting a voltage to said signal compensation chip when said bit signal characterization inserts said add-on card comprises: and when the bit signal representation is inserted into the external card, transmitting an enabling signal to the power supply module so that the power supply module responds to the enabling signal to start to supply power for the signal compensation chip.
In an alternative embodiment, after sending an enable signal to the power module, the method further comprises: and sending a first notification signal to a processor so that the processor runs a hot plug-in program, and establishing communication connection with the PCIe interface through the signal compensation chip.
According to the embodiment, whether the additional card is inserted into the SFF-8639 interface is detected through the on-site signal, when the additional card is inserted into the SFF-8639 interface, the complex programmable logic device can control the power module to start, power is firstly supplied to the signal compensation chip, the time sequence of the power is ensured, the processor is informed to operate the hot plug-in program, the inserted additional card can be timely read by the processor, time sequence errors cannot be generated due to untimely starting of the signal compensation chip, and the problem that the additional card cannot be successfully read by the processor in a starting state is avoided.
In an alternative embodiment, the method further comprises: judging whether the PCIe interface pulls out the external card or not through the in-place signal; when the on-site signal characterizes that the add-on card is pulled out, sending a second notification signal to the processor so that the processor runs a heat removal program; and sending a power-off signal to the power module so as to enable the power module to be turned off.
According to the embodiment, whether the additional card is pulled out of the SFF-8639 interface is detected through the on-site signal, when the additional card is pulled out of the SFF-8639 interface, the processor is firstly informed by the complex programmable logic device to operate a heat removal program, the process of pulling out the additional card is protected by the heat removal program, faults caused by pulling out the additional card are avoided, then an electrical signal is sent to a logic power supply, so that the logic power supply is closed and stopped to supply power for the signal compensation chip, and the purpose of saving electric energy is achieved.
In a third aspect, the present invention provides a PCIe signal control device, which is applied to a logic power supply, the device including: the in-place detection module is used for judging whether the PCIe interface is inserted with an add-on card or not through the in-place signal; the power-off module is used for not outputting voltage to the signal compensation chip when the in-place signal representation is not inserted into the external card; and the power-on module is used for outputting voltage to the signal compensation chip when the in-place signal representation is inserted into the externally-added card.
In a fourth aspect, the present invention provides a computer readable storage medium, where computer instructions are stored, where the computer instructions are configured to cause a computer to perform the PCIe signal control method of the second aspect or any one of the corresponding embodiments of the second aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a PCIE bus connection structure diagram of the related art;
FIG. 2 is a schematic diagram of a PCIe bus device in accordance with an embodiment of the invention;
FIG. 3 is another schematic diagram of a PCIe bus device in accordance with an embodiment of the invention;
FIG. 4 is a flowchart of a PCIe signal control method according to an embodiment of the invention;
FIG. 5 is another flow chart of a PCIe signal control method according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a PCIe signal control device according to an embodiment of the invention;
fig. 7 is another schematic structural diagram of a PCIe signal control device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Currently, in the field of computer technology, in order to improve the quality of PCIe signals, 3 main schemes are generally included. The first is to select a better PCB board to overcome PCIe loss, because the better PCB board affects the overall PCB board at a high cost, overcoming PCIe signal loss through the PCB board is often the most costly solution, and may not necessarily satisfy the entire PCIe loss. The second is to solve PCIe loss through the cable, because the loss of the cable at each inch length is only 25% of the equivalent PCB, for a system with only a few high-speed signal requirements, it is most preferable to solve the problem through the cable inside the chassis, but the cable has the disadvantage that the number of signal bearers of a single cable is limited, the cable inside the chassis will cause wind shielding, the heat dissipation performance of the computer is affected, and the cable needs to be designed and fixed additionally, which has a cost problem. In the third embodiment, as shown in fig. 1, once the inserted PCIe native interface device or NVMe device at the end is not present, the signal compensation chip is in a standby state, which results in continuous power consumption, and this results in a larger power consumption for the customer without the device requirement, which results in a lower product competitiveness of the scheme of the signal compensation chip.
Based on the above, the invention provides PCIe bus equipment, which can solve the problem of greater power consumption. As shown in fig. 2, a PCIe bus device includes: processor 001, signal compensation chip 002, logic power 003 and PCIe interface 004. The PCIe interface 004 is connected with the signal compensation chip 002 bus, and the signal compensation chip 002 is connected with the processor 001 bus; the PCIe interface 004 is connected with the logic power supply 003; the logic power supply 003 is connected to the signal compensation chip 002.
In particular, the processor 001 may be a central processor, a network processor, or a combination thereof. The processor 001 may further include a hardware chip, where the hardware chip may be an application specific integrated circuit, a programmable logic device or a combination thereof, and the programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic or any combination thereof. PCIe interfaces 004 include, but are not limited to PCIe slots such as PCIe 1, PCIe 4, PCIe 8, PCIe 16, etc., and SFF-8639 interfaces for interfacing with devices such as video modules, audio modules, graphics cards, memory, hard disks, etc. In this embodiment, logic power 003 is deployed and PCIe interface 004 and logic power 003 are connected by an in-place signal circuit, the in-place signal is a card detection signal of a PCIe bus, the current specification corresponds to PCIe slots or SFF-8639 interfaces, different in-place detection signals are usually used, which is related to the device type of interface interfacing, in this embodiment, the in-place detection signal of PCIe slots uses prsnt2# signals of the common specification, and SFF-8639 interfaces use ifdet#. Based on the circuit, when the computer is started, the logic power supply 003 judges whether the PCIe interface 004 is inserted with an external card or not through the in-place signal; when the external card is not inserted in the in-place signal representation, namely, no voltage is output to the signal compensation chip 002, the power-off of the signal compensation chip 002 is kept, and when the external card is inserted in the in-place signal representation, the voltage is output to the signal compensation chip 002, so that the signal compensation chip 002 starts to work. Meanwhile, in the running process of the computer, whether some additional cards supporting hot plug are inserted into the slots can be judged through the in-place signals, so that the power-off and the starting of the signal compensation chip 002 are controlled. By this way, the signal compensation chip 002 is prevented from being kept in a standby state for a long time and continuously consuming electricity, and the purpose of saving electric energy is achieved.
Taking a specific embodiment as an example, assuming PCIe interface 004 is a PCIe slot, logic power supply 003 may employ a separate dc-dc converter or MOS transistor switching power supply to respond to the bit signal. When the PCIe slot is inserted into the PCIe AIC device, the prsnt2# signal is detected to be at a low level, which indicates that an additional card is inserted into the slot, so that the logic power supply 003 responds to the low level to start the signal compensation chip 002, and when the PCIe slot is not inserted into the PCIe AIC device, the prsnt2# signal is detected to be at a high level, which indicates that no additional card is inserted into the slot, so that the logic power supply 003 responds to the high level to not supply power to the signal compensation chip 002, so that the signal compensation chip 002 is turned off.
Taking a specific embodiment as an example, assuming PCIe interface 004 is a PCIe slot, logic power supply 003 may comprise a power block (dc-dc converter or MOS transistor switching power supply) and complex programmable logic devices to respond to the on-bit signals. The complex programmable logic device is connected with the PCIe slot, the PCIe slot is connected with the power module, and the power module is connected with the signal compensation chip 002. When the PCIe slot is inserted into the PCIe AIC device, the PRSNT2# signal is detected to be low level, the fact that the external card is inserted into the slot is indicated, the signal reaches the complex programmable logic device, the complex programmable logic device sends a power-on signal to the power module to enable the power module to supply power for the signal compensation chip 002, when the PCIe slot is not inserted into the PCIe AIC device, the PRSNT2# signal is detected to be high level, the fact that the external card is not inserted into the slot is indicated, and accordingly the complex programmable logic device responds to the high level, sends a power-down signal to the power module, the power module does not supply power to the signal compensation chip 002, and the signal compensation chip 002 is closed.
In some alternative embodiments, the logic power supply 003 includes a complex programmable logic device 005 and a power supply module 006, the PCIe interface 004 being an SFF-8639 interface; the complex programmable logic device 005 is respectively connected with the processor 001, the PCIe interface 004 and the power module 006; the power module 006 is connected to the signal compensation chip 002.
In some application scenarios, PCIe interface 004 is an SFF-8639 interface based on NVMe protocol, and is mainly used for inserting memories such as NVMe solid state disks, and may also be used for inserting other add-on cards such as NVMe wireless network cards. Therefore, high-speed PCIe transmission is realized through the NVMe transmission protocol, and the performance and the speed of the externally added card are improved. However, the hot plug of the add-on card of the slot requires the configuration of the corresponding hot plug and hot remove program to implement the hot plug, so if a dc-dc converter or MOS transistor switching power supply is used alone as the logic power supply 003, the hot plug program cannot be run in response to the in-place signal.
Based on this, the PCIe bus device provided in this embodiment can also solve the above-mentioned problem of greater power consumption in an application scenario of hot plug of the SFF-8639 interface. As shown in fig. 3, a PCIe bus device includes: complex programmable logic device 005, processor 001, signal compensation chip 002, power module 006, and PCIe bus based SFF-8639 interface (PCIe interface 004); the SFF-8639 interface is connected with the signal compensation chip 002 bus, and the signal compensation chip 002 is connected with the processor 001 bus; the complex programmable logic device 005 is respectively connected with the processor 001, the SFF-8639 interface and the power module 006 bus; the power module 006 is connected to the signal compensation chip 002.
In particular, complex programmable logic devices 005 (Complex Programmable Logic Device, CPLD) deployed by embodiments of the present invention are high-density, high-speed, and low-power programmable logic devices. The CPLD is mainly composed of a logic block, a programmable interconnection channel and an I/O block. Compared with PLD, CPLD has more product items, more macro units and more I/O ports, thereby realizing more flexible control logic such as signal judgment, signal control and the like. The programmable logic device 005 is mainly used for detecting whether the additional card is inserted into the SFF-8639 interface through the bit signal IfDet# and coordinating the power supply of the signal compensation chip 002 and the operation of the hot plug program according to the insertion condition. In the embodiment of the invention, the in-place detection signal adopts an IfDet# signal which is commonly specified in the specification, the IfDet# is a long pin signal and is used for in-place detection of the NVMe external card, and when the NVMe disc is inserted and pulled out, the signal is pulled down and pulled up, so that whether the external card is inserted or not in a starting state is judged through in-place detection. The processor 001 may be a central processor, a network processor, or a combination thereof. The processor 001 may further include a hardware chip, which may be an application specific integrated circuit, a programmable logic device, or a combination thereof. Processor 001 is different from the model typically adopted by complex programmable logic device 005 due to the limitation of functional conditions, for example, processor 001 adopts the core series of x86 architecture, and complex programmable logic device 005 adopts the XC9500/XL/XV series of Xilinx corporation. However, in some low power devices, the models of the two devices may be the same, for example, XC9500/XL/XV series of Xilinx company is adopted. In this embodiment, processor 001 communicates with complex programmable logic device 005 via pehp_i2c protocol. The processor 001 and the complex programmable logic device 005 in the PCIe bus device may be regarded as a master-slave dual core, where the processor 001 is used as a master core, and connected to the SFF-8639 interface through the signal compensation chip 002, and used for reading data of the add-on card such as the solid state disk, and the CPLD is used as a slave core, and used for detecting whether the SFF-8639 interface inserts the add-on card.
Through the above components, the embodiment of the invention detects whether the connected SFF-8639 interface is inserted with an add-on card based on the complex programmable logic device 005 which is deployed to receive the bit signal of the SFF-8639 interface. When the SFF-8639 interface is not provided with an additional card, the power module 006 is controlled to be turned off by the power-off signal by the complex programmable logic device 005, so that the power supply to the signal compensation chip 002 is stopped, and the signal compensation chip 002 is in an inactive state. When the SFF-8639 interface is inserted with an add-on card, the complex programmable logic device 005 firstly controls the power module 006 to start through the enabling signal, and supplies power for the signal compensation chip 002 so as to ensure the time sequence of the power supply. The processor 001 is then controlled to run a hot plug-in program to cause the processor 001 to establish a communication connection with the PCIe interface 004, thereby reading the inserted add-on card. When the additional card is pulled out of the SFF-8639 interface, the complex programmable logic device 005 firstly informs the processor 001 to operate the heat removal program, so that the process of pulling out the additional card is protected by the heat removal program, faults caused by pulling out the additional card are avoided, and then a power-off signal is sent to the power module 006, so that the power module 006 is closed to stop supplying power to the signal compensation chip 002, and the purpose of saving electric energy is achieved. Through the technical scheme provided by the embodiment, the signal compensation chip 002 is prevented from continuously consuming power in a standby state for a long time, the purpose of saving electric energy is achieved, meanwhile, system errors caused by a power supply time sequence problem are avoided, and the method is suitable for hot plug application scenes of SFF-8639 interfaces.
In some alternative implementations, the power module 006 used in the embodiments of the present invention may be a dc-dc converter, or may be a MOS transistor switching power supply.
Specifically, the power module 006 provided in this embodiment is flexibly determined according to the current attribute of the upper power supply, and when the upper power supply is dc, the power module 006 may be disposed as a dc-dc converter, so as to convert the voltage of the upper power supply to adapt to the signal compensation chip 002, and flexibly control the start and stop of the signal compensation chip 002. When the upper power supply is alternating current, the power supply module 006 can be deployed as a MOS tube switching power supply, so that the voltage of the upper power supply is converted into the voltage matched with the signal compensation chip 002, and the starting and stopping of the signal compensation chip are flexibly controlled.
In addition, the signal compensation chip 002 employed in the two PCIe bus device embodiments described above includes, but is not limited to, a Re-timer chip and a Re-driver chip. The Re-driver chip has relatively simple functions, and the balance and pre-emphasis are only carried out on signals at a physical layer through a high-pass filter of an RX end (a receiving end) and a driver of a TX end (a transmitting end) so as to realize the compensation of loss. Since the Re-driver chip does not relate to protocol related content, devices at both ends of the Re-driver chip are equivalent to pass-through at a protocol layer. The Re-timer chip reconstructs signals through an internal clock, so that the signal transmission energy is increased, and then the signals are continuously transmitted. The Re-timer chip has the data clock recovery inside, and after the data recovery is realized, the signal is sent out according to the serial channel, so that the jitter of the signal can be reduced, the Re-timer chip can realize the effect of reducing the physical loss better than the Re-driver chip, but the complex Re-timer chip can also increase more time delay. Therefore, in the embodiment of the invention, the signal compensation chip can be flexibly selected from the two chips according to the actual scene requirements of a user.
In accordance with an embodiment of the present invention, there is also provided an embodiment of a PCIe signal control method, where the steps shown in the flowchart of the drawing may be performed in a computer system such as a set of computer executable instructions, and where although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in an order other than that shown or described herein.
Fig. 4 is a flowchart of a PCIe signal control method according to an embodiment of the present invention, as shown in fig. 4, the flowchart includes the following steps:
step S401, judging whether an external card is inserted into the PCIe interface through the in-place signal;
step S402, when the bit signal representation is not inserted with an additional card, no voltage is output to the signal compensation chip;
step S403, when the bit signal represents that the add-on card is inserted, outputting a voltage to the signal compensation chip.
Specifically, in the PCIe signal control method provided by the embodiment of the present invention, an in-place signal of a PCIe card machine is connected to a PCIe interface, and is connected to a signal compensation chip. When the PCIe interface is inserted with the external card, the logic power supply can take the in-place signal for detecting the insertion of the external card as an enabling signal, output voltage supplies power for the signal compensation chip, and meanwhile, the in-place signal for detecting the extraction of the external card is taken as a power-off signal, and no output voltage supplies power for the signal compensation chip. The detailed explanation of the principles of the present embodiment may refer to the related descriptions of the above product embodiments, and will not be repeated here.
According to an embodiment of the present invention, when the logic power supply includes a complex programmable logic device and a power module, the PCIe interface is an SFF-8639 interface, and the method is applied to the complex programmable logic device, as shown in fig. 5 and fig. 6, the flow includes the following steps:
in step S501, it is determined whether the PCIe interface is plugged with an add-on card according to the bit signal. Specifically, step S501 is the above-described step S401.
Step S502, when the in-place signal indicates that the add-on card is not inserted, sending a power-off signal to the power module, so that the power module is turned off. Specifically, step S502 includes step S402 described above.
Step S503, when the bit signal indicates that the add-on card is inserted, an enable signal is sent to the power module, so that the power module is started in response to the enable signal to supply power to the signal compensation chip. Specifically, step S503 includes step S403 described above.
In step S504, a first notification signal is sent to the processor, so that the processor runs a hot plug-in program, and a communication connection is established with the PCIe interface through the signal compensation chip.
Step S505, judging whether the PCIe interface pulls out the external card or not through the in-place signal;
step S506, when the bit signal represents that the add-on card is pulled out, a second notification signal is sent to the processor so that the processor runs a heat removal program.
Step S507, sending a power-off signal to the power module to turn off the power module.
Specifically, the PCIe signal control method provided by the embodiment of the present invention is specifically applied to the product embodiment of the SFF-8639 interface, and the hot plug of the device adapted to the NVME protocol during startup needs to configure an application scenario of a corresponding hot plug and hot removal program. According to the embodiment, whether the additional card is inserted into the SFF-8639 interface or not is detected through the second in-place signal by deploying the complex programmable logic device, and when the additional card is not inserted into the SFF-8639 interface, hot plug is not needed at the moment, and only the complex programmable logic device is required to control a logic power supply to stop supplying power to the signal compensation chip, so that the purpose of saving electric energy is achieved. When the SFF-8639 interface is inserted with the add-on card, the complex programmable logic device can control the logic power supply to start to supply power for the signal compensation chip, ensure the time sequence of the power supply, and then control the processor to run the hot plug-in program to establish communication connection with the PCIe interface so as to read the inserted add-on card. Meanwhile, in the running process of the system, whether the additional card is pulled out of the SFF-8639 interface connected is detected through a second in-place signal, when the additional card is pulled out of the SFF-8639 interface, the complex programmable logic device firstly informs the processor of running a heat removal program, the process of pulling out the additional card is protected by the heat removal program, faults caused by pulling out the additional card are avoided, then an electrical signal is sent to a logic power supply, so that the logic power supply is closed to stop supplying power to the signal compensation chip, and the purpose of saving electric energy is achieved. By the mode, the signal compensation chip is prevented from being kept in a standby state for a long time and continuously consuming electricity, and the purpose of saving electric energy is achieved. Meanwhile, system errors caused by power supply time sequence problems are avoided, and the method is suitable for the application scene of hot plug of an SFF-8639 interface. For explanation of the principle of the hardware elements in the embodiment of the method, reference may be made to the related description of the embodiment of the product, which is not repeated herein.
In this embodiment, a PCIe signal control device is further provided, and this device is used to implement the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The embodiment provides a PCIe signal control device, applied to a logic power supply, as shown in fig. 7, including:
the in-place detection module 601 is configured to determine whether the PCIe interface is inserted with an add-on card according to the in-place signal. For details, see the description of step S401 in the above method embodiment, and the details are not repeated here.
The power-off module 602 is configured to not output a voltage to the signal compensation chip when the bit signal indicates that the add-on card is not inserted. For details, refer to the related description of step S402 in the above method embodiment, and no further description is given here.
The power-up module 603 is configured to output a voltage to the signal compensation chip when the bit signal indicates that the add-on card is inserted. For details, see the description of step S403 in the above method embodiment, and the details are not repeated here.
The PCIe signal control means in this embodiment are in the form of functional units, where the units are ASIC circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above functions.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
In some alternative embodiments, when the logic power supply includes a complex programmable logic device and a power module, the PCIe interface is an SFF-8639 interface, and the method is applied to the complex programmable logic device, the power-down module 602 includes:
and the second power-off module is used for sending a power-off signal to the power supply module when the in-place signal represents that the external card is not inserted, so that the power supply module is closed. In some optional embodiments, the details refer to the related description of step S502 in the above method embodiments, and are not described herein.
In some alternative embodiments, when the logic power supply includes a complex programmable logic device and a power module, the PCIe interface is an SFF-8639 interface, and the method is applied to the complex programmable logic device, the power-on module 603 includes:
and the second power-on module is used for sending an enabling signal to the power supply module when the in-place signal represents that the external card is inserted, so that the power supply module responds to the enabling signal to start to supply power for the signal compensation chip. For details, see the description of step S503 in the above method embodiment, and the details are not repeated here.
In some optional implementations, when the logic power supply includes a complex programmable logic device and a power module, the PCIe interface is an SFF-8639 interface, and the method is applied to the complex programmable logic device, a PCIe signal control apparatus provided by the embodiment of the present invention further includes:
and the hot plug module is used for sending a first notification signal to the processor so that the processor runs a hot plug program and establishes communication connection with the SFF-8639 interface through the signal compensation chip. For details, refer to the related description of step S504 in the above method embodiment, and no further description is given here.
The third in-place detecting module 705 determines whether the SFF-8639 interface has pulled out the add-on card according to the second in-place signal. For details, refer to the related description of step S505 in the above method embodiment, and no further description is given here.
And the heat removing module is used for sending a second notification signal to the processor when the second bit signal represents that the external card is pulled out, so that the processor runs a heat removing program. For details, refer to the related description of step S506 in the above method embodiment, and no further description is given here.
And the third power-off module sends a power-off signal to the logic power supply so as to enable the logic power supply to be turned off. For details, see the description of step S507 in the above method embodiment, and the details are not repeated here.
The PCIe signal control means in this embodiment are in the form of functional units, where the units are ASIC circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above functions.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (11)
1. A PCIe bus device, comprising: the system comprises a processor, a signal compensation chip, a logic power supply and a PCIe interface;
the PCIe interface is connected with the signal compensation chip bus, and the signal compensation chip is connected with the processor bus;
the PCIe interface is connected with the logic power supply;
the logic power supply is connected with the signal compensation chip.
2. The PCIe bus device of claim 1, wherein the logic power supply comprises a complex programmable logic device and a power module, the PCIe interface being an SFF-8639 interface;
the complex programmable logic device is respectively connected with the processor, the PCIe interface and the power supply module;
the power module is connected with the signal compensation chip.
3. The PCIe bus device of claim 2, wherein the power module is a dc-dc converter or a MOS transistor switching power supply.
4. The PCIe bus device of claim 1, wherein the signal compensation chip is a Re-timer chip or a Re-driver chip.
5. A PCIe signal control method, applied to a logic power supply, the method comprising:
judging whether an external card is inserted into the PCIe interface through the in-place signal;
when the in-place signal representation is not inserted into the externally added card, no voltage is output to a signal compensation chip;
and outputting voltage to the signal compensation chip when the bit signal representation is inserted into the externally applied card.
6. The method of claim 5, wherein the logic power supply includes a complex programmable logic device and a power module, the PCIe interface is an SFF-8639 interface, the method being applied to the complex programmable logic device, the not outputting a voltage to a signal compensation chip when the bit signal characterization is not inserted into the add-on card comprising:
and when the in-place signal represents that the external card is not inserted, sending a power-off signal to a power module so as to enable the power module to be closed.
7. The method of claim 6, wherein outputting a voltage to the signal compensation chip when the bit signal characterization inserts the add-on card comprises:
and when the bit signal representation is inserted into the external card, transmitting an enabling signal to the power supply module so that the power supply module responds to the enabling signal to start to supply power for the signal compensation chip.
8. The method of claim 7, wherein after sending an enable signal to the power module, the method further comprises:
and sending a first notification signal to a processor so that the processor runs a hot plug-in program, and establishing communication connection with the PCIe interface through the signal compensation chip.
9. The method of claim 8, wherein the method further comprises:
judging whether the PCIe interface pulls out the external card or not through the in-place signal;
when the on-site signal characterizes that the add-on card is pulled out, sending a second notification signal to the processor so that the processor runs a heat removal program;
and sending a power-off signal to the power module so as to enable the power module to be turned off.
10. A PCIe signal control device for use with a logic power supply, the device comprising:
the in-place detection module is used for judging whether the PCIe interface is inserted with an add-on card or not through the in-place signal;
the power-off module is used for not outputting voltage to the signal compensation chip when the in-place signal representation is not inserted into the external card;
and the power-on module is used for outputting voltage to the signal compensation chip when the in-place signal representation is inserted into the externally-added card.
11. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any of claims 5-8.
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| CN202310565432.6A CN116521595A (en) | 2023-05-18 | 2023-05-18 | PCIe bus device, PCIe signal control method, PCIe signal control device and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310565432.6A CN116521595A (en) | 2023-05-18 | 2023-05-18 | PCIe bus device, PCIe signal control method, PCIe signal control device and storage medium |
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