CN113168207A - Interface assembly, chip and electronic equipment - Google Patents

Interface assembly, chip and electronic equipment Download PDF

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Publication number
CN113168207A
CN113168207A CN201980078223.0A CN201980078223A CN113168207A CN 113168207 A CN113168207 A CN 113168207A CN 201980078223 A CN201980078223 A CN 201980078223A CN 113168207 A CN113168207 A CN 113168207A
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usb transceiver
usb
control
control circuit
circuit
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鲁灯
曾涛
郑科
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
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Abstract

Interface assembly (200), chip and electronic device, comprising: the USB host comprises a USB host controller (201), a USB transceiver (202), a control circuit (204) and a first signal switching circuit (205-1), wherein the USB host controller (201) and the control circuit (204) are connected with the USB transceiver (202) through the first signal switching circuit (205-1); and the control circuit (204) is used for controlling the first signal switching circuit (205-1) to be communicated with the connection between the control circuit (204) and the USB transceiver (202) under the condition that the USB transceiver (204) is not connected with an external device, so that the control circuit (204) controls the USB transceiver (202) to enter a low power consumption state. The interface component (200) in the above technical solution further includes a control circuit (204) in addition to the USB host controller (201), the source of the control signal of the USB transceiver (202) can be switched by the first signal switching circuit (205-1), and when the signal source is the control circuit (204), the control circuit (204) can control the USB transceiver (202) to enter a low power consumption state, so that the power consumption of the USB interface can be reduced.

Description

Interface assembly, chip and electronic equipment Technical Field
The present application relates to the field of electronic devices, and more particularly to interface assemblies, chips, and electronic devices.
Background
The existing low power consumption scheme of a Universal Serial Bus (USB) interface is directed to a scenario in which a USB transceiver is connected to an external device. However, in practical use scenarios of products such as Personal Computers (PCs), tablet computers, set-top boxes, and televisions, the USB transceiver is more in a state of not being connected to an external device.
For the scenario where the USB transceiver is not connected to an external device, the USB interface is in an idle state, and for example, a typical chip with a 28 nanometer (nm) technology, the power consumption of one USB interface will be above 10 milliwatts (mW). In this scenario, the USB interface generates a large power consumption.
Disclosure of Invention
The application provides an interface assembly, a chip and an electronic device, which can reduce the power consumption of a USB interface.
In a first aspect, the present application provides an interface assembly comprising: the method comprises the following steps: the USB host comprises a USB host controller, a USB transceiver, a control circuit and a first signal switching circuit, wherein the USB host controller and the control circuit are connected with the USB transceiver through the first signal switching circuit; the control circuit is used for controlling the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver under the condition that the USB transceiver is not connected with external equipment, so that the control circuit controls the USB transceiver to enter a low power consumption state.
The interface assembly in the above technical scheme further comprises a control circuit besides the USB host controller, and the source of the USB transceiver control signal can be switched through the first signal switching circuit. That is, in some cases the USB transceiver may be controlled by the USB host controller, and in other cases the USB transceiver may be controlled by the control circuit. And particularly under the condition that the USB transceiver is not connected with an external device, the control circuit can control the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state, and the power consumption of a USB interface can be reduced.
And the technical scheme does not change the related protocol of the USB, thereby avoiding the introduction of the USB compatibility problem.
In a possible implementation manner, the control circuit is further configured to control the USB transceiver to exit the low power consumption state when the USB transceiver is connected to an external device; the control circuit is further configured to control the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and to connect the connection between the USB host controller and the USB transceiver after the USB transceiver exits from the low power consumption state.
In a possible implementation manner, the interface component further includes a second signal switching circuit, and the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit; the control circuit is further configured to control the second signal switching circuit to communicate the connection between the control circuit and the USB host controller when the USB transceiver is not connected to an external device.
In a possible implementation manner, the interface component further includes a detection circuit, and the detection circuit is connected to the control circuit and the USB transceiver; the detection circuit is used for detecting whether an external device is connected to the USB transceiver or not and transmitting a detection result to the control circuit; the control circuit is specifically configured to control the USB transceiver to enter the low power consumption state when the detection result indicates that the USB transceiver is not connected to an external device.
In one possible implementation, the control circuit includes a control register, a status register, an interrupt circuit, and a Central Processing Unit (CPU); the state register is used for storing the detection result of the detection circuit and reporting the detection result to the CPU through the interrupt circuit; the CPU is used for executing at least one of the following operations when the detection result indicates that the USB transceiver is not connected with an external device: controlling the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver by configuring a first control signal in the control register; controlling the USB transceiver to enter the low power consumption state by configuring a second control signal in the control register; and controlling the second signal switching circuit to communicate the connection between the control circuit and the USB host controller by configuring a third control signal in the control register.
In a possible implementation manner, the CPU is further configured to, in a case that the detection result indicates that the USB transceiver is connected to an external device, perform at least one of the following operations: controlling the USB transceiver to exit the low power consumption state by configuring the second control signal in the control register; after the USB transceiver exits the low power consumption state, the first signal switching circuit is controlled by the first control signal configured to the control register to disconnect the connection between the control circuit and the USB transceiver and connect the connection between the USB host controller and the USB transceiver.
The technical scheme adopts a software implementation mode to control the signal switching unit, and the cost is lower.
In one possible implementation, the control circuit includes a control register, a status register, and a control logic circuit; the state register is used for storing the detection result of the detection circuit; the control logic circuit is configured to, if the detection result indicates that the USB transceiver is not connected to an external device, perform at least one of the following operations: controlling the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver; controlling the USB transceiver to enter the low power consumption state; and controlling the second signal switching circuit to be communicated with the connection between the control circuit and the USB host controller.
According to the technical scheme, the control of the signal switching circuit is realized through the logic circuit, and compared with a mode of realizing by software, the complexity of the software can be reduced.
In a possible implementation manner, the control logic circuit is further configured to, in a case that the detection result indicates that an external device is connected to the USB transceiver, perform at least one of the following operations: controlling the USB transceiver to exit the low power consumption state; and after the USB transceiver exits the low power consumption state, controlling the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and connect the connection between the USB host controller and the USB transceiver.
According to the technical scheme, the control of the signal switching circuit is realized through the logic circuit, and compared with a mode of realizing by software, the complexity of the software can be reduced.
In a possible implementation manner, the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal, the first input terminal and the first control terminal are respectively connected to the control circuit, the second input terminal is connected to the USB host controller, and the first output terminal is connected to the USB transceiver; the second signal switching circuit comprises a third input end, a fourth input end, a second output end and a second control end, the third input end and the second control end are respectively connected with the control circuit, the fourth input end is connected with the USB transceiver, and the second output end is connected with the USB host controller; the control circuit is specifically configured to, when the USB transceiver is not connected to an external device, control the first signal switching circuit to communicate with the connection between the control circuit and the USB transceiver through the first control end, and control the second signal switching circuit to communicate with the connection between the control circuit and the USB host controller through the second control end; the control circuit is specifically configured to, when an external device is connected to the USB transceiver, control the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver through the first control end, and communicate the connection between the USB host controller and the USB transceiver through the first control end and the second control end.
In a possible implementation manner, the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver and is configured to detect whether an external device is connected to the USB transceiver.
In one possible implementation, when the USB transceiver is in the low power consumption state, a phase-locked loop PLL circuit of the USB transceiver is in an off state.
Since the PLL circuit is a high power consuming device in the USB transceiver, the PLL circuit is turned off. The system clock signal with lower power consumption (or without generating extra power consumption) can be used instead to ensure the normal operation of the USB host controller. This can reduce the power consumption of the USB interface.
In a second aspect, the present application provides a control method, which is applied to an interface component, where the interface component includes a USB host controller, a USB transceiver, a control circuit and a first signal switching circuit, where the USB host controller and the control circuit are connected to the USB transceiver through the first signal switching circuit, and the method includes: under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
In one possible implementation, the method further includes: under the condition that the USB transceiver is connected with an external device, the control circuit controls the USB transceiver to exit the low power consumption state; after the USB transceiver exits the low power consumption state, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and to connect the connection between the USB host controller and the USB transceiver.
In one possible implementation manner, the interface component further includes a second signal switching circuit, and the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit, and the method further includes: under the condition that the USB transceiver is not connected with an external device, the control circuit controls the second signal switching circuit to communicate the connection between the control circuit and the USB host controller.
In one possible implementation, the interface component further includes a detection circuit, and the detection circuit is connected to the control circuit and the USB transceiver, and the method further includes: the control circuit receives a detection result transmitted by the detection circuit, and the detection result is used for indicating whether an external device is connected to the USB transceiver or not; under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state, and the method comprises the following steps: and under the condition that the detection result indicates that the USB transceiver is not connected with external equipment, the control circuit controls the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver and controls the USB transceiver to enter the low power consumption state.
In a possible implementation manner, the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal, the first input terminal and the first control terminal are respectively connected to the control circuit, the second input terminal is connected to the USB host controller, and the first output terminal is connected to the USB transceiver; the second signal switching circuit comprises a third input end, a fourth input end, a second output end and a second control end, the third input end and the second control end are respectively connected with the control circuit, the fourth input end is connected with the USB transceiver, and the second output end is connected with the USB host controller; under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, and the control circuit comprises: the control circuit controls the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver through the first control end under the condition that the USB transceiver is not connected with external equipment, and controls the second signal switching circuit to be communicated with the connection between the control circuit and the USB host controller through the second control end; under the condition that the USB transceiver is connected with external equipment, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver through the first control end and controls the connection between the USB host controller and the USB transceiver through the second control end.
In a possible implementation manner, the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver and is configured to detect whether an external device is connected to the USB transceiver.
In one possible implementation, when the USB transceiver is in the low power consumption state, a phase-locked loop PLL circuit of the USB transceiver is in an off state.
In a third aspect, the present application provides a chip, where the chip includes a processor and an interface component as described in the first aspect or any one of the possible implementation manners of the first aspect.
In a fourth aspect, the present application provides an electronic device comprising a processor, a memory, and an interface component as described in the first aspect or any one of the possible implementations of the first aspect.
Drawings
Fig. 1 is a schematic structural diagram of a USB system to which the technical solution of the embodiment of the present application can be applied.
Fig. 2 is a schematic structural diagram of an interface module according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a signal flow direction of an interface module according to an embodiment of the present application.
Fig. 4 is a schematic diagram of another signal flow direction of the interface module according to the embodiment of the present application.
Fig. 5 is a schematic configuration diagram of a control circuit of an embodiment of the present application.
Fig. 6 is a schematic configuration diagram of another control circuit of the embodiment of the present application.
Fig. 7 is a schematic structural diagram of the MUX.
Fig. 8 is a schematic block diagram of an interface module according to another embodiment of the present application.
Fig. 9 is a schematic block diagram of an interface module according to another embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
The technical scheme of the embodiment of the application can be applied to various devices or products needing to reduce interface power consumption, and only the devices or products need to carry out data transmission with external devices through USB interfaces. Such as a PC, tablet, set-top box, television, etc. It is understood that the technical solution of the embodiment of the present application can also be applied to other types of interface systems, such as a High Definition Multimedia Interface (HDMI), an external serial advanced technology attachment (E-SATA) interface, a Video Graphics Array (VGA) interface, and the like. The application takes a USB interface as an example to describe the technical solution of the application.
The type of the USB interface is not particularly limited in the embodiments of the present application, and may be, for example, Micro-USB, Mini-USB, Sub-USB, USB-type C, or the like.
Fig. 1 is a schematic structural diagram of a USB system to which the technical solution of the embodiment of the present application can be applied. As shown in fig. 1, the USB host controller 101 is connected to a memory 114 (e.g., a double data rate synchronous dynamic random access memory (DDR SDRAM)), a Central Processing Unit (CPU) 1041 and the USB transceiver 102 through a system bus 115, and the USB host controller 101 implements reading or writing of data between the memory 104 and an external device 106 through the USB transceiver 102 after receiving a task issued by the CPU 1041, where the external device 106 is connected to the USB transceiver 102.
The existing low-power-consumption schemes of USB interfaces all aim at a scenario where a USB transceiver is connected to a USB device, but in an actual usage scenario of products such as a Personal Computer (PC), a tablet PC, a set-top box, and a television, the USB transceiver is more in a state where the USB device is not connected, and for a case where the USB transceiver is not connected to the USB device, the USB device is usually handled in an idle state rather than entering a suspend state according to a state where a USB host controller and the USB transceiver are in an idle state. Taking a typical 28 nanometer (nm) technology chip as an example, the power consumption of a USB interface will be above 10 milliwatts (mW). In this scenario, the USB interface generates a large power consumption. Therefore, the embodiment of the present application provides a low power consumption scheme for a scenario where a USB transceiver is not connected to a USB device based on the interface component 200.
Fig. 2 is a schematic structural diagram of an interface module according to an embodiment of the present application. As shown in fig. 2, the interface assembly 200 includes a USB host controller 201, a USB transceiver 202, a control circuit 204, and a first signal switching circuit 205-1. The USB host controller 201 and the USB transceiver 202 may correspond to the USB host controller 101 and the USB transceiver 102 in fig. 1, respectively.
The USB host controller 201 and the control circuit 204 are connected to the USB transceiver 202 via the first signal switching circuit 205-1. That is, the control circuit 204 and the first signal switching circuit 205-1 are added between the USB host controller 201 and the USB transceiver 202.
The embodiment of the present application does not specifically limit the type of the USB host controller 201, and examples include an Enhanced Host Controller Interface (EHCI), a Universal Host Controller Interface (UHCI) host controller, an Open Host Controller Interface (OHCI) host controller, and the like.
The present embodiment does not specifically limit the type of the USB transceiver 202, such as a USB2.0transceiver macro interface (UTMI) transceiver.
The control circuit 204 is used for controlling the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202 in case that the USB transceiver 202 is not connected with an external device, so that the control circuit 204 controls the USB transceiver 202 to enter a low power consumption state. Among them, the connection between the communication control circuit 204 and the USB transceiver 202 may be signal transmission/reception communicated therebetween.
Specifically, in the case where the first signal switching circuit 205-1 switches on the connection between the control circuit 204 and the USB transceiver 202, the control signal sent by the control circuit 204 can reach the USB transceiver 202, thereby changing the state of the USB transceiver 202. Optionally, when the USB transceiver 202 is in a low power consumption state, at least a portion of the circuitry is turned off to save power consumption, for example, the low power consumption state is a suspend state. Alternatively, when the USB transceiver 202 is in a low power consumption state, the phase-locked loop PLL circuit of the USB transceiver 202 is turned off. Under the condition of not changing the existing USB protocol, in the technical solution of the embodiment of the present application, when the USB transceiver 202 is not connected to the external device, the USB host controller 201 is in the low power consumption state, and the USB host controller 201 is in the non-low power consumption state, so that in order to make the USB host controller 201 operate normally, when the USB transceiver 202 is in the low power consumption state, the USB host controller 201 can be connected to the system clock signal.
That is, in the case where the USB transceiver 202 is connected to an external device, the USB transceiver 202 is controlled by the USB host controller 201, and is in a state of high power consumption to wait for data transmission; in the case where the USB transceiver 202 is not connected to an external device, the USB transceiver 202 is controlled by the control circuit 204 to enter a state with lower power consumption, for example, a low power consumption state, so as to reduce the power consumption of the USB interface.
The first signal switching circuit 205-1 of the embodiment of the present application can switch according to whether the USB transceiver 202 is connected to an external device. As an example, the first signal switching circuit 205-1 may be controlled by the control circuit 204, and specifically, the control circuit 204 controls the first signal switching circuit 205-1 to connect the connection between the USB host controller 201 and the USB transceiver 202 in a case where the USB transceiver 202 is connected to an external device, and controls the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202 in a case where the USB transceiver 202 is not connected to an external device.
It is understood that the interface module implemented in the present application may also have more control circuits, for example, two control circuits or more than two control circuits, and accordingly, the first signal switching circuit 205-1 of the embodiment of the present application may also perform switching of more paths of signals, for example, 3 paths or more than 3 paths, etc. For example, when the interface module has two control circuits 204-1 and 204-2, the first signal switching circuit 205-1 can perform switching between 3 signals, for example, when the first signal switching circuit 205-1 connects the USB host controller 201 to the USB transceiver, the USB transceiver is in an idle state; when the first signal switching circuit 205-1 connects the connection between the control circuit 204-1 and the USB transceiver 202, the USB transceiver is in a low power consumption state; when the first signal switching circuit 205-1 connects the connection between the control circuit 204-2 and the USB transceiver 202, the USB transceiver is in other states than the idle state and the low power consumption state. For convenience of description, the interface module has a 1 control circuit 204, and the first signal switching circuit 205-1 can switch between two signals.
Optionally, the control circuit 204 is further configured to control the USB transceiver 202 to exit the low power consumption state if the USB transceiver 202 is connected to an external device. For example, the control circuitry may control the USB transceiver 202 to exit the low power consumption state when an external device is plugged into the USB transceiver 202.
Optionally, the control circuit 204 is further configured to control the first signal switching circuit 205-1 to disconnect the connection between the control circuit 204 and the USB transceiver 202 and to connect the connection between the USB host controller 201 and the USB transceiver 202 after the USB transceiver 202 exits the low power consumption state.
That is to say, under the condition of not changing the existing USB protocol, in the technical solution of the embodiment of the present application, when the USB transceiver 202 is not connected to the external device, the USB transceiver 202 is switched to the low power consumption state, and the USB host controller 201 is in the idle state, not the low power consumption state, so when the USB transceiver 202 is connected to the external device, in order to avoid various problems caused by the inconsistent states of the USB transceiver 202 and the USB host controller 201, it is necessary to restore the USB transceiver 202 to the normal state, for example, to turn on a circuit or the like that is turned off in the low power consumption state, so that the USB transceiver 202 is restored to the normal state, and then turn on the signal connection between the USB host controller and the USB transceiver.
It is understood that, in the case where the first signal switching circuit 205-1 connects the connection between the control circuit 204 and the USB transceiver 202, the signal sent by the USB host controller 201 to the USB transceiver 202 is disconnected; in the case where the first signal switching circuit 205-1 connects the connection between the USB host controller 201 and the USB transceiver 202, the signal sent by the control circuit 204 to the USB transceiver 202 is disconnected. This avoids interference between the signals.
Optionally, the interface assembly 200 further includes a second signal switching circuit 205-2. The USB transceiver 202 and the control circuit 204 are connected to the USB host controller 201 through the second signal switching circuit 205-2. That is, the signal source of the input signal of the USB host controller 201 can be changed by the second signal switching circuit 205-2. The control circuit 204 is also used to control the second signal switching circuit 205-2 to connect the connection between the control circuit 204 and the USB host controller 201 in the case where the USB transceiver 202 is not connected to an external device.
It should be noted that the control signals of the first signal switching circuit 205-1 and the second signal switching circuit 205-2 may be the same control signal, or different control signals may be used.
That is, in the case where the USB transceiver is connected to the USB device, the USB device is in a state with higher power consumption to wait for data transmission, and in the case where the USB transceiver is not connected to the USB device, the USB controller may be controlled by the control circuit to enter a state with lower power consumption, for example, a state with lower power consumption, so as to reduce the power consumption of the USB interface.
Optionally, the interface module 200 according to the embodiment of the present application further includes a detection circuit 203, where the detection circuit 203 is connected to the USB transceiver 202 and the control circuit 204, and is configured to detect whether the USB transceiver 202 is connected to an external device, and send a detection result to the control circuit 204, so that the control circuit 204 controls the first signal switching circuit 205-1, the second signal switching circuit 205-2, and the USB transceiver 202 according to the detection result.
The detection result of the detection circuit can be represented by the state value of the bit or the high-low level of the output signal of the detection circuit. As an example, two bits are used to indicate whether an external device is connected and one bit indicates whether the connection status has changed. For example, when the state value of two bits is 00, it indicates that the USB transceiver 202 is always in a state where an external device is not connected; when the state value of the two bits is 01, it indicates that no external device is connected and the state changes, that is, the external device on the USB transceiver 202 is pulled out; when the state value of the two bits is 10, it indicates that an external device is connected and the state is not changed, that is, the USB transceiver 202 is always connected to the external device; when the state value of the two bits is 11, it indicates that an external device is connected and the state is changed, that is, the external device is inserted into the USB transceiver 202.
The signal flow of the interface assembly 200 is described below in conjunction with fig. 3 and 4.
For the case where the USB transceiver 202 is not connected to an external device, as shown in fig. 3, the detection circuit 203 receives a first signal 310 from the USB transceiver 202 and generates a second signal 307 in the case where the first signal 310 indicates that the USB transceiver 202 is not connected to an external device, the second signal 307 being used to indicate to the control circuit 204 that the USB transceiver 202 is not connected to an external device; after receiving the second signal 307, the control circuit 204 controls the first signal switching circuit 205-1 to disconnect the connection between the USB host controller 201 and the USB transceiver 202 and connect the connection between the control circuit 204 and the USB transceiver 202, so that the second control signal 311 sent by the control circuit 204 reaches the USB transceiver 202; and controls the second signal switching circuit 205-2 to disconnect the connection between the USB host controller 201 and the USB transceiver 202, and connect the connection between the control circuit 204 and the USB host controller 201; the USB transceiver 202 enters the low power consumption state after receiving the second control signal 311.
For the case where the USB transceiver 202 is connected to an external device, as shown in fig. 4, the detection circuit 203 generates a third signal 412 in the case where the first signal 310 indicates that the USB transceiver 202 is connected to an external device, the third signal 412 being used to indicate to the control circuit 204 that the USB transceiver 202 is connected to an external device; the control circuit 204, upon receiving the third signal 412, sends a fourth control signal 413 to the USB transceiver 202 in the event of signal communication between the control circuit 204 and the USB transceiver 202; the USB transceiver 202 exits the low power consumption state after receiving the fourth control signal 413; the control circuit 204 controls the first signal switching circuit 205-1 to disconnect the connection between the control circuit 204 and the USB transceiver and to connect the connection between the USB host controller 201 and the USB transceiver 202 after the USB transceiver 202 exits the low power consumption state.
Further, at the time of system initialization, the USB host controller 201 and the USB transceiver 202 use signals from the control circuit 204 by default. That is, if no external device is connected all the way through the USB transceiver 202, the USB transceiver 202 may be in a low power consumption state all the time. In this way, power consumption can be reduced for a USB interface that has never been used.
It should be understood that the signals in the control circuit 204 for controlling the first signal switching circuit 205-1 and the second signal switching circuit 205-2 are always connected when the signal sources of the USB transceiver 202 and the USB host controller 201 are switched.
The embodiment of the present application does not specifically limit the form of the control circuit 204, as long as it can implement the functions described above.
As an example, as shown in FIG. 5, the control circuit 204 includes a control register 204-4, a status register 204-1, an interrupt circuit 204-2, and a CPU 204-3. The status register 204-1 is used for storing the detection result of the detection circuit 203 and reporting the detection result to the CPU 204-3 through the interrupt circuit 204-2. The CPU 204-3 is configured to, in a case where the detection result indicates that the USB transceiver 202 is not connected to the external device, perform at least one of the following operations:
controlling the first signal switching circuit 205-1 to connect the control circuit 204 and the USB transceiver 202 by configuring the first control signal in the control register 204-4; controlling the USB transceiver 202 to enter a low power consumption state by configuring the second control signal 311 in the control register 204-4; the second signal switching circuit 205-2 is controlled to communicate the connection between the control circuit 204 and the USB host controller 201 by configuring the third control signal in the control register 204-4.
The CPU 204-3 is further configured to, in a case where the detection result indicates that the USB transceiver 202 is connected to an external device, perform at least one of the following operations:
controlling the USB transceiver 202 to exit the low power consumption state by configuring the second control signal 311 in the control register 204-4; after the USB transceiver 202 exits the low power consumption state, the first signal switching circuit 205-1 is controlled by the first control signal of the configuration control register 204-4 to disconnect the control circuit 204 from the USB transceiver 202 and connect the USB host controller 201 to the USB transceiver 202.
Specifically, for the case that the USB transceiver 202 is not connected to an external device, the status register 204-1 is configured to report a first interrupt event to the CPU 204-3 through the interrupt circuit 204-2 after receiving the second signal 307 from the detection circuit 203, where the first interrupt event is that the USB transceiver 202 is not connected to an external device (for example, when the external device is unplugged), the CPU 204-3 is configured to configure the control register 204-4 according to the first interrupt event, so that the control register 204-4 controls the first signal switching circuit 205-1 to disconnect the connection between the USB host controller 201 and the USB transceiver 202, and connects the connection between the control circuit 204 and the USB transceiver 202, so that the second control signal 311 sent by the control circuit 204 reaches the USB transceiver 202; and controls the second signal switching circuit 205-2 to disconnect the connection between the USB host controller 201 and the USB transceiver 202, and connect the connection between the control circuit 204 and the USB host controller 201; the USB transceiver 202 enters the low power consumption state after receiving the second control signal 311.
For the case where an external device is plugged into the USB transceiver 202, the status register 204-1 is configured to report a second interrupt event to the CPU 204-3 through the interrupt circuit 204-2 after receiving the third signal 412 from the detection circuit 203, where the first interrupt event is that the USB transceiver 202 is connected to the external device (e.g., when the external device is plugged in), and the CPU 204-3 is configured to configure the control register 204-4 according to the second interrupt event, so as to send a fourth control signal 413 to the USB transceiver 202 in the case where the signals between the control circuit 204 and the USB transceiver 202 are communicated; the USB transceiver 202 exits the low power consumption state after receiving the fourth control signal 413; the control circuit 204 controls the first signal switching circuit 205-1 to disconnect the connection between the control circuit 204 and the USB transceiver and to connect the connection between the USB host controller 201 and the USB transceiver 202 after the USB transceiver 202 exits the low power consumption state.
As another example, as shown in FIG. 6, control circuitry 204 includes control registers 204-6, status registers 204-5, and control logic 204-7. The status register 204-5 is used for storing the detection result of the detection circuit 203; the control logic 204-7 is configured to, in case the detection result indicates that the USB transceiver 202 is not connected to the external device, perform at least one of the following operations:
controlling the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202; controlling the USB transceiver 202 to enter a low power consumption state; the second signal switching circuit 205-2 is controlled to communicate the connection between the control circuit 204 and the USB host controller 201.
The control logic 204-7 is further configured to, in the event that the detection result indicates that an external device is connected to the USB transceiver 202, perform at least one of the following operations:
controlling the USB transceiver 202 to exit the low power consumption state; after the USB transceiver 202 exits the low power consumption state, the first signal switching circuit 205-1 is controlled to disconnect the connection between the control circuit 204 and the USB transceiver 202 and to connect the connection between the USB host controller 201 and the USB transceiver 202.
Specifically, for the case where the USB transceiver 202 is not connected to an external device, the status register 204-5 is configured to generate a fourth signal after receiving the second signal 307 from the detection circuit 203, and the control logic circuit 204-7 is configured to control the first signal switching circuit 205-1 to communicate with the connection between the control logic circuit 204-7 and the USB transceiver 202 and to control the connection between the register 204-6 and the USB transceiver 202 and to control the second signal switching circuit 205-2 to communicate with the connection between the control register 204-6 and the USB host controller 201 after receiving the fourth signal, so as to control the USB transceiver 202 to enter a low power consumption state.
For the case of an external device being plugged into the USB transceiver 202, the status register 204-5 is configured to generate a fifth signal after receiving the third signal 412 from the detection circuit, the control logic 204-7 is configured to control the USB transceiver 202 to exit the low power consumption state after receiving the fifth signal, control the first signal switching circuit 205-1 to connect the USB host controller 201 to the USB transceiver 202 and control the second signal switching circuit 205-2 to connect the USB host controller 201 to the USB host controller 201 after the USB transceiver 202 exits the low power consumption state.
It is understood that the control circuit 204 may also be implemented completely using software programming, or completely by hardware, or by a combination of hardware and software, which is not specifically limited in this embodiment of the present application.
The form of the first signal switching circuit 205-1 is not particularly limited in the present application. As an example, the first signal switching circuit 205-1 may be implemented by one or more Multiplexers (MUXs). Optionally, the first signal switching circuit 205-1 includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal, the first input terminal and the first control terminal are respectively connected to the control circuit 204, the second input terminal is connected to the USB transceiver 202, and the first output terminal is connected to the USB host controller 201. The control circuit 204 controls the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202 through the first control terminal when the USB transceiver is not connected to the external device; when an external device is connected to the USB transceiver 202, the first control terminal controls the first signal switching circuit 205-1 to disconnect the connection between the control circuit 204 and the USB transceiver 202, and connect the signal from the USB host controller 201 to the USB transceiver 202.
Also, the second signal switching circuit 205-2 may be implemented by one or more MUXs. Optionally, the second signal switching circuit 205-2 includes a third input terminal, a fourth input terminal, a second output terminal, and a second control terminal, where the third input terminal and the second control terminal are respectively connected to the control circuit 204, the fourth input terminal is connected to the USB host controller 201, and the second output terminal is connected to the USB transceiver 202. The control circuit 204 may control the second signal switching circuit 205-2 to connect the connection between the control circuit 204 and the USB host controller 201 by controlling the second control end when the USB transceiver is not connected to the external device; when an external device is connected to the USB transceiver 202, the second control terminal controls the second signal switching circuit 205-2 to disconnect the connection between the control circuit 204 and the USB host controller 201, and connects the signal from the USB transceiver 202 to the USB host controller 201.
Fig. 7 is a schematic structural diagram of the MUX. As shown in fig. 7, the MUX has two input terminals a and B, an output terminal D, and a control terminal C. The input terminals a and B may correspond to the above first input terminal and second input terminal, or the third input terminal and fourth input terminal, respectively, the output terminal D may correspond to the above first output terminal or second output terminal, and the control terminal C may correspond to the above first control terminal or second control terminal. The control circuit 204 can realize the signal switching by controlling the terminal C to realize the output terminal D as the input terminal a or the output terminal D as the input terminal B.
It should be understood that the implementation manner of the MUX in the embodiment of the present application is not particularly limited, and for example, the implementation manner may be implemented by using software programming, or may be implemented by hardware, or may be implemented by a combination of software and hardware.
The form of the detection circuit 203 is not particularly limited in the embodiment of the present application, as long as it can detect whether the USB transceiver 202 is connected to an external device. For example, the detection circuit 203 may be a filter. The implementation manner of the detection circuit is not particularly limited in the present application, and for example, the detection circuit may be implemented by software programming, or may be implemented by hardware, or may be implemented by a combination of software and hardware.
The technical solutions of the embodiments of the present application are described in detail below with reference to specific examples.
Fig. 8 is a schematic block diagram of an interface module according to another embodiment of the present application. The USB host controller 801 in fig. 8 may correspond to the above host controller 201, the USB2.0transceiver macro cell interface physical layer (UTMI PHY)802 may correspond to the above USB transceiver 202, the control circuit 804 (including the interrupt circuit 8042, CSR 8041, and CPU 8043) may correspond to the above control circuit 204, the 10 MUXs may correspond to the above signal switching circuit 205, and the filter 803 may correspond to the above detection circuit 203.
Taking the EHCI host controller and the UTMI PHY as an example, the interface standard between the EHCI host controller (i.e., logical layer) and the UTMI PHY (i.e., physical layer) is UTMI, and the signals between the EHCI host controller and the UTMI PHY are described as follows:
utmi _ linester: corresponding to 1 and 11, the signal for feeding back the USB bus connection condition is according to the UTMI interface protocol, when UTMI PHY 802 enters a suspend state, a Phase Locked Loop (PLL) clock source inside UTMI PHY 802 is turned off, but the UTMI _ linetate signal may be obtained by a direct reaction of a combinational logic circuit, that is, after UTMI PHY 802 enters a low power consumption state, the UTMI _ linetate signal can still transmit the connection condition of the external device.
utmi _ hostdinect: corresponding to 2 and 12, for feeding back whether UTMI PHY 802 is a disconnected signal.
utmi _ suspend: signals for controlling whether UTMI PHY 802 is standby (i.e., suspended state), corresponding to 3 and 13, active low;
utmi _ xcvselect [1:0 ]: signals for controlling whether UTMI PHY 802 selects a high speed lane, corresponding to 4 and 14;
utmi _ termselect: signals for controlling whether UTMI PHY 802 connects a high speed resistor, corresponding to 5 and 15;
utmi _ opmode [1:0 ]: signals for controlling whether UTMI PHY 802 operates in normal encoding mode, corresponding to 6 and 16;
utmi _ rx: corresponding to 7 and 17, for UTMI PHY 802 to send data received from external devices to USB host controller 801;
utmi _ tx: corresponding to 8 and 18, for UTMI PHY 802 to transmit data received from USB host controller 801 to external devices;
clk _ utmi: corresponding to 9 and 19, the operational clock signal of UTMI PHY 802 is connected from UTMI PHY 802 to USB host controller 801, 60MHz via clock gate 816, and is clocked off in the suspend state;
clk _ free: corresponding to 10 and 20, the operational clock signals of UTMI PHY 802 are coupled from UTMI PHY 802 to USB host controller 801, 60MHz via clock gate 817 without stalling in the suspend state.
As shown in fig. 8, the embodiment of the present application makes some incremental circuit design between the EHCI host controller and the UTMI PHY to implement the above-described scheme. Specifically, muxes 805-1, 805-2 and 805-7 are provided between UTMI _ linester, UTMI _ hostdinect and UTMI _ rx, respectively, muxes 805-3, 805-4, 805-5 and 805-6 are provided between UTMI _ suspend, UTMI _ rcvselect [1:0], UTMI _ termselect and UTMI _ opmode [1:0] and UTMI _ tx, respectively, and muxes 805-9 and 805-10 are provided between clk _ UTMI and clk _ free, respectively, wherein output terminals of muxes 805-1, 805-2 and 805-7 are connected to host USB controller 801, a control terminal is connected to control register 804-4, and two input terminals are connected to control registers 804-4 and UTMI PHY 802, 805-3, 805-4, 805-5 and UTMI _ 6, respectively, output terminals of control registers 802, 804-4, and two input terminals connected to control register 804-4 and USB host controller 801, respectively, the output terminals of MUXs 805-9 and 805-10 connected to USB host controller 801, the control terminal connected to control register 804-4, and two input terminals connected to system clock signal 818 and UTMI PHY 802, respectively; the UTMI _ linetate signal from UTMI PHY 802 is used as an input to filter 803 in addition to MUX 805-1 to allow status register 804-1 to know whether UTMI PHY 802 is connected to an external device when UTMI PHY 802 is controlled by control circuit 804, where filter 803 is a connection status detection filter to prevent connection status misdetection; the interrupt circuit 804-2 may be a level-triggered interrupt signal line that may signal a high-level-triggered interrupt.
Note that the control (i.e., select) connection of each MUX in fig. 8 is not shown, and in fact the control of each MUX is connected to control register 804-4.
The interface component 800 is initially set to default values, and is configured as shown in fig. 8, for example, UTMI _ termsect input is 1, clk _ free/clk _ UTMI input is system clock signal (clk _ from _ crg)818, that is, the connection state between the USB host controller 801 and the UTMI PHY 802 is initially controlled by the control circuit 804. When no external device is plugged into UTMI PHY 802, control circuitry 804 (or software) controls the disconnection between USB host controller 801 and UTMI PHY 802 via the MUX. When an external device is plugged into the UTMI PHY 802, the control circuit 804 controls the UTMI PHY 802 to communicate with the USB host controller 801, for example, the UTMI _ terselect of the USB host controller 801 is connected to the UTMI _ terselect of the UTMI PHY 802, the clk _ free/clk _ UTMI of the USB host controller 801 is connected to the clk _ free/clk _ UTMI of the UTMI PHY 802, and the like, and the interface component 800 resumes the normal mode.
Interface component 800 detects whether UTMI PHY 802 is connected to an external device through filter 803. Specifically, filter 803 is configured to detect whether UTMI PHY 802 is connected to an external device using the UTMI _ linelate signal. More specifically, in the case where the current state of UTMI PHY 802 is no external device connected, if filter 803 detects that UTMI _ linelate [1:0] is equal to 2' b00 and the duration is greater than x milliseconds, this indicates that the external device pulls out UTMI PHY 802; in the case where the current state of UTMI PHY 802 is to connect an external device, if filter 803 detects that UTMI _ linelate [1:0] is not equal to 2' b00 and the duration is greater than y milliseconds (ms), this indicates that an external device is inserted into UTMI PHY 802.
It should be appreciated that the choice of x ensures that UTMI _ linelate lasts at least 3ms, as specified by the USB protocol, to ensure that the external device is stably connected in the presence of an external device plugged into UTMI PHY 802, so x is at least greater than 3 ms. It is further considered that if x is chosen too large, the detection time will be very long. Therefore, preferably, the default value of x may be 10ms, and x may be configured by a register. Similarly, the choice of y should ensure that the USB bus does not have UTMI _ linetate not equal to 2' b00 for durations greater than y milliseconds without an external device inserted into UTMI PHY 802. According to the USB2.0 protocol, y is at least 0.25 ms. The value of y is too small to be easily disturbed by external burrs, and the value of y becomes large to lengthen the detection time. Therefore, preferably, the default value of y may be 10ms, and y may be configured by a register. Therefore, the scheme of the embodiment of the application can ensure the reliability of plug detection and reduce false detection.
The main workflow of the interface component 800 is described below.
1. Initialization
At system initialization, the connection state between USB host controller 801 and UTMI PHY 802 is a default value and is in a disconnected state. For example, the control circuit 804 controls clk _ free/clk _ UTMI to clk _ from _ crg, UTMI _ suspend to 0, etc., and the UTMI PHY 802 enters a standby state (or a low power consumption state). If no external device has been inserted into UTMI PHY 802, UTMI PHY 802 will always be in a low power state.
2. Device insertion
When an external device is inserted into UTMI PHY 802, filter 803 detects the insertion of the external device, status register 804-1 stores the connection status, and reports an interrupt event of the external device insertion to CPU 804-3 through interrupt circuit 804-2, at this time, software receives the interrupt event, sets UTMI _ suspend to 1 through control register 804-4, lets UTMI PHY 802 exit the standby state, and sets the signal connection between USB host controller 801 and UTMI PHY 802 after UTMI PHY 802 exits the standby state. When the signals between the USB host controller 801 and the UTMI PHY 802 are communicated, clk _ free/clk _ UTMI between the USB host controller 801 and the UTMI PHY 802 is controlled first, and then the other signals are communicated, after the communication, the USB host controller 801 and the UTMI PHY 802 enter a normal connection state, and the subsequent normal work flow is the same as that in the prior art.
3. Device extraction
When an external device pulls out UTMI PHY 802, filter 803 detects that the external device is pulled out, status register 804-1 stores the connection status, and reports an interrupt event of the external device pulling out to CPU 804-3 through interrupt circuit 804-2, at this time, software receives the interrupt event, first controls signals (e.g., clk _ free, clk _ UTMI, etc.) between USB host controller 801 and UTMI PHY 802 to be disconnected through control register 804-4, and then sets UTMI _ suspend to 0, so that UTMI PHY 802 enters a standby mode, i.e., returns to a low power consumption state.
Fig. 9 is a schematic block diagram of an interface module according to another embodiment of the present application. FIG. 9 control circuit 904 includes control registers 904-6, status registers 904-5, and control logic 904-7, where control logic 904-7 includes a state machine. As shown in FIG. 9, the control terminal of each MUX is connected to control logic 904-7.
Interface assembly 800 differs from interface assembly 900 in that interface assembly 800 has an interrupt design that requires software to cooperate with logic to implement the process described above, e.g., CPU 804-3 controls UTMI PHY 802 to enter or exit a low power state based on specific events after receiving an interrupt event, while in interface assembly 900, these operations are performed by control logic 904-7. The interface component 900 adds slightly more logic complexity in exchange for the benefit of not requiring software involvement, avoiding increased software maintenance overhead.
Alternatively, the control logic 904-7 may employ existing basic functional blocks.
The structure and function of other parts of the interface module 900 (e.g., USB host controller 901, UTMI PHY 902, filter 903, etc.), and the operation flow of the interface module 900 can be referred to the related description of fig. 8, and are not described herein again.
The technical scheme of the embodiment of the application makes up the shortage of consideration of the low power consumption scene of the USB2.0 protocol. Configuring the UTMI PHY in a suspend state with the interface component unconnected to external devices may significantly reduce the overall power consumption of the USB interface component. Taking a typical 28 nanometer (nm) processed chip as an example, the area of the UTMI PHY is about 10 times that of the USB host controller, and reducing the power consumption of the PHY can significantly reduce the overall power consumption of the USB. For the scene that the USB interface component is not connected with the external equipment, the measured data of the 28nm technology is as follows: if the UTMI PHY does not enter the low power state, the power consumption of the USB interface component is about 15 milliwatts (mW); if the UTMI PHY enters a low power consumption state, the power consumption of the USB interface component is about 0.5mW, and the power consumption is saved by more than 96%.
The embodiment of the application also provides a control method. The method is applied to an interface assembly, the interface assembly comprises a Universal Serial Bus (USB) host controller, a USB transceiver, a control circuit and a first signal switching circuit, wherein the USB host controller and the control circuit are connected with the USB transceiver through the first signal switching circuit, and the method comprises the following steps: under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
Optionally, the method further comprises: under the condition that the USB transceiver is connected with an external device, the control circuit controls the USB transceiver to exit the low power consumption state; after the USB transceiver exits the low power consumption state, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and to connect the connection between the USB host controller and the USB transceiver.
Optionally, the interface component further includes a second signal switching circuit, and the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit, and the method further includes: under the condition that the USB transceiver is not connected with an external device, the control circuit controls the second signal switching circuit to communicate the connection between the control circuit and the USB host controller.
Optionally, the interface component further includes a detection circuit, the detection circuit is connected to the control circuit and the USB transceiver, and the method further includes: the control circuit receives a detection result transmitted by the detection circuit, and the detection result is used for indicating whether an external device is connected to the USB transceiver or not; under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state, and the method comprises the following steps: and under the condition that the detection result indicates that the USB transceiver is not connected with external equipment, controlling the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver and controlling the USB transceiver to enter the low power consumption state.
Optionally, the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal, the first input terminal and the first control terminal are respectively connected to the control circuit, the second input terminal is connected to the USB host controller, and the first output terminal is connected to the USB transceiver; the second signal switching circuit comprises a third input end, a fourth input end, a second output end and a second control end, the third input end and the second control end are respectively connected with the control circuit, the fourth input end is connected with the USB transceiver, and the second output end is connected with the USB host controller; under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, and the control circuit comprises: the control circuit controls the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver through the first control end under the condition that the USB transceiver is not connected with external equipment, and controls the second signal switching circuit to be communicated with the connection between the control circuit and the USB host controller through the second control end; under the condition that the USB transceiver is connected with external equipment, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver through the first control end and controls the connection between the USB host controller and the USB transceiver through the second control end.
Optionally, the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver and is configured to detect whether an external device is connected to the USB transceiver.
Optionally, when the USB transceiver is in the low power consumption state, a phase-locked loop PLL circuit of the USB transceiver is in an off state.
Note that "at least one of … …" in the embodiment of the present application means one of the listed items or any combination thereof, for example, "at least one of A, B and C" means: six cases of A alone, B alone, C alone, A and B together, A and C together, B and C together, and A, B and C together exist.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (20)

  1. An interface assembly, comprising: the USB host comprises a USB host controller, a USB transceiver, a control circuit and a first signal switching circuit, wherein the USB host controller and the control circuit are connected with the USB transceiver through the first signal switching circuit;
    the control circuit is used for controlling the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver under the condition that the USB transceiver is not connected with external equipment, so that the control circuit controls the USB transceiver to enter a low power consumption state.
  2. The interface assembly of claim 1,
    the control circuit is further used for controlling the USB transceiver to exit the low power consumption state under the condition that the USB transceiver is connected with external equipment;
    the control circuit is further configured to control the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and to connect the connection between the USB host controller and the USB transceiver after the USB transceiver exits from the low power consumption state.
  3. The interface module according to claim 1 or 2, wherein the interface module further comprises a second signal switching circuit, and the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit;
    the control circuit is further configured to control the second signal switching circuit to communicate the connection between the control circuit and the USB host controller when the USB transceiver is not connected to an external device.
  4. The interface assembly of any of claims 1-3, further comprising a detection circuit coupled to the control circuit and the USB transceiver;
    the detection circuit is used for detecting whether an external device is connected to the USB transceiver or not and transmitting a detection result to the control circuit;
    the control circuit is specifically configured to control the USB transceiver to enter the low power consumption state when the detection result indicates that the USB transceiver is not connected to an external device.
  5. The interface assembly of claim 4, wherein the control circuitry includes control registers, status registers, interrupt circuitry, and a Central Processing Unit (CPU);
    the state register is used for storing the detection result of the detection circuit and reporting the detection result to the CPU through the interrupt circuit;
    the CPU is used for executing at least one of the following operations when the detection result indicates that the USB transceiver is not connected with an external device:
    controlling the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver by configuring a first control signal in the control register;
    controlling the USB transceiver to enter the low power consumption state by configuring a second control signal in the control register;
    and controlling the second signal switching circuit to communicate the connection between the control circuit and the USB host controller by configuring a third control signal in the control register.
  6. The interface component of claim 5, wherein the CPU is further configured to, if the detection result indicates that the USB transceiver is connected to an external device, perform at least one of the following operations:
    controlling the USB transceiver to exit the low power consumption state by configuring the second control signal in the control register;
    after the USB transceiver exits the low power consumption state, the first signal switching circuit is controlled by the first control signal configured to the control register to disconnect the connection between the control circuit and the USB transceiver and connect the connection between the USB host controller and the USB transceiver.
  7. The interface component of claim 4 wherein the control circuitry comprises a control register, a status register, and control logic circuitry;
    the state register is used for storing the detection result of the detection circuit;
    the control logic circuit is configured to, if the detection result indicates that the USB transceiver is not connected to an external device, perform at least one of the following operations:
    controlling the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver;
    controlling the USB transceiver to enter the low power consumption state;
    and controlling the second signal switching circuit to be communicated with the connection between the control circuit and the USB host controller.
  8. The interface assembly of claim 7, wherein the control logic circuit is further configured to, if the detection result indicates that an external device is connected to the USB transceiver, perform at least one of the following operations:
    controlling the USB transceiver to exit the low power consumption state;
    and after the USB transceiver exits the low power consumption state, controlling the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and connect the connection between the USB host controller and the USB transceiver.
  9. Interface assembly according to any one of claims 3 to 8,
    the first signal switching circuit comprises a first input end, a second input end, a first output end and a first control end, wherein the first input end and the first control end are respectively connected with the control circuit, the second input end is connected with the USB host controller, and the first output end is connected with the USB transceiver;
    the second signal switching circuit comprises a third input end, a fourth input end, a second output end and a second control end, the third input end and the second control end are respectively connected with the control circuit, the fourth input end is connected with the USB transceiver, and the second output end is connected with the USB host controller;
    the control circuit is specifically configured to, when the USB transceiver is not connected to an external device, control the first signal switching circuit to communicate with the connection between the control circuit and the USB transceiver through the first control end, and control the second signal switching circuit to communicate with the connection between the control circuit and the USB host controller through the second control end;
    the control circuit is specifically configured to, when an external device is connected to the USB transceiver, control the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver through the first control end, and communicate the connection between the USB host controller and the USB transceiver through the first control end and the second control end.
  10. An interface assembly according to any one of claims 4 to 9, wherein the detection circuit comprises a filter, the filter being connected to the control circuit and to the USB transceiver for detecting whether an external device is connected to the USB transceiver.
  11. The interface assembly according to any one of claims 1 to 10, wherein a phase-locked loop, PLL, circuit of the USB transceiver is in an off state when the USB transceiver is in the low power consumption state.
  12. A chip comprising a processor and an interface assembly according to any one of claims 1 to 11.
  13. An electronic device comprising a processor, a memory, and an interface assembly as claimed in any one of claims 1 to 11.
  14. A control method, applied to an interface component, where the interface component includes a USB host controller, a USB transceiver, a control circuit, and a first signal switching circuit, where the USB host controller and the control circuit are connected to the USB transceiver through the first signal switching circuit, and the method includes:
    under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
  15. The method of claim 14, further comprising:
    under the condition that the USB transceiver is connected with an external device, the control circuit controls the USB transceiver to exit the low power consumption state;
    after the USB transceiver exits the low power consumption state, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver and to connect the connection between the USB host controller and the USB transceiver.
  16. The method of claim 14 or 15, wherein the interface assembly further comprises a second signal switching circuit, wherein the USB transceiver and the control circuit are connected to the USB host controller via the second signal switching circuit, and wherein the method further comprises:
    under the condition that the USB transceiver is not connected with an external device, the control circuit controls the second signal switching circuit to communicate the connection between the control circuit and the USB host controller.
  17. The method of any of claims 14 to 16, wherein the interface assembly further comprises a detection circuit coupled to the control circuit and the USB transceiver, the method further comprising:
    the control circuit receives a detection result transmitted by the detection circuit, and the detection result is used for indicating whether an external device is connected to the USB transceiver or not;
    under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state, and the method comprises the following steps:
    and under the condition that the detection result indicates that the USB transceiver is not connected with external equipment, the control circuit controls the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver and controls the USB transceiver to enter the low power consumption state.
  18. The method of claim 16 or 17,
    the first signal switching circuit comprises a first input end, a second input end, a first output end and a first control end, wherein the first input end and the first control end are respectively connected with the control circuit, the second input end is connected with the USB host controller, and the first output end is connected with the USB transceiver;
    the second signal switching circuit comprises a third input end, a fourth input end, a second output end and a second control end, the third input end and the second control end are respectively connected with the control circuit, the fourth input end is connected with the USB transceiver, and the second output end is connected with the USB host controller;
    under the condition that the USB transceiver is not connected with an external device, the control circuit controls the first signal switching circuit to communicate the connection between the control circuit and the USB transceiver, and the control circuit comprises:
    the control circuit controls the first signal switching circuit to be communicated with the connection between the control circuit and the USB transceiver through the first control end under the condition that the USB transceiver is not connected with external equipment, and controls the second signal switching circuit to be communicated with the connection between the control circuit and the USB host controller through the second control end;
    under the condition that the USB transceiver is connected with external equipment, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver through the first control end and controls the connection between the USB host controller and the USB transceiver through the second control end.
  19. The method of claim 17 or 18, wherein the detection circuit comprises a filter coupled to the control circuit and the USB transceiver for detecting whether an external device is connected to the USB transceiver.
  20. The method according to any of claims 14 to 19, wherein a phase-locked loop, PLL, circuit of the USB transceiver is in an off state when the USB transceiver is in the low power consumption state.
CN201980078223.0A 2019-05-31 2019-05-31 Interface assembly, chip and electronic equipment Pending CN113168207A (en)

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