CN116505500A - Electrostatic discharge ESD protection circuit of radio frequency switch - Google Patents

Abstract

The invention provides a radio frequency switch electrostatic discharge ESD protection circuit, comprising: a level shift circuit configured to supply a first positive voltage to the chip through the first pin, supply a first negative voltage to the chip through the pin, and output a first gate voltage through the third pin when the chip is powered; a positive clamp circuit configured to connect to the first pin, the third pin, and a ground node and clamp a first gate voltage when a forward electrostatic discharge, ESD, occurs; and a reverse clamp circuit configured to connect to the second pin, the third pin, and the ground node and clamp the first gate voltage when negative electrostatic discharge, ESD, occurs.

Description

Electrostatic discharge ESD protection circuit of radio frequency switch

Technical Field

The present disclosure relates generally to radio frequency switches, and in particular, to electrostatic discharge ESD protection circuits for radio frequency switches.

Background

An electrostatic Discharge (ESD, electroStatic Discharge) circuit is a circuit design commonly used in radio frequency switches. With rapid development of science and technology, wide application of microelectronic technology and more complex electromagnetic environment in recent years, attention is paid to electromagnetic field effects of electrostatic discharge such as electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems. ESD protection protects against electrostatic discharge, and prevents malfunction and malfunction of electronic devices. The ESD standards at the component level mainly include: a Charged Device Model (CDM), a Machine Model (MM), and a Human Body Model (HBM). The present invention is directed to ESD protection circuit schemes for the HBM standard.

The HBM standard is a physical representation of the electrostatic discharge phenomenon that occurs when a charged human body contacts one IC pin and the other IC pin is grounded. It is generally considered that in the environment-protecting area, the electrostatic potential generated by the human body is between 0.5 and 2 kV. The current pulse generated is limited by a discharge resistor of 1.5k ohms, resulting in a peak current of about 1.33A at a stress level of 2 kV. Thus, to achieve ESD protection, each IC pin must rely on self-protection provided by an internal power device or be connected to an ESD protection network. Since the proprietary ESD protection circuit of our general design itself introduces some parasitics (mainly parasitic capacitances), RF circuits often employ self-protection provided by the RF-functional device itself to achieve ESD discharge for ESD protection. Most Radio Frequency (RF) switches currently on the market generally employ the RF switch itself directly to provide ESD protection. Fig. 1 is a typical rf switch design. A typical switch is implemented with many NMOS series. When the Gate pin voltage is positive (a typical design may be 2.5V, which is process dependent, different processes are different), the switch is turned on, and when the Gate pin voltage is negative (a typical design is-2.5V, process dependent), the switch is turned off. The resistance values in the figures are generally relatively large to reduce the impact on the RF signal. When an ESD event occurs, such as a source (source) is grounded, static electricity discharges the corresponding IC pin of the drain (drain). These NMOS tubes can then fly back (snap-back) to achieve ESD discharge to prevent circuit damage.

The voltage between the source and the drain of each NMOS can be approximately 3-4V, which is similar to the withstand voltage of the NMOS. Fig. 2 shows a schematic diagram about a transistor jump. The NMOS is sized large enough to pass the current corresponding to the ESD discharge without damaging the circuit.

However, when the number of NMOS in series is large, the gate voltage is raised very high at the time of ESD discharge even though the NMOS itself is not damaged. At present, an SOI technology is adopted when an RF radio frequency switch is designed, and the withstand voltage of an MOS tube provided by the technology is limited to a certain extent. If the gate voltage rises to 10V or even higher when the ESD discharges. The high voltage is directly seen by the gate voltage driving circuit, and is often broken down by the high voltage first. This is one of the main reasons that current radio frequency switches cannot pass high ESD discharge standards (e.g. HBM 2 kV).

Disclosure of Invention

Technical problem

For the traditional ESD protection circuit, aiming at the main reason of the ESD failure of the radio frequency RF switch, the invention provides a new circuit which ensures that the voltage of the Gate pin does not exceed a certain limit value under any condition, so that the voltage breakdown of the Gate driving circuit does not occur, and the chip pin of the radio frequency switch is effectively protected by ESD.

Solution scheme

There is provided, in accordance with an embodiment of the present disclosure, a radio frequency switch electrostatic discharge ESD protection circuit comprising: a level shift circuit configured to supply a first positive voltage to the chip through the first pin, supply a first negative voltage to the chip through the pin, and output a first gate voltage through the third pin when the chip is powered; a positive clamp circuit configured to connect to the first pin, the third pin, and a ground node and clamp a first gate voltage when a forward electrostatic discharge, ESD, occurs; and a reverse clamp circuit configured to connect to the second pin, the third pin, and the ground node and clamp the first gate voltage when negative electrostatic discharge, ESD, occurs.

Embodiments according to the present disclosure provide a radio frequency switch electrostatic discharge ESD protection circuit in which the positive clamp and the negative clamp have no effect on the output of the level shift circuit when the chip is powered.

There is provided, in accordance with an embodiment of the present disclosure, a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the positive clamp circuit includes: a first transistor configured to have a gate connected to the first pin, a source connected to a clamp voltage node, and a drain connected to a drain of a second transistor; a second transistor configured to have a gate connected to the first pin, a source connected to a ground node, and a drain connected to a drain of the first transistor; a third transistor configured to have a gate connected to a ground node, a source connected to the first pin, and a drain connected to a gate of the fifth transistor; a fourth transistor configured to have a gate connected to the drain of the second transistor, a source connected to a ground node, and a drain connected to the gate of the fifth transistor; and a fifth transistor configured to have a gate connected to a drain of the fourth transistor, a source connected to the clamp voltage node, and a drain connected to a ground node.

There is provided in accordance with an embodiment of the present disclosure a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the positive clamp circuit further comprises a first diode, an anode of the first diode is connected to the third pin, and a cathode of the first diode is connected to the clamp voltage node.

There is provided, in accordance with an embodiment of the present disclosure, a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the positive clamp circuit includes: a first transistor configured to have a gate connected to the first pin, a source connected to a ground node, and a drain connected to a gate of a second transistor; a second transistor configured to have a gate connected to the drain of the first transistor, a source connected to the ground node, and a drain connected to the clamp voltage node.

There is provided in accordance with an embodiment of the present disclosure a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the positive clamp circuit further comprises: a first diode, an anode of the first diode being connected to the third pin, and a cathode of the first diode being connected to the clamp voltage node; and a first capacitor configured to have one end connected to a drain of the first transistor and the other end connected to the third pin.

There is provided, in accordance with an embodiment of the present disclosure, a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the negative clamp circuit includes: a first transistor configured to have a gate connected to the second pin, a source connected to a ground node, and a drain connected to a drain of the second transistor; a second transistor configured to have a gate connected to the second pin, a source connected to a clamp voltage node, and a drain connected to a drain of the first transistor; a third transistor configured to have a gate connected to a drain of the second transistor, a source connected to a ground node, and a drain connected to a gate of the fifth transistor; a fourth transistor configured to have a gate connected to a ground node, a source connected to the second pin, and a drain connected to a gate of the fifth transistor; and a fifth transistor configured to have a gate connected to a drain of the fourth transistor, a source connected to the clamp voltage node, and a drain connected to a ground node.

There is provided in accordance with an embodiment of the present disclosure a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the negative clamp circuit further comprises a first diode, an anode of the first diode is connected to the clamp voltage node, and a cathode of the first diode is connected to the third pin.

There is provided, in accordance with an embodiment of the present disclosure, a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the negative clamp circuit includes: a first transistor configured to have a gate connected to the second pin, a source connected to a ground node, and a drain connected to a gate of the second transistor; a second transistor configured to have a gate connected to the drain of the first transistor, a source connected to the ground node, and a drain connected to the clamp voltage node.

There is provided in accordance with an embodiment of the present disclosure a radio frequency switch electrostatic discharge, ESD, protection circuit, wherein the negative clamp circuit further comprises: a first diode, an anode of the first diode being connected to the clamp voltage node, and a cathode of the first diode being connected to the third pin; and a first capacitor configured to have one end connected to a drain of the first transistor and the other end connected to the third pin.

Technical effects

The circuit is provided for the main reason of the ESD failure of the radio frequency RF switch, and the voltage of the Gate pin of the circuit does not exceed a certain limit value under any condition, so that the voltage breakdown of the Gate driving circuit does not occur, and therefore, the chip pin of the radio frequency switch is effectively protected by the ESD.

Drawings

The foregoing and other aspects, features, and advantages of certain embodiments of the disclosure will become more apparent from the following description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram showing the circuitry of a typical radio frequency switch;

fig. 2 is a schematic diagram showing a back-jump with respect to a transistor;

FIG. 3 is a schematic diagram showing a typical Gate drive circuit for a radio frequency switch;

FIG. 4 shows a schematic diagram illustrating an ESD protection circuit in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a positive clamp circuit according to an embodiment of the invention;

FIG. 6 is a schematic diagram illustrating a positive clamp circuit according to another embodiment of the invention;

FIG. 7 is a schematic diagram of ESD protection simulation results for a positive clamp circuit in accordance with an embodiment of the present invention;

FIG. 8 is a schematic diagram of ESD protection simulation results without positive clamp;

FIG. 9 is a schematic diagram illustrating a negative clamp circuit according to an embodiment of the invention;

FIG. 10 is a schematic diagram illustrating a negative clamp circuit according to another embodiment of the invention;

FIG. 11 is a schematic diagram of ESD protection simulation results for a negative clamp circuit in accordance with an embodiment of the present invention; and

fig. 12 is a schematic diagram of ESD protection simulation results without a negative clamp.

Detailed Description

Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrase "associated with … …" and its derivatives are intended to include, be included in, interconnect with, contain within … …, connect or connect with … …, couple or couple with … …, communicate with … …, mate, interleave, juxtapose, approximate, bind or bind with … …, have attributes, have relationships or have relationships with … …, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one," when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.

Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.

In this patent document, the application combinations of transform blocks and the division levels of sub-transform blocks are for illustration only, and the application combinations of transform blocks and the division levels of sub-transform blocks may have different manners without departing from the scope of the present disclosure.

Figures 1 through 12, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will appreciate that the principles of the present disclosure may be implemented in any suitably arranged system or device.

Fig. 3 is a schematic diagram showing a typical Gate drive circuit for a radio frequency switch.

A typical gate drive circuit is shown in fig. 3. Wherein the positive voltage Vp and the negative voltage Vn are positive and negative power supplies of the level shift circuit, and the output level voltage of the level shift circuit is represented by V _P And V _n And (5) determining. The output voltage of the level shift circuit is the grid voltage V _Gate . The voltage Vp is positive (typically 2.5V) when the chip is in operation and the voltage Vn is negative (typically-2.5V) when the chip is in operation. According to the embodiment of the invention, the output voltage can be defined as V _P Logic "1" at the time; the output voltage is at V _n And is a logic "0" when. Vp and Vn are not driven when ESD occurs, because there is no power at this time, and thus their voltage is 0.

Fig. 4 shows a schematic diagram illustrating an ESD protection circuit according to an embodiment of the invention.

Aiming at the main reason of the ESD failure of the radio frequency RF switch, the invention provides a new circuit which ensures that the voltage of the Gate pin does not exceed a certain limit value under any condition, so that the voltage breakdown of the Gate driving circuit does not occur, and the chip pin of the radio frequency switch is effectively protected by ESD.

Referring to fig. 4, the positive voltage Vp and the negative voltage Vn are positive and negative power supplies of the level shift circuit, and the output level voltage of the level shift circuit is represented by V _P And V _n And (5) determining. The output voltage of the level shift circuit is the grid voltage V _Gate . According to the embodiment of the invention, the output voltage can be defined as V _P Logic "1" at the time; the output voltage is at V _n And is a logic "0" when. Two voltage clamping circuits are provided at the Gate pin of the radio frequency switch, which circuits are arranged to be turned off automatically when the circuit is operating normally (when the chip is powered by a power supply and Vp and Vn are driven), and to clamp the Gate pin voltage when the ESD discharges.

Fig. 5 is a schematic diagram illustrating a positive clamp circuit according to an embodiment of the invention.

Referring to fig. 5, vp is at zero potential when the forward ESD discharges (e.g., hbm+2kv). Therefore, the gate voltage of the NMOS transistor M2 is low, and the transistor M2 is turned off; when the Vclamp voltage rises, the PMOS transistor M1 is turned on. Thus, when the gate voltage rises, the Vclamp voltage rises, so that the gate voltage of transistor M4 is near or equal to Vclamp, thereby turning on transistor M4 and pulling the gate of transistor M5 to ground. Since the transistor M5 is a PMOS transistor, the Vclamp voltage is clamped around Vth (MOS transistor on threshold voltage) by the transistor M5. Thus, the Gate pin voltage is clamped. When the circuit is operating normally, for example Vp is 2.5v, pmos transistor M3 is conductive (its gate is grounded). Transistor M2 is turned on to pull the gate of transistor M4 to zero volts. Transistor M1 is turned off because its gate voltage is not too high for Vp. Therefore, the gate voltage of the transistor M5 is close to or equal to Vp, so the transistor M5 is turned off, so that the Vclamp point is in a high-resistance state. Thus, the above circuit does not affect the gate drive circuit.

Fig. 6 is a schematic diagram illustrating a positive clamp circuit according to another embodiment of the invention.

Referring to fig. 6, vp approaches zero volts when an ESD discharge occurs. The transistor M1 is turned off so that the Gate pin voltage jumps up due to the ESD discharge. Because the Gate of the transistor M2 is in a high-resistance state, the Gate of the transistor M2 will jump up with the Gate pin voltage. The NMOS transistor M2 is turned on to clamp Vclamp at a relatively low voltage, and thus the Gate pin voltage is also clamped. When the chip is powered on and normally works, vp is 2.5V, the transistor M1 is turned on to force the gate of the transistor M2 to be grounded, so that the transistor M2 is turned off, and Vclamp is in a high-resistance state. Therefore, this circuit does not affect the gate drive circuit.

Fig. 7 is a schematic diagram of ESD protection simulation results for a positive clamp circuit according to an embodiment of the invention.

Referring to fig. 7, the Gate pin voltage is less than 3V at the ESD discharge of HBM 2kV, and thus, the voltage is within the device withstand range.

Fig. 8 is a schematic diagram of ESD protection simulation results without positive clamp.

Referring to fig. 8, the Gate pin voltage is greater than 10V or even higher without the clamp circuit, and thus, the driving circuit of the Gate pin is broken down at the time of ESD discharge, resulting in chip damage.

Fig. 9 is a schematic diagram illustrating a negative clamp circuit according to an embodiment of the invention.

Referring to fig. 9, transistors M1 and M3 are PMOS transistors, and transistors M2, M4, and M5 are NMOS transistors. D1 is a diode. When an ESD discharge occurs, the Vn voltage is around zero volts. Thus, transistor M1 is turned off and transistor M2 is turned on, such that the gate voltage drops and Vclamp will follow on a negative (e.g., HBM-2 kV) ESD discharge, such that transistor M3 is turned on, which in turn pulls the gate of transistor M5 down by approximately zero volts, because transistor M2 is turned on such that the gate voltage of transistor M3 is approximately equal to Vclamp. Therefore, the transistor M5 clamps Vclamp around-Vth (MOS transistor on threshold voltage), so that the Gate pin voltage is also clamped. If the chip has a power bias, when the chip is operating, vn is no longer zero volts, for example, -2.5V, transistor M1 is turned on such that the gate of transistor M3 is grounded and such that transistor M3 is in an off state. Because transistor M4 is turned on at this time, the gate voltage of transistor M5 will be near or equal to Vn. Here, the transistor M5 is turned off, vclamp is in a high-resistance state, and the clamp circuit does not affect the gate drive circuit.

Fig. 10 is a schematic diagram illustrating a negative clamp circuit according to another embodiment of the invention.

Referring to fig. 10, when a negative ESD (e.g., HBM-2 kV) discharge occurs, vn approaches zero volts. The transistor M1 is turned off, and thus the Gate pin voltage jumps down due to the ESD discharge. Since the Gate of the transistor M2 is in a high-resistance state, the Gate of the transistor M2 will jump down with the Gate pin voltage. The PMOS transistor M2 is turned on to clamp Vclamp to near zero volts, and therefore the Gate pin voltage is also clamped. When the chip is powered on and then normally works, vn is-2.5V (for example), the transistor M1 is turned on, so that the gate of the transistor M2 is forced to be grounded, and therefore the transistor M2 is turned off, so that the Vclamp is in a high-resistance state, and thus, the circuit does not affect the driving circuit of the gate.

Fig. 11 is a schematic diagram of ESD protection simulation results of a negative clamp circuit according to an embodiment of the invention.

Referring to fig. 11, the Gate pin voltage is greater than-3V at the ESD discharge of HBM-2kV, and thus, the voltage is within the device withstand range.

Fig. 12 is a schematic diagram of ESD protection simulation results without a negative clamp.

Referring to fig. 12, without the clamp circuit, the Gate drive circuit would generate a voltage of-6V at HBM-2kV, resulting in damage to the circuit voltage over voltage.

The text and drawings are provided as examples only to aid in the understanding of the present disclosure. They should not be construed as limiting the scope of the disclosure in any way. While certain embodiments and examples have been provided, it will be apparent to those of ordinary skill in the art from this disclosure that variations can be made to the embodiments and examples shown without departing from the scope of the disclosure.

According to the embodiment of the disclosure, the high gain is realized through a two-stage amplifier structure, the broadband matching is realized by utilizing feedback, and an adjustable device is adopted, so that the two-stage broadband high-gain low-noise amplifier with adjustable gain is realized.

Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The disclosure is intended to embrace such alterations and modifications that fall within the scope of the appended claims.

Any description of the present invention should not be construed as implying that any particular element, step, or function is a necessary element to be included in the scope of the claims. The scope of patented subject matter is defined only by the claims.

Claims (10)

1. A radio frequency switch electrostatic discharge ESD protection circuit comprising:

a level shift circuit configured to supply a first positive voltage to the chip through the first pin, supply a first negative voltage to the chip through the pin, and output a first gate voltage through the third pin when the chip is powered;

a positive clamp circuit configured to connect to the first pin, the third pin, and a ground node and clamp a first gate voltage when a forward electrostatic discharge, ESD, occurs;

and a reverse clamp circuit configured to connect to the second pin, the third pin, and the ground node and clamp the first gate voltage when negative electrostatic discharge, ESD, occurs.

2. The ESD protection circuit of claim 1, wherein the positive clamp and the negative clamp are turned off when a chip is powered.

3. The ESD protection circuit of claim 1, wherein the positive clamp circuit comprises:

a first transistor configured to have a gate connected to the first pin, a source connected to a clamp voltage node, and a drain connected to a drain of a second transistor;

a second transistor configured to have a gate connected to the first pin, a source connected to a ground node, and a drain connected to a drain of the first transistor;

a third transistor configured to have a gate connected to a ground node, a source connected to the first pin, and a drain connected to a gate of the fifth transistor;

a fourth transistor configured to have a gate connected to the drain of the second transistor, a source connected to a ground node, and a drain connected to the gate of the fifth transistor; and

a fifth transistor configured to have a gate connected to the drain of the fourth transistor, a source connected to the clamp voltage node, and a drain connected to a ground node.

4. The ESD protection circuit of claim 3, wherein the positive clamp circuit further comprises a first diode having an anode connected to the third pin and a cathode connected to the clamp voltage node.

5. The ESD protection circuit of claim 1, wherein the positive clamp circuit comprises:

a first transistor configured to have a gate connected to the first pin, a source connected to a ground node, and a drain connected to a gate of a second transistor;

a second transistor configured to have a gate connected to the drain of the first transistor, a source connected to the ground node, and a drain connected to the clamp voltage node.

6. The ESD protection circuit of claim 5, wherein the positive clamp circuit further comprises:

a first diode, an anode of the first diode being connected to the third pin, and a cathode of the first diode being connected to the clamp voltage node; and

a first capacitor configured to have one end connected to the drain of the first transistor and the other end connected to the third pin.

7. The ESD protection circuit of claim 1, wherein the negative clamp circuit comprises:

a first transistor configured to have a gate connected to the second pin, a source connected to a ground node, and a drain connected to a drain of the second transistor;

a second transistor configured to have a gate connected to the second pin, a source connected to a clamp voltage node, and a drain connected to a drain of the first transistor;

a third transistor configured to have a gate connected to a drain of the second transistor, a source connected to a ground node, and a drain connected to a gate of the fifth transistor;

a fourth transistor configured to have a gate connected to a ground node, a source connected to the second pin, and a drain connected to a gate of the fifth transistor; and

a fifth transistor configured to have a gate connected to the drain of the fourth transistor, a source connected to the clamp voltage node, and a drain connected to a ground node.

8. The ESD protection circuit of claim 7, wherein the negative clamp circuit further comprises a first diode having an anode connected to the clamp voltage node and a cathode connected to the third pin.

9. The ESD protection circuit of claim 1, wherein the negative clamp circuit comprises:

a first transistor configured to have a gate connected to the second pin, a source connected to a ground node, and a drain connected to a gate of the second transistor;

a second transistor configured to have a gate connected to the drain of the first transistor, a source connected to the ground node, and a drain connected to the clamp voltage node.

10. The ESD protection circuit of claim 9, wherein the negative clamp circuit further comprises:

a first diode, an anode of the first diode being connected to the clamp voltage node, and a cathode of the first diode being connected to the third pin; and

a first capacitor configured to have one end connected to the drain of the first transistor and the other end connected to the third pin.