CN116504609A - Method for eliminating stress of warpage wafer - Google Patents
Method for eliminating stress of warpage wafer Download PDFInfo
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- CN116504609A CN116504609A CN202310769716.7A CN202310769716A CN116504609A CN 116504609 A CN116504609 A CN 116504609A CN 202310769716 A CN202310769716 A CN 202310769716A CN 116504609 A CN116504609 A CN 116504609A
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- 238000012360 testing method Methods 0.000 claims abstract description 4
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- 239000000463 material Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 15
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- 230000001070 adhesive effect Effects 0.000 claims description 10
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- 239000002253 acid Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- DHKHKXVYLBGOIT-UHFFFAOYSA-N acetaldehyde Diethyl Acetal Natural products CCOC(C)OCC DHKHKXVYLBGOIT-UHFFFAOYSA-N 0.000 claims description 5
- 125000002777 acetyl group Chemical group [H]C([H])([H])C(*)=O 0.000 claims description 5
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 5
- 150000007529 inorganic bases Chemical class 0.000 claims description 5
- 239000002904 solvent Substances 0.000 claims description 5
- 150000007522 mineralic acids Chemical class 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 150000002148 esters Chemical class 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920000728 polyester Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
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- 229920002635 polyurethane Polymers 0.000 claims description 3
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- 229920000915 polyvinyl chloride Polymers 0.000 claims description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000002411 adverse Effects 0.000 abstract description 6
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Abstract
The invention discloses a method for eliminating stress of a warped wafer, which comprises the following steps: performing curvature test on the warped wafer at room temperature to obtain the warp of the wafer; selecting the types of the adhesion layer and the stress layer according to the warpage of the wafer; sequentially forming an adhesion layer and a stress layer on the back surface of the wafer, so that the stress formed by the adhesion layer and the stress layer is balanced with the stress of the wafer, and the surface of the wafer at room temperature is leveled; after the device process is completed, the adhesive layer and the stress layer are heated at a first section temperature of 25-75 ℃, and then the adhesive layer and the stress layer are heated at a second section temperature of-55-10 ℃, so that the adhesive layer and the stress layer are peeled off from the back of the wafer, and the back of the wafer is broken, thereby eliminating the stress in the wafer. The invention can eliminate the adverse effect of wafer warpage on the device process, and can eliminate the stress in the warped wafer, thereby preventing the risk of fragments.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for eliminating stress of a warped wafer.
Background
In semiconductor manufacturing, after undergoing a plurality of manufacturing processes, a lot of stress is inevitably accumulated on the wafer, resulting in warp deformation of the wafer. The presence of warpage can deform the wafer and thus can degrade the lithographic accuracy when performing photolithography. In order to reduce adverse effects of wafer warpage on device technology, CN103871837a discloses a method for improving wafer warpage by using film-sticking materials (such as blue films) with different thermal expansion coefficients, improving wafer warpage by means of thermal expansion and cold contraction, and removing the film-sticking materials after the device technology is completed. Regarding removal of the film-sticking material, CN104966675a discloses a method for protecting a silicon dioxide film on a surface portion of a silicon wafer using a blue film. However, after removal of the blue film, if the stress left by the warped wafer is excessive, further processing is still required to relieve the remaining stress, preventing the risk of chipping during transportation or dicing of the wafer.
Disclosure of Invention
The invention aims to provide a method for eliminating stress of a warped wafer, which can eliminate adverse effects of wafer warpage on a device process, and can eliminate stress in the warped wafer so as to prevent the risk of fragments.
One aspect of the present invention provides a warp wafer stress relief method comprising the steps of:
step S1: performing curvature test on the warped wafer at room temperature to obtain the warp of the wafer;
step S2: selecting the types of the adhesion layer and the stress layer according to the warpage of the wafer;
step S3: sequentially forming an adhesion layer and a stress layer on the back surface of the wafer, so that the stress formed by the adhesion layer and the stress layer is balanced with the stress of the wafer, and the surface of the wafer at room temperature is leveled;
step S4: after the device process is completed, the adhesive layer and the stress layer are heated at a first section temperature of 25-75 ℃, and then the adhesive layer and the stress layer are heated at a second section temperature of-55-10 ℃, so that the adhesive layer and the stress layer are peeled off from the back of the wafer, and the back of the wafer is broken, thereby eliminating the stress in the wafer.
Preferably, the stress layer and the adhesion layer are metallic materials, the metallic material of the stress layer comprises one or more of Ni, fe, cu, W or Au, and the metallic material of the adhesion layer is Ti, alCu, tiW or NiV.
Preferably, the thickness of the metal material of the stress layer is 6 um-50 um, and the thickness of the metal material of the adhesion layer is 0.02 um-1 um.
Preferably, the stress layer is a dielectric material including silicon oxide and silicon nitride, and the adhesion layer is a polymer material including polyimide, polyurethane, polyester, polyolefin acid ester, and polyvinyl chloride.
Preferably, the thickness of the stress layer and the adhesion layer is 100um to 300um.
Preferably, the stress layer is a blue film or pressure sensitive tape and the adhesion layer is an acetal or ketal diepoxide based adhesive or an acrylic based adhesive.
Preferably, the method further comprises: the wafer is placed in an inorganic acid or inorganic base solvent to separate the adhesion layer and the stress layer.
Preferably, in step S3, a thin film layer is further formed on the stress layer, so that stress formed by the adhesion layer, the stress layer and the thin film layer is balanced with stress of the warped wafer, thereby flattening the surface of the wafer at room temperature; in step S4, the adhesion layer, the stress layer, and the thin film layer are peeled from the wafer back surface.
Preferably, the thin film layer is made of a metal material, a dielectric material or a polymer material.
Preferably, in step S4, the breakage of the internal stress of the wafer is eliminated so that a portion of the back surface of the wafer is peeled off together with the adhesion layer and the stress layer.
The method for eliminating the stress of the warpage wafer can eliminate the adverse effect of wafer warpage on the device process, and can eliminate the stress in the warpage wafer so as to prevent the risk of fragments.
Drawings
For a clearer description of the technical solutions of the present invention, the following description will be given with reference to the attached drawings used in the description of the embodiments of the present invention, it being obvious that the attached drawings in the following description are only some embodiments of the present invention, and that other attached drawings can be obtained by those skilled in the art without the need of inventive effort:
FIG. 1 is a flow chart of a method of stress relief of a warped wafer according to one embodiment of the present invention.
Fig. 2 is a schematic view of a warped wafer according to one embodiment of the present invention.
Fig. 3 is a schematic view of a warped wafer formed with an adhesion layer and a stress layer, according to one embodiment of the present invention.
Fig. 4 is a schematic view of the adhesion and stress layers of an embodiment of the present invention being peeled from the back side of a wafer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides a method for eliminating stress of a warpage wafer, and fig. 1 is a flowchart of a method for eliminating stress of a warpage wafer according to an embodiment of the present invention. As shown in fig. 1, the method for eliminating warpage wafer stress in the embodiment of the present invention includes steps S1 to S4.
In step S1, a curvature test is performed on the warped wafer at room temperature to obtain the warp of the warped wafer. Fig. 2 is a schematic view of a warped wafer according to one embodiment of the present invention, wherein 11 is the warped wafer. The warped wafer 11 may be Si, inP, gaN, gaAs, siC, znO, alN, liTaO 3 And LiNbO 3 Etc.
In step S2, the kind of the adhesion layer and the stress layer to be formed in the subsequent step S3 is selected according to the warp degree of the warp wafer 11. In this step, the relationship between the warp of the warp wafer 11 and the types of the stress layer and the adhesion layer used is experimentally determined.
In step S3, an adhesion layer and a stress layer are sequentially formed on the back surface of the warped wafer, so that the stress formed by the adhesion layer and the stress layer is balanced with the stress of the warped wafer, and the wafer surface at room temperature is leveled. Fig. 3 is a schematic view of a warped wafer formed with an adhesion layer and a stress layer, according to one embodiment of the present invention. As shown in fig. 3, an adhesion layer 12 is formed on the back surface of the warped wafer 11, and then a stress layer 13 is formed on the adhesion layer 12, so that the surface of the wafer 11 at room temperature is leveled, that is, the stress formed by the adhesion layer 12 and the stress layer 13 is balanced with the stress of the warped wafer 11. The adhesion layer 12 is formed to increase adhesion between the backside of the warped wafer 11 and the stress layer 13.
Preferably, a thin film layer may be further formed on the stress layer 13 to further control warpage, so that stress formed by the adhesion layer 12, the stress layer 13 and the thin film layer is balanced with stress of the warped wafer 11, and finally the wafer surface at room temperature is leveled. The thin film layer is used for further improving the warpage and further controlling the breakage in the subsequent step, and the material can be a metal material, a dielectric material or a high polymer material, and the thickness is 1 um-10 mm, for example.
Preferably, the back side of the warped wafer 11 has a surface roughness of 1 to 10nm, preferably 1 to 8nm, and most preferably 5nm.
Preferably, the stress layer 13 and the adhesion layer 12 are formed by dip coating, spin coating, brush coating, electroplating, sputtering, chemical vapor deposition, atomic layer deposition, or the like.
In step S4, after the device process is completed, the adhesion layer 12 and the stress layer 13 on the back surface of the warped wafer 11 are removed. In the case where the thin film layer is further formed, the adhesion layer, the stress layer and the thin film layer on the back surface of the warped wafer are removed after the device process is completed. The device process herein is, for example, a process in a semiconductor manufacturing process such as a photolithography process, a dicing process, and the like. Fig. 4 is a schematic view of the adhesion and stress layers of an embodiment of the present invention being peeled from the back side of a wafer. The wafer 11 after the adhesion layer 12 and the stress layer 13 are peeled off becomes flat due to the stress being removed.
In this step, the warp wafer 11 is separated from the adhesion layer 12 and the stress layer 13 by means of temperature adjustment, in this step, the temperature adjustment is divided into two temperatures, and first, the adhesion layer 12 and the stress layer 13 are heated at a first temperature of 25 ℃ to 75 ℃; the adhesion layer 12 and the stress layer 13 are then heated at a second stage temperature of-55 to 10 c, preferably-55 to 0 c.
The stress differential created by the first and second stage temperatures causes the adhesion layer 12 and the stress layer 13 to peel off along the back side of the wafer 11 and causes a depth of fracture in the back side of the wafer 11 that relieves the stress inside the wafer 11.
In this step, the composition, thickness and stress of the adhesion layer 12, the stress layer 13 (and optionally the thin film layer) do not lead to a fracture inside the wafer 11 at the first stage temperature, whereas the stress resulting from the separation of the adhesion layer 12, the stress layer 13 (and optionally the thin film layer) at the second stage temperature only leads to a desired fracture depth inside the wafer 11.
In one embodiment, the fracture that relieves the stress inside the wafer 11 causes a very small portion of the wafer 11 to separate along with the adhesion layer 12 and the stress layer 13.
The material of the stress layer 13 may be a metal material, a dielectric material or a polymer material, and the material of the adhesion layer 12 may be a metal or a polymer gel.
In one embodiment, the material of stress layer 13 is a metallic material, including but not limited to one or more of Ni, fe, cu, W or Au, and the material of adhesion layer 12 is a metallic material, such as Ti, alCu, tiW or NiV. The thickness of the metal material of the stress layer 13 is 6um to 50um, and the thickness of the metal material of the adhesion layer 12 is 0.02um to 1um.
In another embodiment, the material of the stress layer 13 is a dielectric material, such as silicon oxide or silicon nitride, and the amount and type of force applied by the stress layer 13 to the warped wafer 11 can be adjusted by adjusting the gas pressure, plasma power, temperature, carrier gas ratio, deposition cycle time, etc. The material of the adhesion layer 12 is a high molecular material including, but not limited to, polyimide, polyurethane, polyester, polyolefin acid ester and polyvinyl chloride, and the thickness of the stress layer 13 and the adhesion layer 12 is 100um to 300um.
In another embodiment, the material of the stress layer 13 is a polymeric material, such as a blue film or a pressure sensitive tape, and the adhesion layer 12 is an acetal or ketal diepoxide-based adhesive or an acrylic-based adhesive. In this embodiment, the adhesion layer 12 and the stress layer 13 may also be separated by adjusting the solvent. The solvent may be an inorganic acid or an inorganic base. The inorganic acid may be one of sulfuric acid, hydrochloric acid or nitric acid, and the inorganic base may be ammonia water. Preferably, the pH value of the electrodeless acid is less than or equal to 2, and the temperature is 25-30 ℃; the mass concentration of the inorganic base is 10-14%, and the temperature is 55-60 ℃.
The acetal or ketal diepoxide-based adhesive or acrylic-based adhesive does not react with other solvents in the process, but the acetal or ketal diepoxide-based adhesive reacts with an acid to cause a much reduced tackiness, and the acrylic-based adhesive reacts with an alkali to cause a much reduced tackiness, and by utilizing these characteristics, after the end of the process, the wafer 11 to which the adhesive layer 12 and the stress layer 13 are attached is immersed in a usual acid or alkali solution which has little influence on the wafer 11 and is used in a large amount in the process, and after the reaction, the adhesive layer 12 and the stress layer 13 are detached from the back surface of the wafer 11. To increase the stripping rate, the acid or base solution may be heated to a temperature of 25 ℃ to 30 ℃ or 55 to 65 ℃, preferably 25 ℃ or 58 ℃.
As described above, the stress relief method for a warped wafer according to the embodiments of the present invention deposits an adhesion layer and a stress layer on a wafer to be subjected to warpage improvement, and then drops the wafer by a temperature method after the process is completed, thereby not only reducing adverse effects of the warped wafer on the device process, but also relieving stress in the warped wafer and preventing the risk of chipping. Specifically, the method of the invention is to deposit an adhesion layer 12, a stress layer 13 and an optional film layer on the back of the warped wafer, so that the overall stress and the stress of the wafer are mutually counteracted to obtain a flat composite substrate, thereby eliminating the adverse effect of wafer warpage on the process; in addition, the flat composite substrate obtained after the stress in the warped wafer is eliminated by the method can be safely carried by a manipulator, and the risk of fragments in the wafer conveying or dicing process is reduced.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.
Claims (10)
1. A method for stress relief of a warped wafer, comprising the steps of:
step S1: performing curvature test on the warped wafer at room temperature to obtain the warp of the wafer;
step S2: selecting the types of the adhesion layer and the stress layer according to the warpage of the wafer;
step S3: sequentially forming an adhesion layer and a stress layer on the back surface of the wafer, so that the stress formed by the adhesion layer and the stress layer is balanced with the stress of the wafer, and the surface of the wafer at room temperature is leveled;
step S4: after the device process is completed, the adhesive layer and the stress layer are heated at a first section temperature of 25-75 ℃, and then the adhesive layer and the stress layer are heated at a second section temperature of-55-10 ℃, so that the adhesive layer and the stress layer are peeled off from the back of the wafer, and the back of the wafer is broken, thereby eliminating the stress in the wafer.
2. The method of claim 1, wherein the stress layer and the adhesion layer are metallic materials, the metallic material of the stress layer comprising one or more of Ni, fe, cu, W or Au, the metallic material of the adhesion layer being Ti, alCu, tiW or NiV.
3. The method of claim 2, wherein the stress layer has a metal material thickness of 6um to 50um and the adhesion layer has a metal material thickness of 0.02um to 1um.
4. The method of claim 1, wherein the stress layer is a dielectric material including silicon oxide and silicon nitride and the adhesion layer is a polymeric material including polyimide, polyurethane, polyester, polyolefin acid ester, and polyvinyl chloride.
5. The method of claim 4, wherein the stress layer and the adhesion layer have a thickness of 100um to 300um.
6. The method of claim 1, wherein the stress layer is a blue film or a pressure sensitive tape and the adhesion layer is an acetal or ketal diepoxide based adhesive or an acrylic based adhesive.
7. The method as recited in claim 6, further comprising: the wafer is placed in an inorganic acid or inorganic base solvent to separate the adhesion layer and the stress layer.
8. The method of claim 1, wherein in step S3, a thin film layer is further formed on the stress layer, such that stress formed by the adhesion layer, the stress layer, and the thin film layer is balanced with stress of the warped wafer, thereby planarizing the wafer surface at room temperature; in step S4, the adhesion layer, the stress layer, and the thin film layer are peeled from the wafer back surface.
9. The method of claim 8, wherein the thin film layer is a metallic material, a dielectric material, or a polymeric material.
10. The method of claim 1, wherein in step S4, the breaking of the wafer internal stress is eliminated such that a portion of the wafer backside is peeled off together with the adhesion layer and the stress layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310769716.7A CN116504609B (en) | 2023-06-28 | 2023-06-28 | Method for eliminating stress of warpage wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310769716.7A CN116504609B (en) | 2023-06-28 | 2023-06-28 | Method for eliminating stress of warpage wafer |
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| CN116504609A true CN116504609A (en) | 2023-07-28 |
| CN116504609B CN116504609B (en) | 2023-09-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116874991A (en) * | 2023-09-08 | 2023-10-13 | 武汉市三选科技有限公司 | Wafer warp control epoxy functional film, preparation method and application thereof |
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| CN108183065A (en) * | 2017-12-29 | 2018-06-19 | 北京品捷电子科技有限公司 | A kind of method and compound substrate for eliminating silicon wafer warpage |
| CN110235220A (en) * | 2016-09-16 | 2019-09-13 | Ii-Vi光电子设备有限公司 | The metal adjustable thin film stress compensation of epitaxial wafer |
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2023
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030033974A1 (en) * | 2001-07-11 | 2003-02-20 | Tetsuzo Ueda | Layered substrates for epitaxial processing, and device |
| CN103871837A (en) * | 2012-12-18 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Method for improving warping degree of wafer |
| US20170162522A1 (en) * | 2015-07-01 | 2017-06-08 | Ii-Vi Optoelectronic Devices, Inc. | Stress relief in semiconductor wafers |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116874991A (en) * | 2023-09-08 | 2023-10-13 | 武汉市三选科技有限公司 | Wafer warp control epoxy functional film, preparation method and application thereof |
| CN116874991B (en) * | 2023-09-08 | 2023-12-15 | 武汉市三选科技有限公司 | Wafer warp control epoxy functional film, preparation method and application thereof |
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| CN116504609B (en) | 2023-09-15 |
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