CN116490042A - Graphene/hexagonal boron nitride heterojunction field effect transistor and preparation method thereof - Google Patents
Graphene/hexagonal boron nitride heterojunction field effect transistor and preparation method thereof Download PDFInfo
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- CN116490042A CN116490042A CN202310423830.4A CN202310423830A CN116490042A CN 116490042 A CN116490042 A CN 116490042A CN 202310423830 A CN202310423830 A CN 202310423830A CN 116490042 A CN116490042 A CN 116490042A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 76
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 75
- 229910052582 BN Inorganic materials 0.000 title claims abstract description 57
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 230000005669 field effect Effects 0.000 claims abstract description 34
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 34
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 13
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000005416 organic matter Substances 0.000 claims 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Nanotechnology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a graphene/hexagonal boron nitride heterojunction field effect transistor and a preparation method thereof, wherein a gate dielectric layer is prepared on a silicon substrate and comprises a silicon dioxide layer and a hexagonal boron nitride layer; preparing a graphene conductive groove on a gate dielectric layer, and finally preparing a drain electrode and a source electrode which are arranged at intervals on the graphene conductive groove to obtain the graphene/hexagonal boron nitride heterojunction field effect transistor; and hexagonal boron nitride is similar to graphene in structure, high in lattice matching degree, flat in surface and free of dangling bonds and charged impurities, so that the intrinsic performance of graphene is maintained, and the device performance is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a graphene/hexagonal boron nitride heterojunction field effect transistor and a preparation method thereof.
Background
Graphene is used as a carbon monoatomic layer material, and has the characteristics of high thermal conductivity, high saturation rate, flexibility and the like, and the electron mobility in a suspension state is as high as 100000cm < 2 >/V.s. At present, a graphene field effect transistor is generally formed on SiO 2 Preparation on substrate, siO 2 The substrate has low field effect mobility due to high surface roughness, charge and phonon scattering and the like, and has low current switching ratio due to the fact that the single-layer graphene band gap is zero and an effective barrier height cannot be established in a channel.
Disclosure of Invention
The invention aims to provide a graphene/hexagonal boron nitride heterojunction field effect transistor and a preparation method thereof, so as to overcome the defects of the prior art.
A preparation method of a graphene/hexagonal boron nitride heterojunction field effect transistor comprises the following steps:
s1, preparing a gate dielectric layer on a silicon substrate, wherein the gate dielectric layer comprises a silicon dioxide layer and a hexagonal boron nitride layer;
s2, preparing graphene conductive grooves on the gate dielectric layer, and finally preparing drain electrodes and source electrodes which are arranged at intervals on the graphene conductive grooves, so that the graphene/hexagonal boron nitride heterojunction field effect transistor can be obtained.
Preferably, before preparation, the silicon substrate is subjected to cleaning treatment to remove impurities on the surface of the silicon substrate, and then a gate dielectric layer is prepared on the surface of the silicon substrate.
Preferably, a silicon dioxide layer is prepared on the cleaned silicon substrate, then the surface of the silicon dioxide layer is cleaned, the organic pollution on the surface of the silicon dioxide layer is removed, and then the hexagonal boron nitride layer is arranged on the surface of the silicon dioxide layer to form a gate dielectric layer.
Preferably, acetone, alcohol and deionized water are adopted to clean the surface of the silicon dioxide layer in sequence so as to remove organic pollution on the surface of the silicon dioxide layer.
Preferably, the hexagonal boron nitride is peeled off and transferred to the surface of the silicon dioxide layer by adopting a mechanical peeling method.
Preferably, the silicon dioxide layer has a thickness of 300 nm and the hexagonal boron nitride layer has a thickness of 40 nm.
Preferably, the graphene conductive grooves are prepared from a single layer of graphene.
Preferably, the drain electrode and the source electrode are made of metallic titanium, pd, cr or Au.
A graphene/hexagonal boron nitride heterojunction field effect transistor comprises a silicon substrate, a gate dielectric layer and a graphene conductive groove which are sequentially arranged from bottom to top, wherein a drain electrode and a source electrode which are arranged at intervals are arranged on the graphene conductive groove.
Preferably, the gate dielectric layer comprises a silicon dioxide layer and a hexagonal boron nitride layer.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to a preparation method of a graphene/hexagonal boron nitride heterojunction field effect transistor, which comprises the steps of preparing a gate dielectric layer on a silicon substrate, wherein the gate dielectric layer comprises a silicon dioxide layer and a hexagonal boron nitride layer; preparing a graphene conductive groove on a gate dielectric layer, and finally preparing a drain electrode and a source electrode which are arranged at intervals on the graphene conductive groove to obtain the graphene/hexagonal boron nitride heterojunction field effect transistor; and hexagonal boron nitride is similar to graphene in structure, high in lattice matching degree, flat in surface and free of dangling bonds and charged impurities, so that the intrinsic performance of graphene is maintained, and the device performance is improved.
Drawings
Fig. 1 is a schematic flow chart of a field effect transistor manufacturing process in an embodiment of the invention.
Fig. 2 is a schematic diagram of a structure of a gate dielectric layer fabricated on a surface of a silicon substrate in an embodiment of the present invention.
FIG. 3 is a schematic diagram of a hexagonal boron nitride layer according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a graphene conductive trench preparation structure in an embodiment of the present invention.
Fig. 5 is a schematic diagram of a drain and source preparation structure according to an embodiment of the invention.
Fig. 6 is a schematic structural diagram of an output characteristic curve of a device with negative gate voltage in an embodiment of the present invention.
Fig. 7 is a schematic diagram of an output characteristic curve structure when the device applies a positive gate voltage in an embodiment of the present invention.
Fig. 8 is a schematic diagram of a transfer characteristic structure of a device according to an embodiment of the present invention.
In the figure, (1) is a silicon substrate; (2) is a silicon dioxide layer; (3) is a hexagonal boron nitride layer; (4) is a graphene conductive trench; (5) a drain electrode; (6) is the source.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1, the invention provides a preparation method of a Graphene/hexagonal boron nitride heterojunction field effect transistor, which comprises the following steps:
s1, preparing a gate dielectric layer on a silicon substrate (1), wherein the gate dielectric layer comprises a silicon dioxide layer (2) and a hexagonal boron nitride layer (3);
s2, preparing a graphene conductive groove (4) on the gate dielectric layer, and finally preparing a drain electrode (5) and a source electrode (6) which are arranged at intervals on the graphene conductive groove, so as to obtain the graphene/hexagonal boron nitride heterojunction field effect transistor.
The graphene/hexagonal boron nitride heterojunction field effect transistor prepared by the method comprises a silicon substrate, a gate dielectric layer and a graphene conductive groove which are sequentially arranged from bottom to top, wherein a drain electrode and a source electrode which are arranged at intervals are arranged on the graphene conductive groove.
Specifically, as shown in fig. 2, before preparation, cleaning the silicon substrate to remove impurities on the surface of the silicon substrate; and then preparing a gate dielectric layer on the surface of the silicon substrate.
Specifically, firstly preparing a silicon dioxide layer on a cleaned silicon substrate, then cleaning the surface of the silicon dioxide layer to remove the organic pollution on the surface of the silicon dioxide layer, and then arranging a hexagonal boron nitride layer on the surface of the silicon dioxide layer to form a gate dielectric layer.
Specifically, acetone, alcohol and deionized water are adopted to sequentially clean the surface of the silicon dioxide layer so as to remove organic pollution on the surface of the silicon dioxide layer, and then a mechanical stripping method is adopted to strip and transfer hexagonal boron nitride to the surface of the silicon dioxide layer.
In one embodiment of the present application, the silicon dioxide layer has a thickness of 300 nanometers and the hexagonal boron nitride layer has a thickness of 40 nanometers.
As shown in fig. 3, the application adopts a hexagonal boron nitride layer and a silicon dioxide layer as the back gate dielectric layer, which has a plurality of advantages; the hexagonal boron nitride has similar lattice structure with the graphene, is used as a two-dimensional layered material, has uniform surface, can maintain the original molecular structure and characteristics of the graphene, and reduces the influence of geometric deformation and minority carrier scattering caused by surface fluctuation; the chemical property of the hexagonal boron nitride is stable, and the surface of the hexagonal boron nitride has no dangling bond, so that the adsorption of impurities can be reduced; the hexagonal boron nitride surface has larger optical phonon energy, and can reduce heterojunction interface phonon-electron effect.
As shown in fig. 4, the graphene conductive groove is prepared by adopting single-layer graphene, wherein the single-layer graphene is of an atomically thin thickness, is used as a channel layer, is positioned on hexagonal boron nitride, and can maintain the original structure and property, so that higher mobility is realized.
As shown in fig. 5, the drain electrode and the source electrode are made of metal titanium, so that good ohmic contact can be formed with the graphene conductive groove, and other materials such as Pd, cr and Au, which can form good ohmic contact with graphene, can be selected. After the drain electrode and the source electrode are prepared, the structure diagram of the graphene/hexagonal boron nitride heterojunction field effect transistor provided by the invention can be obtained.
The source electrode of the obtained graphene/hexagonal boron nitride heterojunction field effect transistor device is grounded, and a certain voltage V is applied between the source electrode and the drain electrode DS Applying a certain voltage V between the grid sources GS By regulating and controlling V GS The change of the carrier concentration in the graphene channel is changed, and the channel current I is realized DS Thereby obtaining the field effect characteristics of the device and extracting relevant device parameters therefrom: field effect mobility, current switching ratio, etc.
The test results are shown in fig. 6 and 7, which are the measured device plus negative and positive gate voltages, respectivelyOutput characteristic curve with grid voltage V GS Increasing absolute value, source drain current I DS And also increases. Start when V DS Smaller, I DS Along with V DS Is rapidly increased with V DS Is increased by (I) DS To reach weak saturation, increase slowly, when V DS Continue to increase, I DS And increases rapidly. The reason for this characteristic is mainly that graphene lacks a band gap, an electric field cannot pinch off carriers in a channel, so that strong saturation characteristics do not exist in source-drain voltages, and carriers in the channel are converted from single polarity to bipolar by rising of the source-drain voltages.
As shown in FIG. 8, to measure the transfer characteristic of the device, it can be seen that I DS Along with V GS The increase of (1) decreases before increasing, which means that the carrier concentration in graphene decreases before increasing, which is determined by the energy band structure of graphene, and I DS With V DS And increases with increasing numbers of (c).
The output and transfer characteristic curves of the graphene field effect transistor are in accordance with the characteristics of the graphene field effect transistor, and the field effect mobility of 4526.2cm is calculated from the characteristics 2 The current switching ratio is 4.5, and the dirac point voltage is 18V.
According to the invention, a layer of hexagonal boron nitride is inserted between graphene and silicon dioxide, so that a field effect transistor is constructed. When the graphene is positioned on the hexagonal boron nitride, the band gap of the single-layer graphene can be opened due to the interaction between the graphene and the hexagonal boron nitride, so that the current switching ratio of the device is improved; and hexagonal boron nitride is similar to graphene in structure, high in lattice matching degree, flat in surface and free of dangling bonds and charged impurities, so that the intrinsic performance of graphene is maintained, and the device performance is improved.
Claims (10)
1. The preparation method of the graphene/hexagonal boron nitride heterojunction field effect transistor is characterized by comprising the following steps of:
s1, preparing a gate dielectric layer on a silicon substrate, wherein the gate dielectric layer comprises a silicon dioxide layer and a hexagonal boron nitride layer;
s2, preparing graphene conductive grooves on the gate dielectric layer, and finally preparing drain electrodes and source electrodes which are arranged at intervals on the graphene conductive grooves, so that the graphene/hexagonal boron nitride heterojunction field effect transistor can be obtained.
2. The method for preparing the graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 1, wherein the silicon substrate is subjected to cleaning treatment before preparation, impurities on the surface of the silicon substrate are removed, and then a gate dielectric layer is prepared on the surface of the silicon substrate.
3. The method for preparing the graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 1, wherein a silicon dioxide layer is prepared on a cleaned silicon substrate, then cleaning treatment is carried out on the surface of the silicon dioxide layer to remove organic matter pollution on the surface of the silicon dioxide layer, and then the hexagonal boron nitride layer is arranged on the surface of the silicon dioxide layer to form a gate dielectric layer.
4. The method for preparing the graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 3, wherein acetone, alcohol and deionized water are adopted to sequentially clean the surface of the silicon dioxide layer, so that organic matter pollution on the surface of the silicon dioxide layer is removed.
5. A method of fabricating a graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 3, wherein mechanical stripping is employed to transfer hexagonal boron nitride to the surface of the silicon dioxide layer.
6. The method of manufacturing a graphene/hexagonal boron nitride heterojunction field effect transistor of claim 1, wherein the silicon dioxide layer is 300 nm thick and the hexagonal boron nitride layer is 40 nm thick.
7. The method for preparing the graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 1, wherein the graphene conductive groove is prepared by single-layer graphene.
8. The method for preparing the graphene/hexagonal boron nitride heterojunction field effect transistor according to claim 1, wherein the drain electrode and the source electrode are made of metallic titanium, pd, cr or Au.
9. The graphene/hexagonal boron nitride heterojunction field effect transistor prepared based on the method of claim 1 is characterized by comprising a silicon substrate, a gate dielectric layer and a graphene conductive groove which are sequentially arranged from bottom to top, wherein a drain electrode and a source electrode which are arranged at intervals are arranged on the graphene conductive groove.
10. The graphene/hexagonal boron nitride heterojunction field effect transistor of claim 9, wherein the gate dielectric layer comprises a silicon dioxide layer and a hexagonal boron nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310423830.4A CN116490042A (en) | 2023-04-19 | 2023-04-19 | Graphene/hexagonal boron nitride heterojunction field effect transistor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310423830.4A CN116490042A (en) | 2023-04-19 | 2023-04-19 | Graphene/hexagonal boron nitride heterojunction field effect transistor and preparation method thereof |
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| CN116490042A true CN116490042A (en) | 2023-07-25 |
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