CN116455377A - Switch array driving circuit - Google Patents
Switch array driving circuit Download PDFInfo
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- CN116455377A CN116455377A CN202310386046.0A CN202310386046A CN116455377A CN 116455377 A CN116455377 A CN 116455377A CN 202310386046 A CN202310386046 A CN 202310386046A CN 116455377 A CN116455377 A CN 116455377A
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- 230000000903 blocking effect Effects 0.000 claims abstract description 15
- 238000007599 discharging Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 239000011159 matrix material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a switch array driving circuit which comprises a voltage source, a switch circuit, a first signal source and a switch unit array, wherein the voltage source, the switch circuit and the switch unit array are sequentially connected in series, and the first signal source is connected with the switch circuit and is used for controlling the access and the disconnection of the switch circuit; a blocking element is arranged between the switch circuit and the switch unit array, and the blocking element and the switch circuit form a top diode structure; the switch unit array is composed of two N-type MOS tubes Q3, the grid electrode of each N-type MOS tube Q3 is connected with the switch circuit, the source electrode of each N-type MOS tube Q3 is connected with the grid electrode through the discharging module, and the drain electrodes of the two N-type MOS tubes Q3 are respectively connected with the bus terminal and the battery terminal. The invention does not need isolation devices, reduces the volume and reduces the cost. The diode, triode, resistor and capacitor are beneficial to system integration, the chip and modularization scheme is realized, and the control is simple, so that the reliability of the system is enhanced.
Description
Technical Field
The invention relates to the technical field of switch arrays, in particular to a switch array driving circuit.
Background
With the development of economy, batteries are one of the important clean energy sources in the society today. In a general application, each battery pack is formed by connecting a plurality of battery modules in series and in parallel, and each battery module is formed by connecting a plurality of battery cells in series and in parallel. The battery is affected by aging and the like, so that the problem of unequal electric quantity among the batteries is solved, the health degree and the practical use output capacity of the battery are seriously affected, and the balance of the batteries is important. The most common method of cell balancing is to use a switch array to select a cell to be discharged or charged for charging and discharging. Voltage isolation of the drive of the switch array is a big difficulty, and the drive of the power-balanced switch matrix network in the BMS requires floating ground, because the ground references for the drive of the top switch tubes in the switch matrix are all different.
The conventional approach is to use an isolated drive scheme. Most commonly, an isolation transformer driving mode and an optocoupler driving mode are adopted. This kind of way needs a comparatively complicated driving circuit design, and the device is many, still needs to keep apart, and is with high costs, and is bulky, difficult integrated.
Disclosure of Invention
The invention aims to provide a switch array driving circuit which overcomes the defects in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the application discloses a switch array driving circuit, which comprises a voltage source, a switch circuit, a first signal source and a switch unit array, wherein the voltage source, the switch circuit and the switch unit array are sequentially connected in series, and the first signal source is connected with the switch circuit and is used for controlling the access and the disconnection of the switch circuit;
a blocking element is arranged between the switch circuit and the switch unit array, and the blocking element and the switch circuit form a top diode structure;
the switch unit array is composed of two N-type MOS tubes Q3, the grid electrode of each N-type MOS tube Q3 is connected with the switch circuit, the source electrode of each N-type MOS tube Q3 is connected with the grid electrode through the discharging module, and the drain electrodes of the two N-type MOS tubes Q3 are respectively connected with the bus terminal and the battery terminal.
Preferably, the switching circuit comprises an N-type tube Q1 and a P-type tube Q2, and the voltage blocking element adopts a diode;
the N-type tube is an N-type MOS tube Q1 or an NPN triode Q1;
when the N-type MOS tube Q1 is adopted as the N-type MOS tube Q1, the grid electrode of the N-type MOS tube Q1 is connected with a first signal source, the source electrode of the N-type MOS tube Q1 is grounded, and the drain electrode of the N-type MOS tube Q1 is connected with the P-type tube Q2;
when the N-type transistor Q1 adopts an NPN triode Q1, the base electrode of the NPN triode Q1 is connected with a first signal source, the emitting stage of the NPN triode Q1 is grounded, and the collector electrode of the NPN triode Q1 is connected with the P-type transistor Q2;
the P-type transistor Q2 is a P-type MOS transistor Q2 or a PNP triode Q2;
when the P-type MOS tube Q2 is adopted as the P-type MOS tube Q2, the grid electrode of the P-type MOS tube Q2 is connected with the N-type tube Q1, the source electrode of the P-type MOS tube Q2 is connected with a voltage source, the drain electrode of the P-type MOS tube Q2 is connected with a diode to form a top diode structure, and the source electrode of the P-type MOS tube Q2 is connected with the grid electrode of the P-type MOS tube Q2 through a resistor R3;
the P-type tube Q2 adopts a PNP triode Q2; the base stage of the PNP triode Q2 is connected with the N-type tube Q1; the emitter of the PNP triode Q2 is connected with a voltage source, the collector of the PNP triode Q2 is connected with a diode to form a top diode structure, and the emitter of the PNP triode Q2 is connected with the base of the PNP triode Q through a resistor R3.
Preferably, the discharge module employs a resistor R1.
Preferably, the discharging module adopts a P-type MOS transistor Q9 or a PNP triode Q9; the voltage blocking element adopts a diode;
when the P-type MOS tube Q9 is adopted, the grid electrode and the source electrode of the P-type MOS tube Q9 are connected with a switch circuit through a diode, the source electrode of the P-type MOS tube Q9 is also connected with the grid electrode of the N-type MOS tube Q3, the grid electrode of the P-type MOS tube Q9 is also connected with the source electrode of the N-type MOS tube Q3 through a resistor R41, and the drain electrode of the P-type MOS tube Q9 is connected with the source electrode of the N-type MOS tube Q3 through a resistor R42;
when the PNP triode Q9 is adopted, the base electrode and the emitter electrode of the PNP triode Q9 are connected with a switch circuit through diodes, the source electrode of the PNP triode Q9 is also connected with the grid electrode of the N-type MOS tube Q3, the base electrode of the PNP triode Q9 is also connected with the source electrode of the N-type MOS tube Q3 through a resistor R41, and the collector electrode of the PNP triode Q9 is connected with the source electrode of the N-type MOS tube Q3 through a resistor R42.
Preferably, the voltage source adopts a direct current power supply or a power supply with soft start.
Preferably, the power supply with soft start is a push-pull circuit, and the push-pull circuit comprises a second signal source, an upper path and a lower path;
the upper path comprises an NPN triode Q5 and a PNP triode Q6, the base electrode of the NPN triode Q5 is connected with a second signal source, the emitter electrode of the NPN triode Q5 is grounded, the collector electrode of the NPN triode Q5 is connected with the base electrode of the PNP triode Q6, the emitter electrode of the PNP triode Q6 is connected with a power supply end VDD, and the collector electrode of the PNP triode Q6 is connected with a switch module;
the lower path comprises a PNP triode Q7 and an NPN triode Q8, wherein the base electrode of the PNP triode Q7 is connected with a second signal source, the emitting electrode of the PNP triode Q7 is connected with a power supply end VCC, the collecting electrode of the PNP triode Q7 is connected with the base electrode of the NPN triode Q8, the emitting electrode of the NPN triode Q8 is grounded, and the collecting electrode of the NPN triode Q8 is connected with a switch module.
The invention has the beneficial effects that:
1. the invention does not need isolation devices such as optocouplers, transformers and the like, and has the advantages of small volume and low cost.
2. The invention adopts the diode, triode, resistor and capacitor devices to be beneficial to system integration, realizes the chip and modularized scheme, and has simple control, thus the reliability of the system is enhanced.
The features and advantages of the present invention will be described in detail by way of example with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic circuit diagram of a switch array driver circuit of the present invention;
FIG. 2 is a schematic circuit diagram of a switching circuit of the present invention;
FIG. 3 is another schematic circuit diagram of the switching circuit of the present invention;
FIG. 4 is a schematic diagram of a voltage soft-feed of the present invention;
FIG. 5 is a schematic diagram of a push-pull circuit of the present invention;
FIG. 6 is a schematic circuit diagram of a discharge module of the present invention;
fig. 7 is a waveform diagram of a voltage soft-feed circuit of the power supply with soft-start of the present invention.
Fig. 8 is a waveform diagram of a voltage soft-feed circuit of a power supply without soft-start according to the present invention.
Detailed Description
The present invention will be further described in detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Referring to fig. 1, the switch array driving circuit of the present invention includes a voltage source, a switch circuit, a first signal source and a switch unit array, where the voltage source, the switch circuit and the switch unit array are sequentially connected in series, and the first signal source is connected with the switch circuit and used for controlling the on-off and the off-off of the switch circuit; a blocking element is arranged between the switch circuit and the switch unit array, and the blocking element and the switch circuit form a top diode structure; the switch unit array is composed of two N-type MOS tubes Q3, the grid electrode of the N-type MOS tube Q3 is connected with the switch circuit, the source electrode of the N-type MOS tube Q3 is connected with the grid electrode through the discharge module, and the drain electrodes of the two N-type MOS tubes Q3 are respectively connected with the bus terminal and the battery terminal;
referring to fig. 2, one embodiment of a switching circuit:
the voltage blocking element is a diode, the grid electrode of the N-type MOS tube Q1 is connected with a first signal source, the source electrode of the N-type MOS tube Q1 is grounded, the drain electrode of the N-type MOS tube Q1 is connected with the grid electrode of the P-type MOS tube Q2, the source electrode of the P-type MOS tube Q2 is connected with a switching circuit, the drain electrode of the P-type MOS tube Q2 is connected with the diode to form a top diode structure, and the source electrode of the P-type MOS tube Q2 is connected with the grid electrode of the P-type MOS tube Q2 through a resistor R3.
Referring to fig. 3, another embodiment of the switching circuit:
the switching circuit comprises an NPN transistor Q1 and a PNP transistor Q2, the voltage blocking element adopts a diode, the base electrode of the NPN transistor Q1 is connected with a first signal source, the emitter electrode of the NPN transistor Q1 is grounded, the collector electrode of the NPN transistor Q1 is connected with the base electrode of the PNP transistor Q2, the emitter electrode of the PNP transistor Q2 is connected with the switching circuit, the collector electrode of the PNP transistor Q2 is connected with the diode to form a diode structure on top, and the emitter electrode of the PNP transistor Q2 is connected with the base electrode of the PNP transistor Q3 through a resistor.
In the two switch circuits, when the first signal source is high, the NMOS/NPN is conducted, the drain/collector is pulled down, the base of the grid/PNP of the PMOS is pulled down, the PMOS/PNP is conducted, and the VDD voltage is output to the grid of the switch array through the diode D1; the switch array leg is gated.
When the first signal source is low, the NMOS/NPN and the PMOS/PNP are turned off, the grid electrode and the source electrode of the switch array are discharged through resistors, the final voltage difference is 0, the bridge arm of the switch array is turned off, and meanwhile, the PMOS/PNP and the D1 form a diode string on the top, so that voltage isolation is realized. Or PNP tube between grid and source of switch array is turned on, grid source end voltage is discharged to near 0, and bridge arm of switch array is turned off.
The discharging module can be a resistor, such as a resistor R1 in FIG. 2 or FIG. 3, or a circuit, such as a P-type MOS transistor Q9 or PNP transistor Q9 shown in FIG. 6; the voltage blocking element adopts a diode;
when the P-type MOS tube Q9 is adopted, the grid electrode and the source electrode of the P-type MOS tube Q9 are connected with a switch circuit through a diode, the source electrode of the P-type MOS tube Q9 is also connected with the grid electrode of the N-type MOS tube Q3, the grid electrode of the P-type MOS tube Q9 is also connected with the source electrode of the N-type MOS tube Q3 through a resistor R41, and the drain electrode of the P-type MOS tube Q9 is connected with the source electrode of the N-type MOS tube Q3 through a resistor R42;
when the PNP transistor Q9 is adopted, the base electrode and the emitter electrode of the PNP transistor Q9 are connected with a switch circuit through diodes, the source electrode of the PNP transistor Q9 is also connected with the grid electrode of the N-type MOS transistor Q3, the base electrode of the PNP transistor Q9 is also connected with the source electrode of the N-type MOS transistor Q3 through a resistor R41, and the collector electrode of the PNP transistor Q9 is connected with the source electrode of the N-type MOS transistor Q3 through a resistor R42.
The voltage soft-feed circuit can be a direct current power supply, or a power supply with soft start, such as a BUCK circuit, or a push-pull circuit, and FIG. 3 is a voltage soft-feed schematic diagram; referring to fig. 4, a schematic diagram of a push-pull circuit; the push-pull circuit comprises a second signal source, an upper path and a lower path; the upper path comprises an NPN triode Q5 and a PNP triode Q6, the base electrode of the NPN triode Q5 is connected with a second signal source, the emitter electrode of the NPN triode Q5 is grounded, the collector electrode of the NPN triode Q5 is connected with the base electrode of the PNP triode Q6, the emitter electrode of the PNP triode Q6 is connected with a power supply end VDD, and the collector electrode of the PNP triode Q6 is connected with a switch module; the lower path comprises a PNP transistor Q7 and an NPN transistor Q8, wherein the base electrode of the PNP transistor Q7 is connected with a second signal source, the emitter electrode of the PNP transistor Q7 is connected with a power supply end VCC, the collector electrode of the PNP transistor Q7 is connected with the base electrode of the NPN transistor Q8, the emitter electrode of the NPN transistor Q8 is grounded, and the collector electrode of the NPN transistor Q8 is connected with a switch module.
When the second signal source is high, the NPN triode and the PNP triode of the upper channel are conducted, and the Vdd voltage is output to the gate drive; when the second signal source is low, the PNP triode and the NPN triode of the lower channel are conducted, and the gate driving voltage falls back to the ground.
When the voltage soft-giving circuit is adopted, the second signal source is pulled up slower than the first signal source and is pulled down earlier than the first signal source; this can avoid an unnecessary large current change rate due to parasitic capacitance (refer to suppression of current pulses due to parasitic capacitance).
Referring to fig. 7 and 8, a waveform diagram of a voltage soft-feed circuit of a power supply with soft start and a waveform diagram of a voltage soft-feed circuit of a power supply without soft start are shown, respectively;
the foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, or alternatives falling within the spirit and principles of the invention.
Claims (6)
1. A switch array drive circuit, characterized by: the switching device comprises a voltage source, a switching circuit, a first signal source and a switching unit array, wherein the voltage source, the switching circuit and the switching unit array are sequentially connected in series, and the first signal source is connected with the switching circuit and is used for controlling the switching circuit to be switched on and switched off;
a blocking element is arranged between the switch circuit and the switch unit array, and the blocking element and the switch circuit form a top diode structure;
the switch unit array is composed of two N-type MOS tubes Q3, the grid electrode of each N-type MOS tube Q3 is connected with the switch circuit, the source electrode of each N-type MOS tube Q3 is connected with the grid electrode through the discharging module, and the drain electrodes of the two N-type MOS tubes Q3 are respectively connected with the bus terminal and the battery terminal.
2. A switch array driver circuit as claimed in claim 1, wherein: the switching circuit comprises an N-type tube Q1 and a P-type tube Q2, and the voltage blocking element adopts a diode;
the N-type tube is an N-type MOS tube Q1 or an NPN triode Q1;
when the N-type MOS tube Q1 is adopted as the N-type MOS tube Q1, the grid electrode of the N-type MOS tube Q1 is connected with a first signal source, the source electrode of the N-type MOS tube Q1 is grounded, and the drain electrode of the N-type MOS tube Q1 is connected with the P-type tube Q2;
when the N-type transistor Q1 adopts an NPN triode Q1, the base electrode of the NPN triode Q1 is connected with a first signal source, the emitting stage of the NPN triode Q1 is grounded, and the collector electrode of the NPN triode Q1 is connected with the P-type transistor Q2;
the P-type transistor Q2 is a P-type MOS transistor Q2 or a PNP triode Q2;
when the P-type MOS tube Q2 is adopted as the P-type MOS tube Q2, the grid electrode of the P-type MOS tube Q2 is connected with the N-type tube Q1, the source electrode of the P-type MOS tube Q2 is connected with a voltage source, the drain electrode of the P-type MOS tube Q2 is connected with a diode to form a top diode structure, and the source electrode of the P-type MOS tube Q2 is connected with the grid electrode of the P-type MOS tube Q2 through a resistor R3;
the P-type tube Q2 adopts a PNP triode Q2; the base stage of the PNP triode Q2 is connected with the N-type tube Q1; the emitter of the PNP triode Q2 is connected with a voltage source, the collector of the PNP triode Q2 is connected with a diode to form a top diode structure, and the emitter of the PNP triode Q2 is connected with the base of the PNP triode Q through a resistor R3.
3. A switch array driver circuit as claimed in claim 1, wherein: the discharging module adopts a resistor R1.
4. A switch array driver circuit as claimed in claim 1, wherein: the discharging module adopts a P-type MOS transistor Q9 or a PNP triode Q9; the voltage blocking element adopts a diode;
when the P-type MOS tube Q9 is adopted, the grid electrode and the source electrode of the P-type MOS tube Q9 are connected with a switch circuit through a diode, the source electrode of the P-type MOS tube Q9 is also connected with the grid electrode of the N-type MOS tube Q3, the grid electrode of the P-type MOS tube Q9 is also connected with the source electrode of the N-type MOS tube Q3 through a resistor R41, and the drain electrode of the P-type MOS tube Q9 is connected with the source electrode of the N-type MOS tube Q3 through a resistor R42;
when the PNP triode Q9 is adopted, the base electrode and the emitter electrode of the PNP triode Q9 are connected with a switch circuit through diodes, the source electrode of the PNP triode Q9 is also connected with the grid electrode of the N-type MOS tube Q3, the base electrode of the PNP triode Q9 is also connected with the source electrode of the N-type MOS tube Q3 through a resistor R41, and the collector electrode of the PNP triode Q9 is connected with the source electrode of the N-type MOS tube Q3 through a resistor R42.
5. A switch array driver circuit as claimed in claim 1, wherein: the voltage source adopts a direct current power supply or a power supply with soft start.
6. The switch array driver circuit of claim 5, wherein: the power supply with soft start is a push-pull circuit, and the push-pull circuit comprises a second signal source, an upper path and a lower path;
the upper path comprises an NPN triode Q5 and a PNP triode Q6, the base electrode of the NPN triode Q5 is connected with a second signal source, the emitter electrode of the NPN triode Q5 is grounded, the collector electrode of the NPN triode Q5 is connected with the base electrode of the PNP triode Q6, the emitter electrode of the PNP triode Q6 is connected with a power supply end VDD, and the collector electrode of the PNP triode Q6 is connected with a switch module;
the lower path comprises a PNP triode Q7 and an NPN triode Q8, wherein the base electrode of the PNP triode Q7 is connected with a second signal source, the emitting electrode of the PNP triode Q7 is connected with a power supply end VCC, the collecting electrode of the PNP triode Q7 is connected with the base electrode of the NPN triode Q8, the emitting electrode of the NPN triode Q8 is grounded, and the collecting electrode of the NPN triode Q8 is connected with a switch module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310386046.0A CN116455377A (en) | 2023-04-12 | 2023-04-12 | Switch array driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310386046.0A CN116455377A (en) | 2023-04-12 | 2023-04-12 | Switch array driving circuit |
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| Publication Number | Publication Date |
|---|---|
| CN116455377A true CN116455377A (en) | 2023-07-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310386046.0A Pending CN116455377A (en) | 2023-04-12 | 2023-04-12 | Switch array driving circuit |
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| CN (1) | CN116455377A (en) |
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| US20160190379A1 (en) * | 2014-12-26 | 2016-06-30 | Denso Wave Incorporated | Signal output circuit |
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| CN207766002U (en) * | 2018-01-17 | 2018-08-24 | 江苏金帆电源科技有限公司 | A kind of output control circuit of Battery formation power supply |
| CN109120251A (en) * | 2017-06-22 | 2019-01-01 | 付允念 | A kind of the MOS switch driving circuit and its array of series battery cells management system |
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| CN200976577Y (en) * | 2006-11-29 | 2007-11-14 | 青岛海信电器股份有限公司 | MOS tube driving circuit and television set having the same |
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| CN105446208A (en) * | 2014-10-17 | 2016-03-30 | 万向A一二三***有限公司 | Switch array circuit capable of being connected with cells at different positions in switching manner |
| US20160190379A1 (en) * | 2014-12-26 | 2016-06-30 | Denso Wave Incorporated | Signal output circuit |
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| CN206851088U (en) * | 2017-06-02 | 2018-01-05 | 浙江阳光美加照明有限公司 | A kind of LED linear double voltage driving circuit and driving power |
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| CN109552398A (en) * | 2017-09-26 | 2019-04-02 | 比亚迪股份有限公司 | Control device, system and the vehicle of rear-wheel slave steering system |
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