CN116453455B - Pixel multiplexing method, data transmission system and display screen control system and method - Google Patents
Pixel multiplexing method, data transmission system and display screen control system and method Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The application relates to the technical field of pixel multiplication display, in particular to a pixel multiplexing method, a data transmission system and a display screen control system and method, which solve the problem of color distortion of sharp edges under the traditional pixel multiplication rendering algorithm. The pixel multiplexing method based on pixel multiplication arrangement comprises the following steps: two adjacent sub-pixels in the same row are separated by a basic unit, the sub-pixels in the same column are staggered by half a basic unit in the horizontal direction, the adjacent sub-pixels in any direction are all of different primary colors, and the pixel multiplexing method specifically comprises the following steps: taking a parallelogram structure formed by four sub-pixels of two adjacent columns in every two adjacent rows in the pixel multiplication arrangement structure as a display unit, enabling each sub-pixel to be multiplexed by four display units, and enabling all the display units to form a matrix display structure; and determining the mapping relation between each sub-pixel and the pixel point of the image source, wherein the display data of each sub-pixel is the average value of the display data of the corresponding sub-pixels corresponding to four pixel points in the image source.
Description
Technical Field
The application relates to the technical field of pixel multiplication display, in particular to a pixel multiplexing method, a data transmission system, a display screen control system and a display screen control method.
Background
The pixel multiplexing technology is an important technology in the technology of improving the perceived resolution of an LED display, and the lamp points of each sub-pixel are shared by a plurality of surrounding virtual pixel points, so that the method similar to the method of smoothly filtering and then downsampling original video image data is realized, and the image beyond the physical resolution of the display is displayed on the LED display, so that the perceived resolution is increased, and the display effect is enhanced.
In the implementation process of pixel multiplexing, data processing is an indispensable process, and the original data volume is reduced to realize that video source images with the same resolution are displayed on display modules with fewer light points in the same area. The method of implementing the pixel multiplication algorithm at the front end of the transmitting card saves bandwidth on both transmission and reception, and the carrying capacity of the transmitting card and the data processing capacity of the receiving card, which result in lower implementation costs for the pixel multiplication technique than the method implemented on the receiving card. However, whether the pixel multiplication technique is implemented on the front end of the transmitting card or on the receiving card, the pixel arrangement and multiplexing algorithm (not weighted average) can cause the color distortion problem of sharp edges, and the worst is that a single pixel straight line can directly change color.
For example, in the chinese patent document "data transmission system, control system, method and apparatus for pixel multiplication display screen" (publication No. CN115132133a, publication No. 2022, 9/30/9) discloses a pixel multiplication data processing step of a display screen adopting a GB-BR-RG pixel arrangement mode, dividing a repeatable pixel element GB-BR-RG into two BGR pixel data, and outputting 24bit data of a BGR-888 format at an output end in a real pixel mode without changing the pixel data format before and after processing, so that a receiving card achieves a display effect of a virtual pixel in a real pixel display mode, thereby saving the data processing capability of the receiving card. However, due to the scattered arrangement of the sub-pixels and the corresponding multiplexing algorithm, the display screen has the problem of sharp edge color distortion during display, and the display effect, especially the vertical edge of the high-frequency signal, is seriously affected. Conventional multiplexing algorithms, such as shown in fig. 1, may appear purple, yellow, or cyan in pixel arrangement and conventional multiplexing rules, such as black single pixel vertical lines on a white background. As shown in fig. 2, A, B and C correspond to three single-pixel black vertical lines on the white background, wherein the vertical line a is centered on the green sub-pixel, and the red Lan Ya pixels on two sides of the green sub-pixel, which is supposed to be 0 brightness value, are half-white brightness values due to the addition of the multiplexing algorithm, so that the vertical line a of the single-pixel, which is supposed to be black, is displayed as purple. The vertical lines B and C are similarly shown as yellow and cyan, respectively.
In summary, the GB-BR-RG pixel arrangement display screen adopting the traditional multiplication rendering algorithm has the problem that the color distortion occurs at the sharp edge in the display picture, and the display effect is seriously affected.
Disclosure of Invention
In order to solve the problem of sharp edge color distortion in GB-BR-RG pixel arrangement display under the traditional pixel multiplication rendering algorithm, the application provides a novel pixel multiplexing method, a data transmission system and a display screen control system and method.
The technical scheme of the application is as follows:
a pixel multiplexing method based on pixel multiplication arrangement, the pixel multiplication arrangement specifically comprises: two adjacent sub-pixels in the same row are separated by a basic unit, the sub-pixels in the same column are staggered by half a basic unit in the horizontal direction, the adjacent sub-pixels in any direction are all of different primary colors, and the pixel multiplexing method specifically comprises the following steps:
taking a parallelogram structure formed by four sub-pixels of two adjacent columns in every two adjacent rows in the pixel multiplication arrangement structure as a display unit, enabling each sub-pixel to be multiplexed by four display units, and enabling all the display units to form a matrix display structure;
and determining the mapping relation between each sub-pixel and the pixel point of the image source, wherein the display data of each sub-pixel is the average value of the display data of the corresponding sub-pixels corresponding to four pixel points in the image source.
The application also provides a data transmission system of the pixel multiplication display screen, which adopts the pixel multiplexing method based on the pixel multiplication arrangement, and comprises an upper computer, an HDMI decoding chip, an HDMI encoding chip, a data processing module and a transmitting card, wherein the upper computer is used for transmitting HDMI video signals to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit and a data processing unit, wherein the pixel multiplication data processing unit is used for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit internally comprises two FIFO memories and 9 data registers, and is used for dynamically storing and reading out data after each frame of data arrives to form a data matrix, calculating the data of the 9 registers according to a pixel multiplication data processing algorithm to obtain monochromatic pixel data, transmitting the calculated data to an HDMI coding chip, recoding the data into HDMI video signals and outputting the HDMI video signals to the transmitting card.
Preferably, the data processing module further includes a DDR memory chip for frame-buffering the processed data, and a synchronization signal generating unit for generating a line synchronization signal, a field synchronization signal, and an enable signal required for displaying the data, and synchronizing the data read out from the DDR memory chip with the generated signal.
Preferably, the decoded data includes a line synchronization signal, a field synchronization signal, an enable signal, and RGB gray data.
Preferably, the data processing module is an FPGA processor.
The application also provides a display screen control system, which comprises a receiving card, a driving IC and the data transmission system, wherein the receiving card is used for receiving the effective video signals which are divided into boxes by the sending card in the data transmission system, and transmitting the effective video signals to the driving IC to drive the display screen to display after electro-optical conversion and brightness correction.
The application also provides a display screen control method, which is applied to the display screen control system, and comprises the following steps:
s1, an upper computer sends an HDMI video signal to be displayed to an HDMI decoding chip;
s2, decoding the HDMI video signal by the HDMI decoding chip, wherein the decoded data comprise a row synchronous signal, a field synchronous signal, an enabling signal and RGB gray scale data, and then sending the data to the data processing module;
s3, pixel multiplication data processing units in the data processing module perform pixel multiplication data processing on the data, the processed data is subjected to frame buffering through the DDR memory chip, and then the processed data is sent to the HDMI coding chip to be recoded into HDMI video signals and output to the sending card;
s4, decoding, intercepting and binning the video data by the transmitting card, after intercepting the effective pixel data, packaging and transmitting the effective video signal into bins to the receiving card, and then performing electro-optical conversion and brightness correction on the data by the receiving card and transmitting the data to the driving IC to drive the display screen to display.
Preferably, before the pixel multiplication data processing, gamma conversion is performed on the 24-bit RGB gray scale data, and the RGB brightness data is developed; after the pixel multiplication data processing, the processed brightness data is subjected to gamma inverse transformation to restore the gray data.
Preferably, the specific steps of the pixel multiplication data processing are as follows:
SS1, after a frame of data arrives, firstly using a FIFO memory to temporarily store the data of the first line, storing the second line of data in the second FIFO memory when the second line of data is input, simultaneously reading the data of the first line buffered in the first FIFO memory, and storing the data of the current time and the last clock cycle of the current two lines by using 6 registers;
when SS2 and third data come, 9 registers are used for storing the data of the current moment of the read-out and current input data of the two FIFO memories and the data of the last clock period and the last clock period to form a 3 multiplied by 3 data window;
SS3, setting a calculating operation sign signal, pulling up the calculating operation sign signal when the column counter of the even number row counts to 3k-2 and 3k-1 (k is a positive integer), carrying out calculating operation and assignment operation, pulling down the calculating operation sign signal at the rest moments, and assigning 0 of the corresponding bit number to output data.
Preferably, the resolution of the pixel multiplication display screen is m×n, after a frame of data arrives, the rows and columns are counted according to the enable signal, when the enable signal is 1, an operation is added to the column counter when each pixel clock rises, an operation is added to the row counter when the column is full of m-1, the column counter is reset to zero, the same operation is performed on the next row, and when the row counter is full of n-1, the counter is reset to zero, which means that the frame of data processing is finished.
Compared with the prior art, the application has the following specific beneficial effects:
aiming at the problem of color lines in the traditional pixel multiplication scheme under GB-BR-RG arrangement, the application provides a novel pixel multiplexing method, which can effectively eliminate or even lighten color edges, solve the problem of color cast of display edges in various scenes and optimize the problem of color edges of high-frequency information such as characters; the data transmission system is matched, so that the color edge display problem can be solved, the transmission bandwidth between the sending card and the receiving card, the tape load of the sending card and the data processing capacity of the receiving card can be saved, the cost is greatly reduced, the short circuit risk is reduced, and the device is easy to maintain.
Drawings
FIG. 1 is a conventional pixel multiplexing method of GB-BR-RG arrangement;
FIG. 2 is a schematic diagram of the principle of single pixel vertical line color non-convergence under the conventional pixel multiplexing method;
fig. 3 is a schematic diagram of a pixel multiplexing method under the arrangement of GB-BR-RG provided by the present application;
FIG. 4 is a schematic diagram of a single pixel line rendered using the pixel multiplexing method of the present application;
fig. 5 is a schematic diagram of the data processing method described in embodiment 9.
Detailed Description
In order to make the technical solution of the present application clearer, the technical solution of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the present application, and it should be noted that the following embodiments are only used for better understanding of the technical solution of the present application, and should not be construed as limiting the present application.
Example 1.
The embodiment provides a pixel multiplexing method based on pixel multiplication arrangement, wherein the pixel multiplication arrangement specifically comprises the following steps: two adjacent sub-pixels in the same row are separated by a basic unit, the sub-pixels in the same column are staggered by half a basic unit in the horizontal direction, the adjacent sub-pixels in any direction are all of different primary colors, and the pixel multiplexing method specifically comprises the following steps:
taking a parallelogram structure formed by four sub-pixels of two adjacent columns in every two adjacent rows in the pixel multiplication arrangement structure as a display unit, so that each sub-pixel is multiplexed by four display units, and all the display units form a matrix display structure, as shown in fig. 3;
and determining the mapping relation between each sub-pixel and the pixel point of the image source, wherein the display data of each sub-pixel is the average value of the display data of the corresponding sub-pixels corresponding to four pixel points in the image source.
The vertical single pixel line rendered by the multiplexing method in this embodiment is shown in fig. 4, in this embodiment, four sub-pixels form a multiplexing display unit, which is different from the conventional multiplexing unit formed by three sub-pixels, in the multiplexing mode in this embodiment, the brightness of the sub-pixels in the vertical single pixel line is uniform; and the width of the vertical edge of the single pixel line or the graph is increased by one sub-pixel compared with the traditional multiplexing mode, so that the distance between display units at two sides of the single pixel line is increased, the phenomenon that the colors are not converged can be greatly weakened according to the space color mixing principle, the problem that the color lines are brought by the traditional algorithm is solved, and the viewing of the display screen is improved.
Example 2.
The embodiment provides a data transmission system of a pixel multiplication display screen, wherein the pixel multiplication display screen applies the pixel multiplexing method based on pixel multiplication arrangement of the embodiment 1, the data transmission system comprises an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a transmitting card, and the upper computer is used for transmitting HDMI video signals to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit and a data processing unit, wherein the pixel multiplication data processing unit is used for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit internally comprises two FIFO memories and 9 data registers, and is used for dynamically storing and reading out data after each frame of data arrives to form a data matrix, calculating monochromatic pixel data according to a pixel multiplication data processing algorithm, transmitting the data to an HDMI coding chip, recoding the data into HDMI video signals and outputting the HDMI video signals to a transmitting card.
The pixel multiplexing method described in embodiment 1 is applied to the data transmission system of the pixel multiplication display screen, so that the problem of color lines caused by a traditional algorithm is solved, virtual processing of data is realized on a transmission path between an upper computer and a transmitting card, transmission bandwidth between the transmitting card and a receiving card is saved, carrying capacity of the transmitting card and data processing capacity of the receiving card are reduced, and requirements of the system on the transmitting card and the receiving card are reduced, so that cost is greatly reduced; the number of wires between the sending card and the receiving card in the corresponding display screen control device is reduced, so that the wires inside the device box body are regular, the short circuit risk is reduced, and the device is easy to maintain.
Example 3.
This embodiment is a further illustration of embodiment 2, where the data processing module further includes a DDR memory chip for frame-buffering the processed data, and a synchronization signal generating unit for generating a line synchronization signal, a field synchronization signal, and an enable signal required for displaying the data, and synchronizing the data read out from the DDR memory chip with the generated signal.
Example 4.
This embodiment is a further illustration of embodiment 2, wherein the decoded data includes a line synchronization signal, a field synchronization signal, an enable signal, and RGB gray scale data.
Example 5.
This embodiment is further illustrative of embodiment 2, wherein the data processing module is an FPGA processor.
Example 6.
The embodiment provides a display screen control system, which comprises a receiving card, a driving IC and the data transmission system as described in any one of embodiments 2 to 5, wherein the receiving card is used for receiving an effective video signal after being divided into boxes by a sending card in the data transmission system, and transmitting the effective video signal to the driving IC for driving the display screen to display after electro-optical conversion and brightness correction.
Example 7.
The present embodiment provides a display screen control method, which applies the display screen control system according to embodiment 6, and includes the following steps:
s1, an upper computer sends an HDMI video signal to be displayed to an HDMI decoding chip;
s2, decoding the HDMI video signal by the HDMI decoding chip, wherein the decoded data comprise a row synchronous signal, a field synchronous signal, an enabling signal and RGB gray scale data, and then sending the data to the data processing module;
s3, performing pixel multiplication data processing on the data by a pixel multiplication data processing unit in the data processing module, wherein the effective data amount of one frame of data obtained after the processing is 1/3 of that before the processing, but the effective data amount is loosely distributed in each frame of image, and the invalid data part is assigned with 0;
in order to centralize scattered image data and truly realize data reduction, the processed data is subjected to frame buffering through a DDR memory chip, so that 1/3 of effective data quantity is buffered into DDR, the resolution is 1080P for example, when DDR3 is read, a synchronous signal generating unit is utilized to generate synchronous signals (line field synchronization and enabling) needed by display data, then column counting is carried out according to the enabling signals, a read enabling signal of a DDR read FIFO with the front 1280 columns and the front 540 lines is generated, 1/3 frame data obtained through processing is read out in the time and is synchronous with the synchronous signals generated by the synchronous signal generating unit, signals at other moments in one frame, namely invalid signals, are still assigned to 0, and then the signals are sent to an HDMI coding chip to be recoded into HDMI video signals and output to a transmitting card;
s4, decoding, intercepting and binning the video data by the transmitting card, after intercepting the effective pixel data, packaging and transmitting the effective video signal into bins to the receiving card, and then performing electro-optical conversion and brightness correction on the data by the receiving card and transmitting the data to the driving IC to drive the display screen to display.
Example 8.
This embodiment is further illustrative of embodiment 7, wherein the gamma conversion is performed on 24bit RGB gray-scale data to develop RGB luminance data prior to pixel-wise data processing; after the pixel multiplication data processing, the processed brightness data is subjected to gamma inverse transformation to restore the gray data.
The number of bits of the RGB luminance data developed in this embodiment is determined by the Gamma table of the LED display terminal, and the Gamma table can be changed differently for different displays, and the number of bits after development is also changed, usually between 36 bits and 66 bits.
Example 9.
This embodiment is a further illustration of embodiment 8, wherein the specific steps of the pixel multiplication data processing are:
SS1, after a frame of data arrives, firstly using a FIFO memory to temporarily store the data of the first line, storing the second line of data in the second FIFO memory when the second line of data is input, simultaneously reading the data of the first line buffered in the first FIFO memory, and storing the data of the current time and the last clock cycle of the current two lines by using 6 registers;
when SS2 and third data come, 9 registers are used for storing the data of the current moment of the read-out and current input data of the two FIFO memories and the data of the last clock period and the last clock period to form a 3 multiplied by 3 data window;
SS3, setting a calculating operation sign signal, pulling up the calculating operation sign signal when the column counter of the even number row counts to 3k-2 and 3k-1 (k is a positive integer), carrying out calculating operation and assignment operation, pulling down the calculating operation sign signal at the rest moments, and assigning 0 of the corresponding bit number to output data.
The data processing method provided in this embodiment is illustrated in detail below. As shown in fig. 5, for the sub-pixel in (1), the R sub-pixel in the upper left corner only needs R data in the video source pixel 11, the B sub-pixel needs the average value of B data of the pixels 11 and 21, and the G sub-pixel needs the average value of G data of the pixels 11 and 12, so the video source data needed by the three sub-pixel points is four data of the video source pixel 11, 12, 21 and 22, after one line is buffered, the data in the 4 registers of the existing data are calculated while the data in the first line in the FIFO1 is read out, and then assigned to the output, so as to obtain RGB data in (1) of the pixel multiplication display;
for the sub-pixel in (2), the red component of the four data of 11, 12, 21 and 22 is required to be averaged by the R sub-pixel in the lower left corner, the B component of the two video source pixel bits of 12 and 13 is required to be averaged by the B sub-pixel in the upper side, the G component of the four video source pixel bit data of 12, 13, 22 and 23 is required to be averaged by the G sub-pixel in the lower right corner, so that the video source data required by the three sub-pixel points are six data of 11, 12, 13, 21, 22 and 23, after one line is cached, the data in the 6 registers of the existing data are calculated by the clock cycle of the arrival of the data in the third column of the second line while the data in the first line in the FIFO1 is read out, and then assigned to the output, so that the RGB data in (2) of the pixel multiplication display is obtained;
for the sub-pixel in (3), the red component of the four data of the R sub-pixel at the lower left corner needs to be averaged with the red component of the four data of 31, 32, 41 and 42, the B sub-pixel at the upper side needs to be averaged with the B component of the four video source pixel bits of 22, 23, 32 and 33, and the G sub-pixel at the lower right corner needs to be averaged with the G component of the four video source pixel bit data of 32, 33, 42 and 43, so that the video source data needed by the three sub-pixel points are eight data of 22, 23, 31, 32, 33, 41, 42 and 43, after the FIFO1 and the FIFO2 respectively buffer the 2 nd line of data and the 3 rd line of data, the clock period of the data of the fourth line and the third line of data arrives at the same time when the data of the FIFO1 and the FIFO2 nd line of data is read, the data of the 9 registers of the existing data is calculated, and then the data of the third line of the data is assigned to the output, so as to obtain the RGB data in the pixel multiplication display (3);
and so on, when each calculation flag signal is at a high level, only the numerical values in the 9 registers at the moment need to be correspondingly processed according to the algorithm of the embodiment, then the data obtained by processing are assigned and output until the last column data of the last row arrives, the calculation of one frame of data is finished, and the function of the data processing module is completed.
Example 10.
This embodiment is further illustrative of embodiment 9, where the resolution of the pixel multiplication display screen is m×n, after a frame of data arrives, the rows and columns are counted according to the enable signal, when the enable signal is 1, an operation is performed to increment the column counter every pixel clock, when the column is m-1, an operation is performed to increment the column counter, and the column counter is zeroed, representing the end of a row of data processing, and the same operation is performed for the next row, and when the column counter is n-1, the counter is all zeroed, representing the end of a frame of data processing.
Claims (5)
1. The control method is characterized in that the control method adopts a display screen control system, the display screen control system comprises a receiving card, a driving IC and a data transmission system of a pixel multiplication display screen, the receiving card is used for receiving an effective video signal which is divided into boxes by a sending card in the data transmission system, and the effective video signal is transmitted to the driving IC to drive the display screen to display after electro-optical conversion and brightness correction;
the pixel multiplication display screen applies a pixel multiplexing method based on pixel multiplication arrangement, and the pixel multiplication arrangement is specifically as follows: two adjacent sub-pixels in the same row are separated by a basic unit, the sub-pixels in the same column are staggered by half a basic unit in the horizontal direction, and the adjacent sub-pixels in any direction are all of different primary colors, and the pixel multiplexing method is characterized in that:
taking a parallelogram structure formed by four sub-pixels of two adjacent columns in every two adjacent rows in the pixel multiplication arrangement structure as a display unit, enabling each sub-pixel to be multiplexed by four display units, and enabling all the display units to form a matrix display structure; determining the mapping relation between each sub-pixel and the pixel point of the image source, wherein the display data of each sub-pixel is the average value of the display data of the corresponding sub-pixels corresponding to four pixel points in the image source;
the data transmission system comprises an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a transmitting card, wherein the upper computer is used for transmitting an HDMI video signal to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit and a data processing unit, wherein the pixel multiplication data processing unit is used for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit internally comprises two FIFO memories and 9 data registers, and is used for dynamically storing and reading out data after each frame of data arrives to form a data matrix, calculating the data of the 9 registers according to a pixel multiplication data processing algorithm to obtain monochromatic pixel data, transmitting the monochromatic pixel data to an HDMI coding chip, recoding the monochromatic pixel data into HDMI video signals and outputting the HDMI video signals to the transmitting card;
the control method comprises the following steps:
s1, an upper computer sends an HDMI video signal to be displayed to an HDMI decoding chip;
s2, decoding the HDMI video signal by the HDMI decoding chip, wherein the decoded data comprise a row synchronous signal, a field synchronous signal, an enabling signal and RGB gray scale data, and then sending the data to the data processing module; before pixel multiplication data processing, gamma conversion is carried out on 24bit RGB gray scale data, and the RGB gray scale data are unfolded into RGB brightness data;
s3, pixel multiplication data processing units in the data processing module perform pixel multiplication data processing on the data, after the pixel multiplication data processing, gamma inverse transformation is performed on the processed brightness data to recover gray data, the processed data is subjected to frame caching by a DDR (double data Rate) memory chip, and then the data is sent to an HDMI (high-definition multimedia interface) encoding chip to be recoded into HDMI video signals and output to a sending card;
s4, decoding, intercepting and binning the video data by the transmitting card, after intercepting the effective pixel data, binning and packaging the effective video signals and transmitting the effective video signals to the receiving card, and then performing electro-optical conversion and brightness correction on the data by the receiving card and transmitting the data to the driving IC to drive the display screen to display;
the specific steps of the pixel multiplication data processing are as follows:
SS1, after a frame of data arrives, firstly using a FIFO memory to temporarily store the data of the first line, storing the second line of data in the second FIFO memory when the second line of data is input, simultaneously reading the data of the first line buffered in the first FIFO memory, and storing the data of the current time and the last clock cycle of the current two lines by using 6 registers;
when SS2 and third data come, 9 registers are used for storing the data of the current moment of the read-out and current input data of the two FIFO memories and the data of the last clock period and the last clock period to form a 3 multiplied by 3 data window;
SS3, setting a calculating operation sign signal, pulling up the calculating operation sign signal when the column counter of the even number row counts to 3k-2 and 3k-1 (k is a positive integer), carrying out calculating operation and assignment operation, pulling down the calculating operation sign signal at the rest moments, and assigning 0 of the corresponding bit number to output data.
2. The display screen control method according to claim 1, wherein the data processing module further includes a DDR memory chip for frame-buffering the processed data, and a synchronization signal generating unit for generating a line synchronization signal, a field synchronization signal, and an enable signal required for displaying the data, and synchronizing the data read out from the DDR memory chip with the generated signal.
3. The display screen control method according to claim 1, wherein the decoded data includes a line synchronization signal, a field synchronization signal, an enable signal, and RGB gray scale data.
4. The display screen control method of claim 1, wherein the data processing module is an FPGA processor.
5. The method of claim 1, wherein the resolution of the pixel-multiplied display screen is m x n, the rows and columns are counted according to the enable signal after a frame of data arrives, the column counter is incremented each time the enable signal rises when the enable signal is 1, the row counter is incremented when the column is full of m-1, the column counter is zeroed, representing the end of a row of data processing, the same operation is performed for the next row, and the counter is all zeroed when the row counter is full of n-1, representing the end of a frame of data processing.
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| CN116913179A (en) * | 2023-09-13 | 2023-10-20 | 长春希达电子技术有限公司 | Arrangement structure of sub-pixels, virtual pixel structure and pixel multiplexing method |
| CN116959333B (en) * | 2023-09-19 | 2023-12-12 | 长春希达电子技术有限公司 | Display pixel arrangement structure, virtual pixel multiplexing mode and control method thereof |
| CN116959334B (en) * | 2023-09-21 | 2023-12-12 | 长春希达电子技术有限公司 | Arrangement structure of sub-pixels, virtual pixel structure and pixel multiplexing method |
| CN116974111B (en) * | 2023-09-22 | 2024-01-05 | 长春希达电子技术有限公司 | Triangular arrangement structure, calculation method thereof and display equipment |
| CN117037635A (en) * | 2023-10-08 | 2023-11-10 | 长春希达电子技术有限公司 | Arrangement structure of light emitting components and display control method |
| CN117058985B (en) * | 2023-10-12 | 2024-01-05 | 长春希达电子技术有限公司 | Arrangement structure, virtual multiplexing mode, control method and display device |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IN187262B (en) * | 1995-02-03 | 2002-03-16 | Koninkl Philips Electronics Nv | |
| CN102857758A (en) * | 2012-09-03 | 2013-01-02 | 上海算芯微电子有限公司 | Reusable pixel processing method and reusable video processing chip |
| KR101737437B1 (en) * | 2017-01-13 | 2017-05-19 | (주)동방데이타테크놀러지 | LED Display to improve the image quality and power saving according to the Gray Scale of the Video output section |
| CN113745271A (en) * | 2020-05-29 | 2021-12-03 | 华为技术有限公司 | Display panel and display device |
| CN114822375A (en) * | 2022-03-18 | 2022-07-29 | 长春希达电子技术有限公司 | Display panel virtual pixel multiplexing structure, control method and system |
| CN115132133A (en) * | 2022-08-31 | 2022-09-30 | 长春希达电子技术有限公司 | Data transmission system, control system, method and device of pixel multiplication display screen |
-
2023
- 2023-06-14 CN CN202310698580.5A patent/CN116453455B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IN187262B (en) * | 1995-02-03 | 2002-03-16 | Koninkl Philips Electronics Nv | |
| CN102857758A (en) * | 2012-09-03 | 2013-01-02 | 上海算芯微电子有限公司 | Reusable pixel processing method and reusable video processing chip |
| KR101737437B1 (en) * | 2017-01-13 | 2017-05-19 | (주)동방데이타테크놀러지 | LED Display to improve the image quality and power saving according to the Gray Scale of the Video output section |
| CN113745271A (en) * | 2020-05-29 | 2021-12-03 | 华为技术有限公司 | Display panel and display device |
| CN114822375A (en) * | 2022-03-18 | 2022-07-29 | 长春希达电子技术有限公司 | Display panel virtual pixel multiplexing structure, control method and system |
| CN115132133A (en) * | 2022-08-31 | 2022-09-30 | 长春希达电子技术有限公司 | Data transmission system, control system, method and device of pixel multiplication display screen |
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