CN115132133A - Data transmission system, control system, method and device of pixel multiplication display screen - Google Patents
Data transmission system, control system, method and device of pixel multiplication display screen Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
A data transmission system, a control system, a method and a device of a pixel multiplication display screen relate to the technical field of display control, solve the problem of data transmission bandwidth waste, and can be applied to the display control of the pixel multiplication display screen. The data transmission system comprises an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a sending card, wherein the upper computer sends an HDMI video signal to be displayed to the HDMI decoding chip; the HDMI decoding chip decodes the HDMI video signal and sends the decoded HDMI video signal to the data processing module; the data processing module performs pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit comprises two FIFO memories, the data are dynamically stored and read after each frame of data arrives to form a data matrix, monochrome pixel data are calculated according to a pixel multiplication data processing algorithm and are sent to an HDMI coding chip to be re-coded into an HDMI video signal, and the HDMI video signal is output to the sending card.
Description
Technical Field
The invention relates to the technical field of display control, in particular to a data transmission and control technology of a pixel multiplication display screen.
Background
Due to the characteristics of the LED chips, the current process technology is not enough to support the realization of a small chip size and a small dot pitch, which results in that the pixel density of the LED display is not constant all the time, and the LED display screen with the same pixel resolution ratio is difficult to realize the same size as the LCD and OLED screens. On the premise of not improving the physical pixel density of the display screen, the method for improving the perception resolution by using the pixel multiplexing technology becomes a feasible method. The sub-pixel multiplexing technology is that the light point of each sub-pixel is shared by a plurality of virtual pixel points around, and the method similar to the method of performing smooth filtering and then zooming on the original image is used for displaying the image exceeding the physical resolution of the display on the LED display so as to increase the perception resolution.
In the implementation process of pixel multiplexing, virtual pixel data processing is an indispensable process, and the original data volume is reduced to display a video source image on a smaller display module. The data processing of the existing pixel multiplexing technology is almost realized on a receiving card of an LED display system, so that the data is sent to a sending card without being changed at the front end, is sent to the receiving card after being separated by a box of the sending card, and is sent to a driving IC of an LED display to drive the LED display to display after being subjected to the data processing by the receiving card. Since the amount of processed data is scaled down, this way of processing data on the receiving card results in a waste of transmission bandwidth from the sending card to the receiving card, i.e. the transmission bandwidth from the sending card to the receiving card is required to be very wide, and the requirements on the data processing capacity of the sending card and the receiving card are very high. Correspondingly, the cost of the adopted sending card and the receiving card is high, more network ports are required to be arranged on the sending card and the receiving card, and the wiring in the box body of the control device is complex, so that the short circuit is easy and the maintenance is inconvenient.
Disclosure of Invention
The invention provides a data processing module of a pixel multiplication display screen, a data transmission system, a control system, a method and a device comprising the module, and aims to solve the problem that the transmission bandwidth is wasted due to a data transmission mode of the existing pixel multiplexing technology.
The technical scheme of the invention is as follows:
a data transmission system of a pixel multiplication display screen comprises an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a sending card, wherein the upper computer is used for sending an HDMI video signal to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit internally comprises two FIFO memories which are used for dynamically storing and reading data after each frame of data arrives to form a data matrix, then single-color pixel data is calculated according to a pixel multiplication data processing algorithm, and the data is sent to an HDMI coding chip to be recoded into an HDMI video signal and output to a sending card.
Preferably, the data processing module further includes a DDR3 memory chip, configured to perform frame buffering on the processed data.
Preferably, the data processing module further includes a synchronization signal generation unit for generating a line synchronization signal, a field synchronization signal, and an enable signal required for displaying data, and synchronizing data read out from the DDR3 memory chip with the generated signals.
Preferably, the decoded data includes a line sync signal, a field sync signal, an enable signal, and RGB gray data.
Preferably, the data processing module is an FPGA processor.
A pixel multiplication display screen control system comprises a receiving card, a driving IC and the data transmission system, wherein the receiving card is used for receiving effective video signals after the effective video signals are separated by a sending card in the data transmission system and then is transmitted to the driving IC to drive a display screen to display.
A pixel multiplication display screen control method, applying the pixel multiplication display screen control system as described above, the control method comprising the steps of:
s1, the upper computer sends the HDMI video signal to be displayed to the HDMI decoding chip;
s2, the HDMI decoding chip decodes the HDMI video signal, the decoded data comprises a line synchronizing signal, a field synchronizing signal, an enabling signal and RGB gray scale data, and then the data are sent to the data processing module;
s3, pixel multiplication data processing unit in the data processing module processes data of pixel multiplication, the processed data is buffered by DDR3 memory chip, then sent to HDMI coding chip to be coded again into HDMI video signal and output to the sending card;
and S4, the sending card decodes and boxes the video data, packs and sends the boxed effective video signals to the receiving card, and then the receiving card transmits the data to the driving IC to drive the display screen to display.
Preferably, the pixel multiplication display screen adopts an RGBG pixel arrangement mode, before the pixel multiplication data processing, the RGB gamma of 24bit is expanded into RGB brightness data of 39bit, and after the pixel multiplication data processing, the processed brightness data is restored to the gamma.
Preferably, the specific steps of the pixel-multiplied data processing are as follows:
SS1, after a frame of data comes, using a FIFO memory to temporarily store the data of the first line, when the second line of data is input, simultaneously reading the data of the first line buffered in the FIFO memory, and registering the values of the first two columns of the two lines of data through 4 registers to obtain the data matrix of the first two lines and two columns;
SS2, processing the single-color 8-bit data in the data matrix of the first two rows and two columns, and assigning values to the read data;
SS3, waiting for a clock cycle, when the data to be input and the data read out from the FIFO memory are respectively the data of the 4 th, 3 rd and 2 nd columns of the second and first rows, using 6 registers to register, processing the monochromatic 8bit data in the data matrix of the two rows and three columns, and assigning to the read data;
SS4, repeating the step SS3, after each column of data is processed, waiting for one clock cycle to process the next data processing again until the data processing of the first two rows is finished;
SS5, waiting for a line, sending the data of the third line to the second FIFO memory in the waiting process, reading the data of the 2 nd and 3 rd lines simultaneously when the 4 th line of data comes, carrying out data processing together with the data of the 4 th line, and assigning value to the read data; in the processing process, the input data is stored in a second FIFO memory, and simultaneously the data originally in the second FIFO memory is read out and stored in a first FIFO memory at the same time, so that the data processed each time are the input row data and the data of the previous two rows;
and SS6, repeating the step SS5, and after each line of data is processed, waiting for one line of time and then performing the next data processing until all data processing is completed.
Preferably, before the processed data is sent to the HDMI encoding chip, the method further includes the following steps:
recoding the data, using 3 registers of the FIFO memory to register the data coming from the moment and the previous two clock cycles, then performing bit splicing on the 3 32-bit data to splice into 96-bit data as the input of the asynchronous clock FIFO memory, and then setting the output of the FIFO memory to be 24-bit wide.
Preferably, the pixel multiplication display screen adopts a GB-BR-RG pixel arrangement, and the specific steps of the pixel multiplication data processing are:
firstly, after frame data comes, temporarily storing data of a first line by using an FIFO memory, inputting second line data and storing the second line data in a second FIFO memory, simultaneously reading the data of the first line cached in the first FIFO memory, and storing the current time of two current lines, the data of the last clock cycle and the data of the last clock cycle by using 6 registers;
when the third line of data comes, using 9 registers to store the data of the current time and the data of the previous clock period and the previous clock period of the two FIFO memories for reading and inputting the data, and forming a 3 x 3 data window;
and step three, setting a sign signal of calculation operation, pulling the sign signal of calculation operation high when the column counters of the even rows count to 3k-2 and 3k-1 (k is a positive integer), performing calculation operation and assignment operation, pulling the sign signal of calculation operation low at other moments, and assigning 0 of the corresponding digit to output data.
Preferably, the resolution of the pixel-multiplied display screen is m × n, after a frame of data comes, the rows and columns are counted according to the enable signal, when the enable signal is 1, an operation is added to the column counter every time the pixel clock rises, when the column is full of m-1, an operation is added to the row counter and the column counter is zeroed, representing the end of a line of data processing, the same operation is performed for the next line, when the row counter is full of n-1, the counters are all zeroed, representing the end of a frame of data processing.
A pixel multiplication display screen control apparatus comprising a pixel multiplication display screen control system as described above.
Compared with the prior art, the invention solves the problem that the data processing method of the pixel multiplexing technology can cause transmission bandwidth waste, and has the following specific beneficial effects:
1. the data transmission system provided by the invention realizes pixel multiplication processing of data by inserting the data processing module in a transmission path between the upper computer and the sending card, adopts the DDR3 memory chip to perform data caching, centralizes the dispersed data after processing, realizes reduction of data volume, can save transmission bandwidth between the sending card and the receiving card, load of the sending card and data processing capacity of the receiving card, and reduces the requirements of the system on the sending card and the receiving card, thereby greatly reducing the cost; the number of the wires between the sending card and the receiving card is reduced, the wires inside the box body of the device are regular, the short circuit risk is reduced, and the device is easy to maintain;
2. for a pixel-multiplied display screen employing an RGBG and GB-BR-RG pixel arrangement, the amount of data per frame that needs to be transmitted by the network cable between the sending card and the receiving card and the amount of data per frame that the receiving card needs to process are only 1/3 in existing control systems.
Drawings
FIG. 1 is a schematic diagram of a data transmission system for a pixel-multiplied display panel according to the present invention;
FIG. 2 is a schematic view of an RGBG pixel arrangement in example 8;
FIG. 3 is a diagram illustrating the amount of data of a frame of video after processing according to embodiment 9;
FIG. 4 is a schematic diagram of the GB-BR-RG pixel arrangement of example 11;
FIG. 5 is a diagram illustrating the amount of data of a frame of video after processing in embodiment 11;
FIG. 6 is a diagram showing the column counter and the count flag signals of the even rows in example 12.
Detailed Description
In order to make the technical solutions of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the specification of the present invention, and it should be noted that the following embodiments are only used for better understanding of the technical solutions of the present invention, and should not be construed as limiting the present invention.
Example 1.
The embodiment provides a data transmission system of a pixel multiplication display screen, which comprises an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a sending card, wherein the upper computer is used for sending an HDMI video signal to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit comprises two FIFO memories inside and is used for dynamically storing and reading data after each frame of data arrives to form a data matrix, calculating monochromatic pixel data according to a pixel multiplication data processing algorithm, sending the data to an HDMI coding chip, recoding the data into an HDMI video signal and outputting the HDMI video signal to a sending card.
The schematic structural diagram of the data transmission system in this embodiment is shown in fig. 1, and a data processing module is inserted in a transmission path between an upper computer and a sending card to realize pixel multiplication processing of data, so that transmission bandwidth between the sending card and a receiving card, loading of the sending card, and data processing capacity of the receiving card can be saved, requirements of the system on the sending card and the receiving card are reduced, and cost is greatly reduced; and the wiring quantity between the sending card and the receiving card is reduced, the wiring inside the device box body is regular, the short circuit risk is reduced, and the device is easy to maintain.
Example 2.
This embodiment is a further example of embodiment 1, and the data processing module further includes a DDR3 memory chip, configured to perform frame buffering on the processed data.
Since the effective data after data processing is loosely distributed in each frame of image, the system provided by this embodiment further uses the DDR3 memory chip to perform buffering of one frame of data, centralizing the distributed image data, and thus really achieving reduction of data.
Example 3.
This embodiment is a further illustration of embodiment 2, and the data processing module further includes a synchronizing signal generating unit configured to generate a line synchronizing signal, a field synchronizing signal, and an enable signal required for displaying data, and synchronize data read out from the DDR3 memory chip with the generated signals.
The synchronization signal generation unit of the present embodiment generates a timing signal required for displaying data, and then performs column counting according to an enable signal,
and reading the effective data obtained by processing in the time, sending the effective data to the data generated by the synchronizing signal generating unit, and finally sending the effective data to the HDMI data encoding chip to re-encode the effective data into an HDMI signal for outputting.
Example 4.
This embodiment is a further illustration of embodiment 1, and the decoded data includes a line synchronization signal, a field synchronization signal, an enable signal, and RGB grayscale data.
Example 5.
This embodiment is a further illustration of embodiment 1, and the data processing module is an FPGA processor.
Example 6.
The embodiment provides a pixel multiplication display screen control system, which comprises a receiving card, a driving IC and the data transmission system as described in any one of embodiments 1 to 5, wherein the receiving card is used for receiving effective video signals after being subjected to binning by a sending card in the data transmission system and then transmitting the effective video signals to the driving IC to drive the display screen to display.
In the control system of this embodiment, since the pixel multiplication processing of the data has been implemented on the transmission path from the host computer to the sending card, the transmission bandwidth from the sending card to the receiving card is greatly reduced, and the requirement on the data processing capability of the receiving card is reduced, thereby greatly reducing the cost.
Example 7.
The present embodiment provides a pixel-multiplication display screen control method, which applies the pixel-multiplication display screen control system according to embodiment 6, and the control method includes the following steps:
s1, the upper computer sends the HDMI video signal to be displayed to the HDMI decoding chip;
s2, the HDMI decoding chip decodes the HDMI video signal, the decoded data comprises a line synchronization signal, a field synchronization signal, an enable signal and RGB gray data, and then the data is sent to the data processing module;
s3, a pixel multiplication data processing unit in the data processing module performs pixel multiplication data processing on the data, the processed data is subjected to frame buffer by a DDR3 storage chip, and then the data is sent to an HDMI coding chip to be coded again into an HDMI video signal and output to a sending card;
and S4, the sending card decodes and boxes the video data, packs and sends the boxed effective video signals to the receiving card, and then the receiving card transmits the data to the driving IC to drive the display screen to display.
Example 8.
This embodiment is a further illustration of embodiment 7, in which the RGBG pixel arrangement shown in fig. 2 is adopted for the pixel multiplication display panel, before the data processing of pixel multiplication, gamma transformation is performed on RGB gray scale data of 24bit, and the RGB gray scale data is expanded into RGB brightness data of 39bit, and after the data processing of pixel multiplication, gamma inverse transformation is performed on the processed brightness data to restore the gray scale data.
In order to directly process the brightness in the data processing module, in this embodiment, the 24-bit RGB gray scale data is transformed and expanded into 39-bit RGB brightness data by gamma, and then the RGB brightness data is sent to the data processing module for processing, after entering the data processing module, the RGB brightness data is processed by a pixel multiplication module, and after the processing, the RGB brightness data is subjected to inverse gamma transformation to restore the processed brightness data into gray scale data, and then the data is buffered and transmitted.
Example 9.
This embodiment is a further example of embodiment 8, and the specific steps of the pixel multiplication data processing are as follows:
SS1, after a frame of data comes, using a FIFO memory to temporarily store the data of the first line, when the second line of data is input, simultaneously reading the data of the first line buffered in the FIFO memory, and registering the values of the first two columns of the two lines of data through 4 registers to obtain the data matrix of the first two lines and two columns;
SS2, processing the single-color 8-bit data in the data matrix of the first two rows and two columns, and assigning values to the read data;
SS3, waiting for a clock cycle, when the data to be input and the data read out from the FIFO memory are respectively the data of the 4 th, 3 rd and 2 nd columns of the second row and the first row, using 6 registers to register, processing the monochromatic 8bit data in the data matrix of the two rows and the three columns, and assigning to the read data;
SS4, repeating the step SS3, after each column of data is processed, waiting for one clock cycle to process the next data processing again until the data processing of the first two rows is finished;
SS5, waiting for a line, sending the data of the third line to the second FIFO memory in the waiting process, reading the data of the 2 nd and 3 rd lines simultaneously when the 4 th line of data comes, carrying out data processing together with the data of the 4 th line, and assigning value to the read data; in the processing process, the input data is stored in a second FIFO memory, and simultaneously the data originally in the second FIFO memory is read out and stored in a first FIFO memory at the same time, so that the data processed each time are the input row data and the data of the previous two rows;
and SS6, repeating the step SS5, and after each line of data is processed, waiting for one line of time and then performing the next data processing until all data processing is completed.
In the data processing described in this embodiment, after each column of data is processed, the next data processing is performed after waiting for one clock cycle, and after each row of data is processed, the pixel data is processed again after waiting for one row of time (the data processing for interlaced columns is implemented by parity of row and column counters), it can be found that the obtained virtual pixel image data is interlaced columns, that is, only even rows and even columns in one frame of image have valid pixel data, and output data in other places are assigned to zero.
Taking a 1080P resolution display screen as an example, according to a scheme of data processing on a receiving card in the prior art, the data volume of one frame of image required to be transmitted by a network cable between a sending card and the receiving card and the data volume required to be processed by the receiving card are both the data volume of a video source, that is, 1920 × 1080 × 24 bits =49766400 bits; by the pixel multiplication data processing described in this embodiment, and using the DDR3 memory chip to buffer one frame of data, the data reduction can be really realized by centralizing the dispersed image data, and as shown in fig. 3, the amount of data per frame that needs to be transmitted by the network cable between the sending card and the receiving card and the amount of data per frame that needs to be processed by the receiving card are only 1/3 of the former, that is, 960 × 540 × 32 bits =16588800 bits. Therefore, the method provided by the embodiment can save the transmission bandwidth and the data processing capacity of the receiving card.
Example 10.
This embodiment is a further example of embodiment 9, and before the processed data is sent to the HDMI encoding chip, the method further includes the following steps:
recoding the data, utilizing 3 registers of the FIFO memory to register the data coming from the moment and the previous two clock cycles, then performing bit splicing on the 3 32-bit data to form 96-bit data which is used as the input of the asynchronous clock FIFO memory, and then setting the output of the FIFO memory to be 24-bit wide.
Data obtained by processing display screen data in an RGBG pixel arrangement mode is 32bit, and is not in a standard RGB-888 format, an HDMI coding chip supporting 36bit (RGB-121212) is needed, 32bit data are dispersed into 36bit (every 8bit data are separated by 0 of 1 bit), then the data are sent to the HDMI coding chip to wait for coding transmission, the coded HDMI data are sent to a sending card to be decoded by HDMI, then a video binning algorithm is carried out to intercept an effective data area 1/3 and send the effective data area to a receiving card through an Ethernet cable, and the receiving card sends the processed data to a driving IC to drive an LED lamp on a lamp panel to display. This causes a certain increase in cost.
In this embodiment, a step of re-encoding data is added before the processed data is sent to the HDMI encoding chip, and a display screen with a resolution of 1080P is also taken as an example for explanation, before the card is sent to the box, the data in each row of the first 540 rows is only valid in the first 960 columns of data, and the valid data is 32 bits. If the precision of the data is not lost, the product of the bit width and the depth of the same line of data should be unchanged, considering that 960 × 32 bits =1280 × 24 bits, so in this embodiment, we use the characteristic of the FIFO memory that processes data across clock domains to re-encode the data, first use 3 registers to register the data coming from this time and the previous two clock cycles, then perform bit splicing on the 3 32-bit data (once every three clock cycles within the time when the data is valid), splice into a 96-bit data as the input of the asynchronous clock FIFO memory, then set the output of the FIFO memory to the bit width of 24 bits, so that the original line of data can be "stretched" from the depth of 960 bit width 32 bits to the data with the depth of 1280 bit width of 24 bits, then be sent to the encoding chip of the HDMI for encoding output, and the data area that needs to be intercepted on the sending card is also changed, the original 960 multiplied by 540 is changed into 1280 multiplied by 540, and the receiving card also needs to be decoded again when being processed and then is sent to a driving IC to drive an LED lamp panel to display. The embodiment only needs to use a standard coding chip, and the cost is further reduced.
Example 11.
This embodiment is a further example of embodiment 7, where the pixel multiplication display screen adopts a GB-BR-RG pixel arrangement mode, and the specific steps of the pixel multiplication data processing are as follows:
firstly, after frame data comes, temporarily storing data of a first line by using an FIFO memory, inputting second line data and storing the second line data in a second FIFO memory, simultaneously reading the data of the first line cached in the first FIFO memory, and storing the current time of two current lines, the data of the last clock cycle and the data of the last clock cycle by using 6 registers;
when the third line of data comes, using 9 registers to store the data of the current time and the data of the previous clock period and the previous clock period of the two FIFO memories for reading and inputting the data, and forming a 3 x 3 data window;
and step three, setting a sign signal of calculation operation, pulling the sign signal of calculation operation high when the column counters of the even rows count to 3k-2 and 3k-1 (k is a positive integer), performing calculation operation and assignment operation, pulling the sign signal of calculation operation low at other moments, and assigning 0 of the corresponding digit to output data.
Although each repeatable pixel element in the arrangement of the lamp panel is six sub-pixels of GB-BR-RG as shown in fig. 4, the pixel element may be divided into two pieces of BGR pixel data, so that the format of the pixel data before and after processing is not changed, and the processed pixel data is still 24bit data in the BGR-888 format and is output in the form of real pixels at the output end, so that the receiving card achieves the display effect of virtual pixels in the display mode of real pixels, thereby saving the data processing capability of the receiving card.
According to the multiplexing of the GB-BR-RG pixel arrangement mode, the data quantity output in the horizontal direction is 2/3 of the input data quantity after multiplexing calculation, and the data quantity output in the vertical direction is 1/2 of the input data quantity after multiplexing calculation, so that when the row counter counts to an even number and the column counter counts to 3k-2 and 3k-1, calculation operation and assignment operation are required. Taking a display screen with a resolution of 1080P as an example, according to a scheme of performing data processing on a receiving card in the prior art, the data volume of one frame of image required to be transmitted by a network cable from a sending card to the receiving card and the data volume required to be processed by the receiving card are both the data volume of a video source, that is, 1920 × 1080 × 24 bits =49766400 bits; after the pixel multiplication data processing described in this embodiment, and the DDR3 memory chip is used to perform buffering of one frame of data, so as to centralize the dispersed image data, which can really achieve the reduction of data, as shown in fig. 5, the amount of data per frame that needs to be transmitted by the network cable between the sending card and the receiving card and the amount of data per frame that needs to be processed by the receiving card are only 1/3 of the former, that is, 1280 × 540 × 24 bits =16588800 bits. Therefore, the method provided by the embodiment can save the transmission bandwidth and the data processing capacity of the receiving card.
Example 12.
This embodiment is a further illustration of embodiment 11, in which the resolution of the pixel-multiplied display screen is m × n, after a frame of data arrives, as shown in fig. 6 (the rst _ n reset signal in the figure is used to assign the system signal to an initial value of 0 when a system fails or has an operation error), rows and columns are counted according to the enable signal, when the enable signal is 1, an adding operation is performed on the column counters every clk pixel clock rises, when the column counters of even rows count to 3k-2 and 3k-1, the calculation flag signal is pulled high, the calculation operation and the assignment operation are performed, and when the rest of time, the calculation operation flag signal is pulled low, and 0 of the corresponding number of bits is assigned to the output data. When the column is full of m-1, the row counter is incremented by one and the column counter is reset to zero, representing the end of data processing for one row, and when the row counter is full of n-1, the counters are all reset to zero, representing the end of data processing for one frame.
Since the counter starts counting from 0, for example, in a display screen with a resolution of 1920 × 1080, 1080P, when the enable signal is 1, the column counter is incremented every pixel clock, the row counter is incremented 1919, and the column counter is zeroed, which represents the end of one line of data, and the row counter is also zeroed 1079, which represents the end of one frame of data.
Example 13.
This embodiment provides a pixel-multiplication display screen control device including the pixel-multiplication display screen control system according to embodiment 6.
In the pixel multiplication display screen control device provided by the embodiment, the applied system realizes virtual processing of data on a transmission path from the upper computer to the sending card, so that the transmission bandwidth from the sending card to the receiving card, the carrying capacity of the sending card and the data processing capacity of the receiving card are saved, the requirements of the system on the sending card and the receiving card are reduced, and the cost is greatly reduced; the wiring quantity between the sending card and the receiving card is reduced, wiring inside the box body of the device is regular, short circuit risks are reduced, and the device is easy to maintain.
Claims (13)
1. A data transmission system of a pixel multiplication display screen is characterized by comprising an upper computer, an HDMI decoding chip, an HDMI coding chip, a data processing module and a sending card, wherein the upper computer is used for sending an HDMI video signal to be displayed to the HDMI decoding chip; the HDMI decoding chip is used for decoding the HDMI video signal and sending the decoded data to the data processing module; the data processing module comprises a pixel multiplication data processing unit for carrying out pixel multiplication data processing on each frame of data; the pixel multiplication data processing unit comprises two FIFO memories inside and is used for dynamically storing and reading data after each frame of data arrives to form a data matrix, calculating monochromatic pixel data according to a pixel multiplication data processing algorithm, sending the data to an HDMI coding chip, recoding the data into an HDMI video signal and outputting the HDMI video signal to a sending card.
2. The data transmission system of a pixel-multiplied display screen of claim 1, wherein said data processing module further comprises a DDR3 memory chip for frame buffering of processed data.
3. The data transfer system for the pixel-multiplied display screen according to claim 2, wherein the data processing module further comprises a synchronizing signal generating unit for generating a line synchronizing signal, a field synchronizing signal and an enable signal required for displaying data, and synchronizing data read out from the DDR3 memory chip with the generated signals.
4. The data transmission system of a pixel-multiplied display screen of claim 1, wherein said decoded data comprises a line synchronization signal, a field synchronization signal, an enable signal and RGB gray scale data.
5. The data transmission system of a pixel-multiplied display screen of claim 1, wherein said data processing module is an FPGA processor.
6. A pixel multiplication display screen control system, which is characterized by comprising a receiving card, a driving IC and a data transmission system according to any one of claims 1 to 5, wherein the receiving card is used for receiving effective video signals which are subjected to binning by a sending card in the data transmission system and then transmitting the effective video signals to the driving IC to drive the display screen to display.
7. A pixel-multiplication display screen control method, characterized by applying the pixel-multiplication display screen control system according to claim 6, the control method comprising the steps of:
s1, the upper computer sends the HDMI video signal to be displayed to the HDMI decoding chip;
s2, the HDMI decoding chip decodes the HDMI video signal, the decoded data comprises a line synchronization signal, a field synchronization signal, an enable signal and RGB gray data, and then the data is sent to the data processing module;
s3, pixel multiplication data processing unit in the data processing module processes data of pixel multiplication, the processed data is buffered by DDR3 memory chip, then sent to HDMI coding chip to be coded again into HDMI video signal and output to the sending card;
and S4, the sending card decodes and boxes the video data, packs and sends the boxed effective video signals to the receiving card, and then the receiving card transmits the data to the driving IC to drive the display screen to display.
8. The method for controlling the pixel multiplication display screen according to claim 7, wherein the pixel multiplication display screen adopts an RGBG pixel arrangement mode, before the data processing of the pixel multiplication, gamma conversion is performed on 24-bit RGB gray scale data, the RGB gray scale data are expanded into 39-bit RGB luminance data, and after the data processing of the pixel multiplication, gamma inverse conversion is performed on the processed luminance data, and the processed luminance data are restored into gray scale data.
9. The pixel-multiplied display screen control method according to claim 8, wherein the data processing of the pixel multiplication comprises the following specific steps:
SS1, after a frame of data comes, using a FIFO memory to temporarily store the data of the first line, when the data of the second line is input, simultaneously reading the data of the first line buffered in the FIFO memory, and registering the values of the first two columns of the data of the two lines through 4 registers to obtain the data matrix of the first two lines and the first two columns;
SS2, processing the single-color 8-bit data in the data matrix of the first two rows and two columns, and assigning values to the read data;
SS3, waiting for a clock cycle, when the data to be input and the data read out from the FIFO memory are respectively the data of the 4 th, 3 rd and 2 nd columns of the second and first rows, using 6 registers to register, processing the monochromatic 8bit data in the data matrix of the two rows and three columns, and assigning to the read data;
SS4, repeating the step SS3, after each column of data is processed, waiting for one clock cycle to process the next data processing again until the data processing of the first two rows is finished;
SS5, waiting for a line, sending the data of the third line to the second FIFO memory in the waiting process, reading the data of the 2 nd and 3 rd lines simultaneously when the 4 th line of data comes, carrying out data processing together with the data of the 4 th line, and assigning value to the read data; in the processing process, the input data is stored in a second FIFO memory, and simultaneously the data originally in the second FIFO memory is read out and stored in a first FIFO memory at the same time, so that the data processed each time are the input row data and the data of the previous two rows;
and SS6, repeating the step SS5, and after each line of data is processed, waiting for one line of time and then performing the next data processing until all data processing is completed.
10. The pixel-multiplied display screen control method according to claim 9, wherein before the processed data is sent to the HDMI encoding chip, the method further comprises the following steps:
recoding the data, using 3 registers of the FIFO memory to register the data coming from the moment and the previous two clock cycles, then performing bit splicing on the 3 32-bit data to splice into 96-bit data as the input of the asynchronous clock FIFO memory, and then setting the output of the FIFO memory to be 24-bit wide.
11. The pixel multiplication display screen control method according to claim 7, wherein the pixel multiplication display screen adopts a GB-BR-RG pixel arrangement, and the specific steps of the pixel multiplication data processing are:
firstly, temporarily storing data of a first line by using an FIFO memory after frame data come, storing second line data in a second FIFO memory when the second line data are input, simultaneously reading the data of the first line cached in the first FIFO memory, and storing the current time of two current lines, the data of a previous clock cycle and the data of the previous clock cycle by using 6 registers;
when the third row of data comes, using 9 registers to store the data of the current time and the data of the previous clock period and the previous clock period read by two FIFO memories to form a 3 x 3 data window;
and step three, setting a sign signal of calculation operation, pulling the sign signal of calculation operation high when the column counters of the even rows count to 3k-2 and 3k-1 (k is a positive integer), performing calculation operation and assignment operation, pulling the sign signal of calculation operation low at other moments, and assigning 0 of the corresponding digit to output data.
12. The pixel-multiplied display screen control method according to claim 11, wherein the resolution of the pixel-multiplied display screen is mxn, after a frame of data comes, the rows and columns are counted according to the enable signal, an adding operation is performed to the column counter every time the pixel clock rises when the enable signal is 1, an adding operation is performed to the row counter when the column is full of m-1 and the column counter is zeroed, which represents the end of a line of data processing, the same operation is performed to the next line, the counters are all zeroed when the row counter is full of n-1, which represents the end of a frame of data processing.
13. A pixel multiplication display control apparatus comprising the pixel multiplication display control system of claim 6.
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